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Physical Verification Engineer - ASIC/SoC

4 - 6 years

0 Lacs

chennai tamil nadu india

Posted:1 week ago| Platform: Linkedin logo

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Skills Required

verification design compliance drc lvs checks layout resolve extraction cad support automation audits validator cadence synopsys debugging communication

Work Mode

On-site

Job Type

Full Time

Job Description

Job Title :

Physical Verification Engineer

Location :

Chennai, India

Experience :

4- 6 Years

Notice Period :

Immediate to 15 Days

Job Overview

We are seeking a skilled Physical Verification Engineer to join our dynamic VLSI design team in Chennai. The ideal candidate will have hands-on experience in performing physical verification of complex SoC and ASIC designs, ensuring design compliance with foundry requirements and achieving sign-off quality results.

Key Responsibilities

  • Execute physical verification tasks including DRC, LVS, ERC, and Antenna checks using industry-standard tools.
  • Collaborate with layout, P&R, and design teams to debug and resolve verification issues efficiently.
  • Perform parasitic extraction (PEX) and validate results against design specifications.
  • Work closely with foundry and CAD teams to ensure design rule compliance and maintain verification decks.
  • Support the tape-out process, ensuring all verification milestones are completed on schedule.
  • Develop and maintain verification scripts and automation flows to enhance productivity.
  • Document verification procedures, methodologies, and results for design audits and reviews.

Required Skills And Qualifications

  • 4- 6 years of hands-on experience in Physical Verification (PV) for ASIC/SoC designs.
  • Proficiency in tools such as Calibre, IC Validator (ICV), or Pegasus.
  • Strong understanding of semiconductor process technologies and DRC/LVS methodologies.
  • Experience with Cadence Virtuoso and Synopsys/Cadence flows is preferred.
  • Excellent problem-solving, debugging, and communication skills.
(ref:hirist.tech)

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