1253 Physical Design Jobs - Page 50

: To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimization, routing, a...

Physical Design Manager role managing team of 10+ members for SOC designs. Key Responsibilities :- Manage Synthesis, Physical Design, and timing teams Lead internal and external resources Ensure SOC chip completion on schedule Oversee Physical implementation Guide Synthesis and Power Reduction efforts Handle complex SOC management Work with 7nm and sub-7nm projects Manage Full Chip Floor planning Ensure on-time delivery Drive improvements and problem-solving Qualifications & Skills Education:- BE/B.Tech/ME/M.TECH in ECE/EEE Experience:- 12+ years (3+ years in people management) Skills: -Team management, technical problem solving, Communication skills, Presentation skills, Tool expertise (Syn...

Join SanDisk India as a Technical ASIC Project Leader and take charge of developing cutting-edge ASICs that power the next generation of SD cards for imaging, gaming, mobile, and data storage. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities: Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisk s storage solutions. Drive Cross-Fu...

We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements and translate them into precise layouts. Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently. Work closely with the physica...

Position Overview: We are seeking a highly skilled and experienced Staff Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities: - Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Development & Review activities. - D...

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, implement, and execute the Physical design and verification of processing subsystems IP, resulting in meeting the signoff criteria for tapeout. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and Implementation in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. PREFERRED EXPERIENCE: 7+ Years of experience in relevant domain. Experienced with Blocklevel and Tople...

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate...

Design analog and mixed-signal system blocks of DC-DC converter power stages and POL ICs Job Description In your new role you will: Design analog and mixed-signal system blocks of DC-DC converter power stages and POL ICs including POR, Bandgap, LDO, Oscillators, drivers,current sensing, test modes etc. Assist in defining the requirements for analog and mixed-signal blocks , aligning them with IP Module architecture, and ensuringcompliance with requirements through documentation. Provide essential support to physical design engineers, post-silicon validation, production testing, and other critical activities extending beyond the design phase. Communicates with cross functional/inter disciplin...

About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications. What You Can Expect In this role based in Bangalore , you will work with a global team on both the physical design of complex c...

Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include global corporations across multiple industries, national labs, and top-tier healthcare systems. In January, we announced a multi-year, multi-million-dollar partnership with Mayo Clinic, underscoring ou...

Positions are open for full-time in the ares of physical design and integration from sub-system level to full chip level, involving all aspects of physical design partition and integration functions. Responsibilities Own sub-system level or full chip level physical design integration, particularly focusing on design partition/integration, pin arrangement, feedthrough creation, clock/power grid planning. Be responsible for design integration and signoff coordination at sub-system or full chip level Evaluate/implementation physical design for channel, particularly for route ability and repeater planning Work with block or sub-system owners across the whole design cycles to drive design closure...

We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform f loorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages. Drive physical verification (DRC, LVS, antenna checks) and reso...

We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success. Key Responsibilities Own and drive timing closure for multiple blocks or full-chip designs from synthesis through tape-out. Develop and maintain timing constraints (SDC) for synthesis, place-and-route, and sign-off flows. Perform setup, hold, recovery, and removal analysis using industry-standard STA tools. Analyze timing reports and debug violations, providing gu...

MTS SILICON DESIGN ENGINEER THE ROLE: AMD is looking for an experienced Analog Mixed Signal engineer to take on the technical challenges within the I/O and PHY Technology Group. This group delivers critical Mixed Signal IP such as highly configurable high-speed memory I/Os/PHYs and Chiplet Interconnect IP (e.g. UCIE) to various Business Units/SoCs within AMD. The ideal candidate will get to work with circuit and FE architects to accurately model the analog digital interface boundary of high speed mixed signal IPs to accomplish timing integrity goals. KEY RESPONSIBILITIES: Analyze timing constraints for complicated static timing analysis (STA) paths including multistage generated clocks, ZCPs...

Join SanDisk India as a Technical ASIC Project Leader and take charge of developing the cutting-edge ASICs that power the next generation of the USB storage solutions. This is a high-impact leadership role where your technical expertise and strategic vision will drive projects from concept to mass production. Key Responsibilities: Lead Full-Cycle SoC Development: Own the end-to-end development of high-performance ASIC controllers, from architecture definition to production ramp-up. Translate Product Vision into Technical Execution: Collaborate with product, firmware, and system teams to define ASIC requirements aligned with SanDisk s storage solutions. Drive Cross-Functional Collaboration: P...

What you ll do: Will be responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation. Prefer sound knowledge in EDA tools such as DC, ICC2, Cadence Innovus, STAR-RC, PT-SI, Verplex, Quartz, Calibre, internal tools & flow, etc. Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow. Experienced in design au...

Altera is looking for a talented and driven Silicon Design Engineering Manager to lead and inspire a multidisciplinary silicon design team. In this critical role, you will manage design engineers across multiple functional domains including logic design, verification, circuit design, and physical implementation for cutting-edge IP, subsystems, SoCs, and discrete chips. You ll be at the forefront of Altera s product innovation, driving high-quality silicon solutions that meet power, performance, area, and cost objectives. Key Responsibilities: Lead and manage a team of silicon design engineers across multiple disciplines and development phases. Drive end-to-end development of IP blocks, subsy...

Lead/manage a team of design verification engineers responsible for IP and SoC design verification. Deploys and manages leading silicon design verification processes, procedures, verification tools, and technologies based on latest best industry practices. Works with design, microarchitecture, and post-silicon validation teams to identify design bugs and improve overall microarchitecture. Collaborates with program leaders on the verification delivery and regression metrics against milestone requirements. Understands security milestone expectations and works with SoC security validation teams to incorporate security-related testing through validation, hackathon reviews, and new validation tec...

Position: Physical Design Engineer (IS100FF RM 3490) Responsibilities Required Experience: Lead Netlist to-GDSII implementation, including floorplanning, power planning, placement, CTS, routing, and full signoff (DRC, LVS, STA, EMIR). Own and drive PnR execution and closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification challenges. Proficient with industry-standard tools: Cadence Innovus, Synopsys ICC2, and scripting in Tcl, Perl, Python for automation and flow development. Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe. Collaborate cross-functionally w...

Where R&D Engineering, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview . Play Video Job Description Category Engineering Hire Type Employee Job ID 12354 Remote Eligible No Date Posted 10/08/2025 Alternate Job Titles: R&D Staff Engineer We Are: . You Are: You are a motivated and forward-thinking engineering professional eager to make a meaningful impact in the semiconductor industry. You thrive in collaborative environments and are passionate about solving complex technical challenges. Your expertise in simulation and verification flows, coupled with a strong f...

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s fueled by great technology and amazing people. Today, we re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We a...

SMTS SILICON DESIGN ENGINEER T HE ROLE : As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: The ideal candidate will have experience developing RTL for IP or subsystems and understand architectural specifications. Responsibilities include IP and subsystem design, integrating multiple IPs, performing quality checks and working collaboratively with the IP/SoC team. K EY RESPONSIBLITIES : Design of IP and subsystems with integration of AMD and o...

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It s a unique legacy of innovation that s fueled by great technology and amazing people. Today, we re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what s never been done before takes vision, innovation, and the world s best talent. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We a...

Principal Physical Design Verification / ESD Engineer in Bangalore, KA, India Principal Physical Design Verification / ESD Engineer Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a...

Principal Physical Design Verification / ESD Engineer in Pune, MH, India Principal Physical Design Verification / ESD Engineer Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a pass...