We are seeking an experienced Lead Physical Design Engineer to take ownership of Place-and-Route (PNR) for complex flat SoC designs using Cadence flow. You will lead physical implementation from floorplanning to timing closure, collaborating closely with RTL, STA, DFT, and verification teams. Key Responsibilities Lead physical design execution for flat SoC projects from RTL handoff through GDSII. Perform f loorplanning, partitioning, power planning, and clock tree synthesis (CTS). Execute placement, routing, optimization, and sign-off using Cadence Innovus or equivalent tools. Develop and maintain SDC constraints for PNR stages. Drive physical verification (DRC, LVS, antenna checks) and resolve violations. Perform congestion analysis and optimization for flat SoC designs. Work with methodology teams to improve PNR flow and scalability. Mentor junior engineers on PNR best practices and advanced Cadence Innovus features. Qualifications Must-Have: Bachelor s or Master s degree in Electrical/Electronics/Computer Engineering or related field. 10-12 years of hands-on physical design and PNR experience. Proven ability to handle flat SoC designs in Cadence flow Strong knowledge of floorplanning, CTS, routing, optimization, and sign-off closure. Solid understanding of STA, SDC creation, and ECO flows for physical implementation. Prior technical leadership or mentoring experience. Nice-to-Have: Automotive semiconductor experience Low-power implementation (UPF/CPF). Experience with scripting ( Tcl, Perl, Python ) for automation.
We are looking for a highly experienced DFT Lead Engineer to take ownership of Design-for-Test (DFT) architecture, implementation, and sign-off for complex flat SoC designs. This role requires deep expertise in PNR (Place-and-Route) within Cadence flow. Key Responsibilities Lead DFT strategy and implementation for flat SoC designs from RTL through tape-out. Develop and integrate test architectures including scan insertion, MBIST, LBIST, JTAG, and boundary scan. Work closely with the PNR team to ensure DFT structures are timing- and placement-aware. Drive test mode constraint creation and ensure compatibility with functional modes. Perform gate-level simulations for test logic verification. Own ATPG pattern generation and coverage analysis for manufacturing test. Lead reviews and mentor junior DFT engineers in best practices. Qualifications Must-Have: Bachelor s or Master s degree in Electrical/Electronics/Computer Engineering or related field. 10 12 years of hands-on DFT experience in ASIC/SoC projects. Proven PNR experience to handle flat SoC designs in Cadence flow Strong knowledge of scan insertion, MBIST, LBIST, boundary scan, JTAG, and related standards (IEEE 1149.x). Experience with Synopsys DFT Compiler, Tessent, or equivalent DFT tools. Good understanding of STA and SDC constraints for test modes. Familiarity with ECO flows in post-PNR stages for DFT fixes. Nice-to-Have: Automotive semiconductor industry experience Proficiency in scripting ( Tcl, Perl, Python ) for automation. Low-power DFT experience with UPF/CPF. Exposure to signal integrity considerations for test structures. Prior technical leadership or mentoring experience.
We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet performance, power, and area targets while achieving first-pass silicon success. Key Responsibilities Own and drive timing closure for multiple blocks or full-chip designs from synthesis through tape-out. Develop and maintain timing constraints (SDC) for synthesis, place-and-route, and sign-off flows. Perform setup, hold, recovery, and removal analysis using industry-standard STA tools. Analyze timing reports and debug violations, providing guidance to physical design, RTL, and DFT teams. Work closely with clock, power, and signal integrity engineers to address timing and noise-related issues. Lead STA reviews with design and physical implementation teams, ensuring issues are tracked and resolved. Collaborate with methodology teams to enhance STA flows and timing sign-off quality. Contribute to methodology improvements for STA and PNR flows. Mentor and guide junior engineers in STA and timing-driven PNR techniques. Qualifications Bachelor s or Master s degree in Electrical/Electronics/Computer Engineering or related field. 10-12 years of hands-on experience in STA for large, complex ASIC/SoC designs. Proven PNR experience to handle flat SoC designs in Cadence flow. Solid understanding of multi-mode, multi-corner (MMMC) timing analysis. Proficiency in timing constraints writing (SDC), clock domain crossing (CDC) considerations, and asynchronous interface analysis. Experience with ECO timing closure and post-route sign-off. Prior experience in team leadership or technical mentoring . Nice-to-Have: Familiarity with scripting languages ( Tcl, Perl, Python ) for flow automation. Exposure to low-power design techniques (UPF/CPF). Knowledge of signal integrity, EM/IR drop impacts on timing. Experience in the automotive industry is a plus Send Us A Message Recaptcha requires verification. I'm not a robot US Office 5005 W Royal Ln Suite 224, Irving, TX 75063 India Office Plot No 133, Sri Hari Nilayam, Vaishali Nagar, Madinaguda, Hyderabad - 500049