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Technologist, ASIC Development Engineering

Technologist, ASIC Development Engineering

Western Digital

12 - 15 years

40 - 50 Lacs

bengaluru

Posted:None| Platform:

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Skills Required

electrical engineering automation asic layout design chip design analog mixed signal debugging signal integrity physical design

Work Mode

Work from Office

Job Type

Full Time

Job Description

We are looking for technically sound and highly skilled High-speed SERDES IO PHY Layout designer with 12-15 years of experience. Apart from Serdes PHY Layout, the ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems.

Key Responsibilities:

Develop and optimize Serdes PHY, analog and mixed-signal IC layouts, ensuring high performance and manufacturability.
Collaborate with design engineers to understand design requirements and translate them into precise layouts.
Strong experience in debugging DRC, ERC, LVS, EMIR and PERC issues independently.
Work closely with the physical design team to integrate custom blocks into the overall chip design.
Identify and resolve layout-related issues, providing creative solutions to meet design specifications.
Conduct design reviews and provide technical feedback to improve layout practices and methodologies.
Stay up-to-date with industry trends, tools, and technologies to continuously enhance layout processes.

Qualifications

12-15 years of experience in Serdes Phy, Analog and Mixed-signal IC layout design.
Proficiency in layout tools such as Cadence, Synopsys, or Mentor Graphics.
Hands-on experience with custom layout design for various Serdes Phy, Analog and IO circuits is required, including expertise in Bandgap references, LDOs, Clocking circuits, GPIOs, DDR IOs.
Familiarity with custom digital layout (i.e. high speed logic paths).
Knowledge of signal integrity issues (i.e. clock/data routes, differential routing, shielding).
Strong understanding of analog/IO design principles, including circuit performance and parasitic effects.
Aware of layout techniques to mitigate ESD, latch-up issues.
Holds advanced knowledge of CMOS and FinFET technologies and their impact on design and performance issues in deep sub-micron process nodes, specifically 5nm and below.
Experience with layout concepts that incorporate reliability considerations, including techniques for managing electromigration (EM), IR drop, and self-heating.
Experience with layout optimization for power, performance, and area (PPA) metrics.
Excellent problem-solving skills and attention to detail.
Effective communication and teamwork abilities.

Preferred Skills:

Knowledge of scripting languages (e.g., Skill,TCL and SVRF) for automation tasks.

Qualifications

Bachelor s or Master s degree in Electronics or Electrical Engineering

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Technologist, ASIC Development Engineering