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Sourceright Technologies
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Physical Design Engineer

Physical Design Engineer

Sourceright Technologies

10 - 15 years

9 - 14 Lacs

bengaluru

Posted:None| Platform:

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Skills Required

sta automation dft packaging physical verification perl pcie floor planning physical design python

Work Mode

Work from Office

Job Type

Full Time

Job Description

Position: Physical Design Engineer (IS100FF RM 3490)

Responsibilities Required Experience:

Lead Netlist to-GDSII implementation, including floorplanning, power planning, placement, CTS, routing, and full signoff (DRC, LVS, STA, EMIR).
Own and drive PnR execution and closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification challenges.
Proficient with industry-standard tools: Cadence Innovus, Synopsys ICC2, and scripting in Tcl, Perl, Python for automation and flow development.
Deep expertise in low-power design (UPF/CPF), clock gating, logic optimization, and integration of high-speed interfaces like DDR and PCIe.
Collaborate cross-functionally with RTL, STA, DFT, verification, and packaging teams to ensure smooth integration and closure.
Manage comprehensive signoff processes, including STA (PrimeTime SI), EM/IR analysis (RedHawk), and physical verification (Calibre); handle ECOs and DRC/LVS clean-up.
Provide technical leadership, mentor junior engineers, and contribute to successful tape outs at advanced technology nodes (7nm, 5nm and 3nm).

Job Category:

Others

Job Type:

Full Time

Job Location:

Bangalore

Experience:

10+ Years

Notice period:

0-15 days

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