1253 Physical Design Jobs - Page 33

We are looking for Physical Design Engineers with Exp in Low Power Verification with above 10yrs Exp

Plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Collaborate with cross-functional teams to develop solutions and meet performance requirements. Hands-on Physical Design (PD) execution at block/SoC level with a focus on Power, Performance, Area (PPA) improvements. Strong understanding of technology and PD Flow Methodology enablement. Work with Physical Design engineers to roll out robust methodologies, identify areas for flow improvement (area/power/performance/convergence), develop plans, and deploy/support them. Provide tool support a...

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Role: SOC level Mixed Signal and High Speed Interfaces verification Eng...

Job Specs : We are seeking a highly skilled and motivated ASIC Physical Design Experts to join the offshore development teams of our group companies. You will work with the rapidly expanding team which focuses on the research and development of ASIC Design IPs for Silicon Lifecycle Management, driving innovation and excellence in chip design and verification. You will work alongside a talented and dedicated group of engineers, all committed to pushing the boundaries of technology and delivering top-notch solutions to our customers. Work Location and Expertise: Bangalore : 4 Years 15 Years Beijing : 8 Years 10 Years Chennai : 3 Years 6 Years Vietnam : 8 Years 10 Years Taiwan : 8 Years 10 Year...

As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on block level and SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work with PD team on subsystem and block level physical verification and signoff Work closely with physical design imple...

Front-End Silicon Design & Integration (FEINT) Engineer The role: A Front-End Silicon Design and Integration (FEINT) Engineering role in our Security IP (SECIP) team, where a large number of embedded micro-processor subsystems, hardware accelerators and other IPs vital to improve system performance and functionality are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, ...

Silicon Labs (NASDAQ: SLAB) is the leading innovator in low-power wireless connectivity, building embedded technology that connects devices and improves lives. Merging cutting-edge technology into the world s most highly integrated SoCs, Silicon Labs provides device makers the solutions, support, and ecosystems needed to create advanced edge connectivity applications. Headquartered in Austin, Texas, Silicon Labs has operations in over 16 countries and is the trusted partner for innovative solutions in the smart home, industrial IoT, and smart cities markets. Learn more at www.silabs.com . Job Description The position involves design verification of next generation modem sub systems (which ha...

Job Responsibilities : Process & quality monitoring for respective technology plants Identify and analyse deviations Perform root cause analysis Propose corrective action and track the status of process improvement Identify opportunities for profit improvement Identify opportunities for product quality enhancement Process design calculations for the improvement schemes Develop process design package using appropriate tools Participate in commercial plant trials Understand and evaluate basic engineering design documents Participate in plant performance audits as per set guidelines Participate in Critical PHAs and turnaround activities of the related plants Validate MoCs to ensure specified st...

With this position you will be in our Technical Ladder: a special career path for those who share innovative ideas, demonstrate comprehensive technical knowledge, show thought leadership, possess problem solving abilities and are able to create business value, Job Description In your new role you will: Contribute to highly complex designs in a multi-site organization covering all aspects of Structural and Physical SoC Design Be responsible for the physical design of multifarious digital SoCs Translate requirements into layout specifics using our state-of-the-art EDA tools and flows Work independently in different phases of the RTL2GDS flow: With focus on (one or many) Synthesis and equivalen...

Job Responsibilities : Education Requirement : Experience Requirement : Skills & Competencies : Work Output Define project charters and implementation plan, Develop project proposal for management approval & budget Manage projects within allocated budget & resources available, Coordinate with key stakeholders at sites for implementation & embedding of the new process/system, Coordinate with partner/vendor for project execution Actively contribute in managing Knowledge Assets, Evaluate information gathered through workshops & surveys and incorporate in process description, Identify the competitive commercial solution for recommendation, Communicate with internal teams & external clients to de...

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL de...

DFT Implementation: Strong expertise in implementing DFT architectures, including Scan Insertion, ATPG (Automatic Test Pattern Generation), and MBIST/ LBIST for SoC designs. Test Coverage Optimization: Experience in optimizing test coverage while minimizing test cost and pattern volume. Scan & Compression Techniques: Proficient in scan chain design, scan compression techniques, and reducing test data volume. Boundary Scan (IEEE 1149.1): In-depth knowledge of boundary scan standards and Fault Models: Familiarity with various fault models (stuck-at, transition, path delay, etc.) and their application in test generation. DFT Tools: Hands-on experience with DFT tools like Synopsys TetraMAX, Ment...

Physical Design Implementation: Experience in block and SoC level PD implementation, covering the entire flow from netlist to GDSII, including PnR/APR. Low Power Design: Proficient in low power design techniques. Flow Expertise: Hands-on experience with floorplanning, power planning, placement, CTS (Clock Tree Synthesis), routing, extraction, and DFM (Design for Analysis Skills: Strong ability to perform congestion and timing analysis, with a focus on achieving better QoR (Quality of Results). Sign-Off Expertise: In-depth knowledge of sign-off processes including STA (Static Timing Analysis), DRC/LVS/Antenna/ERC checks, power analysis, IR/EM analysis, LEC (Logic Equivalence Checking), and EC...

BSEE and at least 5 years of prior experience are required. MSEE and at least 3 years of previous experience are strongly preferred. Prior experience in timing and or RTL design of high-speed interfaces. Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP Tape Outs. Knowledge of the IP/SoC level timing closure flow and methodology. Strong command of Verilog/System Verilog language. Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies. Ability to handle multiple projects/tasks successfully. Experience in IP/ASIC timing constraints generation and timing closure. Expertise in ...

Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes. Must-Have Hands-on experience on Full chip floor plan, Full chip PNR, and Design Partitioning. Hands-on experience in IO Planning, Bump Plan and RDL Routing. Experience in ECOs, Synthesis and STA, and Power analysis. Hands-on experience in Physical verification. Hands-on experience on 7nm and 10nm technology nodes. Good-to-Have Effective communication skills to interact with cross-functional teams.

Role & responsibilities Those who had a chance to work on CPU, GPU and / or NPU would be better on 3 or 5 nm Technology . Experience Levels would 4-8 years.

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency powerconversion for applications using GaN devices. D esign and verify pre-silicon analog/mixed-signal integrated circuitblocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog and mixed-signalblocks , aligning them with IP Module architecture, and ensuri...

Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies, with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Job Description In your new role you will: Design analog and mixed-signal modules in CMOS and Smart PowerTechnologies , with a particular focus on achieving high-efficiency power conversion for applications using GaN devices. Design and verify pre-silicon analog/mixed-signal integrated circuit blocks , including incorporating features for testing and quality assurance, and providing support for top-level integration. Assist in defining the requirements for analog andmixed-signal blocks , aligning them with IP Mod...

You have a passion for modern, complex processor architecture, digital design as we'll as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi site environment are keys to being successful in this role. KEY RESPONSIBILITIES: RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design Architect and design of power management features, cache, coherency. Design optimization for implementing power efficient IP, implementing the RTL using lo...

As a member of the Radeon Technologies Group, you will help bring to life cutting-edge designs. As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with senior silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Implementation and verification of DFT architecture and features Scan insertion and ATPG pattern generation ATPG patterns verification with gate-level simulation Test coverage and test ...

ARF Design Pvt Ltd is looking for Physical Design Engineer/Lead to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skillsStrong analytical and problem-solving skillsFamiliarity with scripting languages, such as Tcl, Perl, or Python

: We are looking for a highly skilled & experienced PD expert to join our Flows & Methodologies team. The candidate must be experienced, hands-on and have robust understanding of physical design including Floorplan, Power-plan, Place & Route, UPF, CTS. This role requires strong analytical skills, attention to detail, and the ability to work collaboratively with cross-functional teams. Proficiency in relevant EDA tools and a solid understanding of digital design principles are essential for success in these positions Scope of Responsibilities: As part of the Design Enablement team of the organization, you need to work closely with SoC cross functional teams to develop and define Physical Desi...

Roles and Responsibilities Good experience in PD execution of multiple medium to High critical blocks/HMs from Netlist to GDSII Develop and qualify the methodology and implementation flow in advanced technologies like 14nm and below. Well versed with FC/Innovus tools and good understanding of place/cts/Route critical settings Develop expertise in ASIC Synthesis, Floor Planning, STA (Static Timing Analysis), and other relevant technologies. Good experience in Low power designs Conduct thorough analysis of designs to identify potential issues and implement solutions. Perform physical design activities including floor planning, PNR (Physical Netlist) creation, and timing closure using Innovus t...

Your Job The engineer will be responsible for doing physical design implementation, timing closure, and Physical verification at the block level. Job Responsibilities Execute block-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Need experience in full chip physical design such as integration of blocks, top level floorplanning, clock tree synthesis, timing constraints development and convergence. I/O placement and constraints. Experience ...

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are highly adept at collaboration amo...