1253 Physical Design Jobs - Page 37

Introduction Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. Your role and responsibilities Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing Close the design to meet timing, power budget and area Implement ECO's to address functional bugs and timing violations Team player, with good problem solving and communication skills Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 58 years industry experience in physical design methodology Good knowledg...

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test ca...

Wipro Limited (NYSEWIT, BSE507685, NSEWIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role _x000D_ Role Purpose The purpose of this...

About The Role Role Purpose The purpose of this role is to perform the development of VLSI system by defining the various functionalities, architecture, layout and implementation for a client ? Do 1. Conduct verification of the module/ IP functionality and provide customer support a. Understand the architecture of the module or the IP and create verification environment and the development plan as per Universal Verification Methodology b. Create test bench development and test case coding of the one or multiple module c. Write the codes or check the code as required d. Execute the test cases and debug the test cases if required e. Conduct functional coverage analysis and document the test ca...

Wipro Limited (NYSEWIT, BSE507685, NSEWIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at www.wipro.com. About The Role _x000D_ Role Purpose The purpose of this...

Backup and recovery processes and tools Database knowledge (logical and physical design) Experience with troubleshooting database performance issues and query tuning concepts Perform data management tasks as required: loading / unloading, updating, restoring and removing data to ensure that database is accurate as a data source. Perform Database Maintenance activities like Adhoc Reorgs, Runstats etc on demand from the application teams, as well as monitor the scheduled maintenance activities. Monitor and manage Space: Purge obsolete data and reclaim space Identify and troubleshoot databases issues with high priority. Monitor database backups and Database maintenance jobs. Troubleshoot job fa...

As a Logic design Engineer in the IBM Systems division, you will be responsible for the microarchitecture design and development of features to meet Secure, high performance & low power targets of the Mainframe and / or POWER customers. Deep expertise in the implementation of functional units within the core / cache / Memory controller / Interrupt / crypto / PCIE / DLL Additional responsibilities: logic (RTL) design, timing closure, CDC analysis etc. Understand and Design Power efficient logic. Agile project planning and execution. Masters in VLSI with demonstrated experience in the micro architecture and design of state of art Processor features to enhance high performance secure system per...

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in g...

As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6....

- Lead the architecture, design and development of an Interrupt Controller for a highly virtualized, multi-threaded, many-core and multi-socket SMP (symmetric multi-processor) . - Develop the features, present the proposed architecture in the High level design discussions to hardware and software teams - Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, firmware, software teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in globa...

1. Hands on work on custom layout for analog blocks like High Speed SerDes and General purpose IO designs with Cadence Virtuoso on latest technologies like 5nm and below and also take leadership roles in delivery of IPs 2. Work on Floor planning, power design, signal routing strategy, EMIR awareness andparasitic optimisations 3. Understand and apply analog Layout techniques to ensure the design meets performance with minimum possible area and good yield. 4. Participate in building and enhancing layout flow for faster, higher quality design process. 5. Checking physical verifications like DRC/LVS/ERC/ANT/DFM and other IBM internal checks 6. Collaborate with Circuit Designers to solve challeng...

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in g...

We have roles in the digital and analog domains wherein you will be:Working towards definition, design, verification, and documentation for SoC(System on a Chip) developmentDetermining architecture design, logic design, and system simulationPerforming all aspects of SoC design flow-from high-level design tosynthesis, place and route, timing, and power-to create a design databasethat is ready for manufacturingTranslating SoC requirements to analog circuit specifications, architectingand designing analog IPs: ADC/DAC, LDOs, PLLs, temperature sensors, etc.Designing innovative analog and mixed signal circuits and contributing todelivering analog IPs in advanced Intel process nodesCollaborating w...

Expertise in logic synthesis, conformal, static timing analysis and Place and Route (PnR) Hands on experience in all aspects of the chip development process Experience in creating or improving low power synthesis methodologies Experience with scripting languages like Perl, Tcl or Python Floorplan, Place and Route at block level, physical design verification, LVS, DRC, IR drop analysis; netlist to gds at block level RTL logic design or implementation experience on multi-million gate ASICs will be a plus Strong communication skills to effectively communicate across all internal groups Description: As a synthesis, PnR Engineer, you will have responsibilities spanning various aspects of SOC desi...

Building, implementing and supporting SSRS, SSIS and Power BI solutions Responsible for logical design, physical design, implementation, testing and deployment of BI project. Understand complex business problems and implement product features that are secure, scalable, robust and easy to implement and maintain. Take full ownership of product features to implement, provide bug fixes and write tests and tooling for those features to ensure they work we'll at cloud scale. Take pride of ownership in features that are used by users of Top 100 Global enterprises. Out of the box thinking for optimizing work and providing best in class Solution. Self-Motivated who can understand the requirements wit...

Engineer / Sr Engineer (Linux BSP), eInfochips, 4 - 10 years, Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore - ACHNET Are you sure you want to cancel? Are you sure you want to cancel this Profile? You can always come back later Edit Profile The first thing people see You do not have permission to access the Talent Management menu. This section is restricted to Admins and Editors only. If you believe you should have access, please contact your administrator for assistance. YOUR BROWSER IS NOT SUPPORTED To view this experience, please upgade to the latest one of these browsers Engineer / Sr Engineer (Linux Bsp) DESCRIPTION Job Description, Role Responsibilities POSITION TITLE: EXPERIENCE: ...

Work together with system architects and micro architects to define high level specifications that are implementable. Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. Provide support to functional validation teams in post silicon deb...

Apply to this job Meta is hiring ASIC EDA Infrastructure Engineers within our Infrastructure ASIC organization. EDA Infrastructure Engineers are individuals with experience in EDA flow and methodology, CAD/automation and ASIC infrastructure to build efficient System on Chip (SoC) and IP for data center applications. ASIC Engineer, EDA Infrastructure Responsibilities Front End implementation flow development and support Internal tools development and automation to help improve productivity across ASIC design cycles including but not limited to RTL generation tools, memory selection automation, register generation, filelist generation Manage the internal EDA license requests, installation and ...

Work together with system architects and micro architects to define high level specifications that are implementable. Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. Provide support to functional validation teams in post silicon deb...

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Basic qualifications: Strong academic and techn...

As a Hardware at , you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today s market. Your role and responsibilities As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verificatio...

Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced ...

: We are looking for a highly skilled and experienced Physical Design Lead to join our VLSI team. The ideal candidate will have a strong background in physical design and a deep understanding of the VLSI design flow. This role involves leading a team of engineers and working closely with cross-functional teams to ensure the successful implementation and optimization of physical designs. Key Responsibilities: Lead the physical design team in the implementation of complex digital designs, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Collaborate with RTL design, verification, and DFT teams to ensure design quality and robustness. Develop and implement p...

Role: Physical Design Engineer Experience Required: 5-15 Years Work location: Noida Minimum Experience required is 5 Years in Physical Design Strong fundamentals on Physical design including Floorplan, power grid analysis, placement, cts, routing, DRC-LVS closure, timing closure, antenna fixing, signal integrity on 65nm, 45nm, 28nm, 16nm geometry. Sound expertise in Tcl, Perl, and Shell scripting. Technically sound & good team player Hands-on experience with Place and Route tools (Synopsys - ICC, Cadence Innovus / Encounter) is a must. Experience with latest technology (28nm,16nm,7 nm) Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com Ref...

Urgent Hiring VLSI Physical Design / STA / EMIR Engineers (Immediate Joiners Only) | Pune Location Location: Pune Notice Period: Only Immediate Joiners Hiring Duration: Till 3rd Week of June Mode: Full-time Opportunity 1. Physical Design Engineer Experience: 4 to 6 Years Key Responsibilities: Full RTL-to-GDSII flow execution including floorplanning, power planning, placement, CTS, routing, DRC/LVS closure. Work on advanced technology nodes (7nm/5nm and below). Experience in hierarchical and flat implementation. Ownership of block-level PnR, timing closure, IR/EM, and physical verification. Interfacing with cross-functional teams RTL, DFT, PD, and verification teams. Required Skills: Strong e...