1253 Physical Design Jobs - Page 39

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Mumbai Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Mumbai Work Locations: Andheri West (Infinity Mall) Lower Parel (High Street Phoenix Mall) Thane (Viviana Mall) Malad (Inorbit Mall) Vashi (Raghuleela Mall) Shift Timing: 12:00 PM 9:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Assist kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orie...

Primary & Mandatory Skill: Python, Docker/Kubernetes Level: SA Client Round (Yes/ No): No Location Constraint if any : No Shift timing: 2-11pm JD: Good hands in Python scripting Experience in Docker & Kubernetes

SMTS SILICON DESIGN ENGINEER (AECG ASIC Physical Design Implementation) THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver...

SENIOR SILICON DESIGN ENGINEER ASIC Physical Design Engineer THE ROLE: The focus of this role in the AECG ASIC organization is to own physical design implementation for next generation ASICs that meet Engineering, Business and Customer requirements. Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deli...

**Job Summary:** We are looking for an experienced and results-driven IC Physical Design Engineer with 5+ years of hands-on experience in digital backend implementation of complex SoCs or ASICs. In this role, you will lead or contribute significantly to block-level and full-chip physical design, timing closure, and sign-off processes in advanced technology nodes. You will work cross-functionally with RTL, DFT, verification, and packaging teams to deliver high-quality silicon on aggressive schedules. **Key Responsibilities:** + Lead physical implementation of blocks and/or full chip through all stages: floorplanning, power planning, placement, CTS, routing, and sign-off. + Drive timing closur...

Primary/ Mandatory skills : Extensive experience in “Chef IT Automation” Secondary skills : Good knowledge and experience in DevOps Level: SA RR : Maintain a consistent terraform script when compared to existing cloud resources Chef version update: version 14 to version 18 Crowdstrike, Qualys and Splunk integration for Ecommerce workloads Packer AMI creation for Windows Core and CentOS Stream 9 Terraform version update Collaborate with DB team for “CentOS version + DB version” update project Test every change made. Work with DevOps, SRE and development teams for testing. Document and publish the changes, and projects undertaken. Client Round (Yes/ No): Yes Location Constraint if any : No Con...

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll Do: Perform hands-on physical design and physical verification tasks across projects in advanced process nodes. Manage project-specific ASIC development flow setup and maintenance. Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities. Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database. Ensure cor...

About Tessolve Tessolve is a leading engineering solutions provider, enabling silicon and system companies to accelerate their products to market. With capabilities across silicon design, test engineering, and embedded solutions, we are an end-to-end partner for semiconductor companies globally. Job Description We are looking for a Senior STA Engineer with 8 10 years of hands-on experience in Static Timing Analysis for complex SoC/ASIC designs at advanced technology nodes (7nm, 5nm, or below). The ideal candidate should be technically sound, self-driven, and capable of independently owning STA tasks from RTL to signoff. Key Responsibilities Perform full-chip and block-level static timing ana...

DIRECTOR OF MARKETING www.einfochips.com Job Description, Role Responsibilities POSITION TITLE: Engineer / Sr Engineer (Linux BSP) EXPERIENCE: 4-10 Years Role: Linux BSP LOCATION: Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore Company Profile eInfochips An Arrow Company (www.einfochips.com) is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company s service offerings include digital transformation and connected IoT solutions, Including IoT Security, across various cloud platforms, including AWS and A...

Key Responsibilities: Lead end-to-end physical design flow for complex blocks or full-chip designs. Drive floorplanning, power planning, placement, CTS, routing, and physical verification (DRC, LVS). Optimize timing, power, and area to meet design specifications. Perform hierarchical/flat implementation based on project needs. Work closely with RTL, DFT, STA, and packaging teams. Manage and mentor a team of physical design engineers. Interact with EDA vendors to improve tool flows and resolve tool-related issues. Contribute to methodology improvements and script automation for design efficiency. Required Skills and Qualifications: B.Tech/M.Tech in Electronics/Electrical Engineering or relate...

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Senior/Lead PD Engineer ADI is looking for Senior/Lead PD Engineer for the develo...

THE ROLE: The Core design team is responsible for development of High performance and Ultralow power x86 microprocessor core . The role provides a unique opportunity to work at the micro-architectural level of the next-gen Core, with exposure to designs that defines the next wave of client (laptops / ultra-books / think-clients / server) and custom designs. The multi-billion gate complexity and high-frequency (GHz) design development gives the learning experience of the latest and greatest design and verification methodologies, using cutting edge advanced technology nodes. KEY RESPONSIBILITIES: RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP ...

P MTS SILICON DESIGN ENGINEER (AECG ASIC PD Architect) THE ROLE: The focus of this role in the AECG ASIC organization is to lead physical design architecture and flow development for next generation ASICs that meet Engineering, Business and Customer requirements. THE PERSON: AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanni...

FELLOW SILICON DESIGN ENGINEER THE ROLE: We are looking for a Fellow-level Engineer to join our team to develop world-class Server products . In this role you will be engaged with Server SOC architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define end to end Power Optimization Methodology, PVT Corners, timing methodology that require technically analyzing, defining usage cases, and mapping across a broad spectrum of technologies to ensure a well-defined methodology to achieve PPA uplift across a spectrum of Server products. In this role you will provide a cohesive technical vision of the required PPA improvement methodology. THE PERSON: You will possess very ...

THE ROLE: We are seeking a highly experienced and innovative SOC Physical Design Director to lead the development of Server SOC designs and very experienced physical design team . This senior level role is critical for the design development of Server SOC designs products at AMD and is responsible for delivering Server SOCs meeting challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: This role combines strong people leadership and teamwork skills driving cross functional teams across geographies. The person with strong technical expertise, Strong analytical and problem-solvi...

Video Editing Intern Jaipur (In-office) - Digi Spheres Video Editing Intern Jaipur (In-office) Job Summary: We re seeking a creative and technically skilled Video Editing Intern to bring our content to life. You ll be responsible for editing short-form and long-form content for various platforms. Key Responsibilities: Edit videos, reels, and motion graphics for client campaigns Add music, text, transitions, and other visual effects Optimize content for Instagram, YouTube, and other platforms Collaborate with content creators and strategists for ideation Requirements: Proficiency in Premiere Pro, Final Cut Pro, or CapCut Strong sense of pace, timing, and narrative flow

Conceptualizes, documents, and designs tools, flows, and methods (TFM) for use in the physical design implementation of IPs, SoCs, and the interaction/handoff/reuse between IPs and SoCs. Establishes regression flows, drives improvement in RTL to GDS flows, and creates and implements methodologies for improving robustness, power, performance, area, and timing for optimizing physical design constraints. Develops new physical design techniques through innovative scripts, checkers, flows, and other CAD based automation to simplify and expedite the design process. Analyzes retrospective data on current generation quality and efficiency gaps to identify proper incremental, evolutionary, or transfo...

This position typically requires at least 2 to 3 years of related IP design or customer experience, but we may also consider candidates with less experience with the right academic background. ASIC design experience with proven design background. Experience in one or multiple steps on IP design or integration flow of ASIC / SoC design (such as simulation/verification, RTL synthesis, floor planning, physical design, timing closure, etc.) and silicon bring-up/characterization in a system environment. Domain knowledge of at least one of the following protocols: PCI Express SERDES Serial ATA Good RTL and Gate Level simulation Debug skills Familiarity with Front end implementation like Synthesis,...

An experienced and passionate Applications Engineer, ready to join our dynamic team. You thrive in fast-paced environments and are driven by the opportunity to work with high-end customers in the Mobile Industry Processor Interface (MIPI ) domain. With your strong technical background in ASIC design, you are adept at providing top-tier technical support and guidance. Your excellent communication skills enable you to effectively interact with customers and internal teams alike. You are not just looking for a job, but a place where you can make a significant impact and grow your career. What You ll Be Doing: Providing technical support to field engineers and customers utilizing Synopsys MIPI U...

Working on functional verification of high-speed serial link PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Studying IP/design blocks/firmware specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs) as per verification plan needs. Performing simulation, random and direct stimulus development, and coverage review. Working closely with digital designers for debugging and achieving the desired coverage. The Impact You Will Have: Ensuring the accuracy and...

Notice Period : Immediate - 15 Days Key Responsibilities : - Software Development : Implement software solutions using Python programming language. - Test and Validation : Design and execute comprehensive test cases to ensure software quality. - Technical Documentation : Create clear and concise technical documentation. - Customer Support : Respond to customer inquiries and resolve issues in a timely manner. - Automation : Automate design steps within the VLSI CAD flow. - Agile Development : Work in Agile Scrum teams and follow Agile methodologies. - Collaboration : Collaborate with customers to align on project requirements and present project updates. - Quality Assurance : Adhere to coding...

Key Qualifications Must have B.Tech or M.Tech with 4-7 years of relevant experience. Good knowledge of Physical design , STA , Physical Verification and Parasitic Extractionmethodologies. Proficiency in Unix, a strong understanding of ASIC design flow. Knowledge of Analog Mixed Signal flows will be an added advantage. Strong communication skills are a must. Proficiency in scripting languages - shell scripting, tcl, python would be helpful

We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly skilled and motivated Physical Design Engineer with a passion for innovation and a proven track record in the semiconductor industry You thrive in dynamic environments and are adept at managing multiple projects simultaneously Your deep understanding of the full design cycle from RTL to GDSII, particularly in advanced FinFET nodes, positions you as a technical driver in your field You possess excellent communication skills, enabling you to effectively coll...

What You ll Be Doing: * Serving as the single point of contact for post-silicon debug activities. * Enabling Product Requirement Documents (PRDs). * Working to enable IP as a product development platform. * Handling hands-on post-silicon test setups. * Collaborating on top-level physical design, board-level, and package-level designs. * Developing post-silicon reports and conducting debug analysis. The Impact You Will Have: * Driving the successful development and deployment of PVT IP sensors. * Enhancing the reliability and performance of Synopsys silicon lifecycle monitoring solutions. * Ensuring high-quality product development through meticulous testing and debugging. * Contributing to t...

Greeting with HCL Tech! We were looking somebody who is having experience in Physical design Experience: 4 to 10 Years Location: Kochi JD#1 : 4-6years Tapeout experience in block level PnR implementation including synthesis for medium to complex blocks Good to have experience in TSMC/Intel lower technology node(16/14nm or below) Experience in independently analyzing/resolving congestion, timing issues and basic understanding of clock tree build Basic Timing understanding to independently analyze timing paths Experience in ICC2/Innovus/DC tools, Fusion compiler being added advantage Basic equivalency check understanding. Good to have Conformal LEC experience. Should have understanding of basi...