BSEE and at least 5 years of prior experience are required. MSEE and at least 3 years of previous experience are strongly preferred. Prior experience in timing and or RTL design of high-speed interfaces. Prior experience collaborating with Physical Design teams in multiple successful ASIC/IP Tape Outs. Knowledge of the IP/SoC level timing closure flow and methodology. Strong command of Verilog/System Verilog language. Strong command of simulation, lint, synthesis, STA, formal verification, functional coverage, design for test, and design methodologies. Ability to handle multiple projects/tasks successfully. Experience in IP/ASIC timing constraints generation and timing closure. Expertise in STA tools and flow. Hands-on experience in timing constraints generation and management. Proficiency in scripting languages (TCL and Perl). Familiarity with synthesis, logic equivalence, DFT and backend-related methodology and tools. Capability to understand and implement improvements to existing methodologies and flows. Strong background in Constraint analysis and debugging, using industry-standard tools. Deep understanding and experience in timing closure of various test modes such as scan shift, scan capture, at speed and Best testing. Team player with a passion for innovating and a can-do attitude. Self-starter and highly motivated. Desired Skills : Knowledge of DDR/GDDR DRAM protocol; high-speed PHYs. Experience designing or integrating IP. Experience in high-speed and low-power digital design using advanced deep-micron processes. Experience with highly configurable designs
Technical Skill Set - SOC level Floor Plan, PNR, IO Ring Design, Timing Closure, Physical Verification, Power planning and analysis, ECOs on 7nm and 10nm technology nodes. Must-Have Hands-on experience on Full chip floor plan, Full chip PNR, and Design Partitioning. Hands-on experience in IO Planning, Bump Plan and RDL Routing. Experience in ECOs, Synthesis and STA, and Power analysis. Hands-on experience in Physical verification. Hands-on experience on 7nm and 10nm technology nodes. Good-to-Have Effective communication skills to interact with cross-functional teams.
Experience in front-end development languages like HTML, CSS, and JavaScript. At least 2+ years of hands-on experience with atleast any one backend programming language - Python, Java, PHP, C Sharp, etc. At least 2+ years of hands-on experience with any one of the database languages - Microsoft SQL Server, Oracle, MongoDB, etc. Experience in frameworks for known languages. such as ASP.NET, PyCharm, etc. Database design/data modelling experience and performance tuning. Experience with version control systems such as Git, Mercurial, Subversion, etc. Ability to solve business problems Ability to work independently and in a team environment.
The Technical Information Security Officer (TISO) is accountable for the complete lifecycle of the Application currently on the Archer platform including the development, releases and support activities of the application. He/she has to ensure that the application(s) are enhanced and maintained per the Banks IT Security Risk and Compliance requirements of the client and other stakeholders as included in the application strategy and service levels. The TISO identifies and manages the risks and issues associated with the application(s) and escalates appropriately. This role requires an Archer Administrators expertise and skills and good knowledge of the ServiceNow GRC platform (preferably IRM module). Migration experience from one platform to another would be an added advantage. Scoping and planning of release schedule. Maintain the JIRA board. Deploy release according to DB SDLC release process - Create release and change request in ServiceNow - Fulfill release and application controls before deployment - Monitor SDLC platform. Facilitate Disaster Recovery activities by reviewing DR plans and coordinating the execution of DR exercises for the application. Manage Internal and external application audits and Audit issue remediation activities. Manage Technology Roadmap Compliance (TRC). Manage remediation of gaps in application lifecycle management activities such as Account recertification, remediation of Application configuration gaps, Essential Maintenance, etc. Manage application-related Risk and Compliance Evaluation tasks and resolution of gaps in this area. Perform Log Reviews for Servers, Databases, and Applications. Manage Application user access-related tasks Like maintaining SOD, Timely Recertification, Granting/Modifying/ Revoking access, etc. Plan for Application Hardware / Software / License upgrades. Plan and lead migration activities to align with the compliant platforms. SDLC Onboarding and ensuring the SDLC release process adheres. Onboard mandatory Control for Governance, Compliance and Security for Application and its assets as per Banks Standard recommendations, like Tools/control onboarding for Access Mgt workflow, SDLC, App infra and Security Monitoring, Encryption/masking if applicable, etc. Liaise with other stakeholders for Security Framework, solution implementation, Security Remediation, Infra Provisioning, Setup if needed, Liaise with capacity teams for any issues etc. Should be able to handle Incidents and support issues for Prod and Non-prod. Should be well versed with programming languages like Java/DotNet/Javascript/SQL. Should be good with Server Management. Should be good with RestAPI and should be able to manage the interfaces between the applications. Should be good with the latest SDLC tools and technologies and responsible for complete application management and releases supported by a small team of developers. Should be able to upgrade the Archer platforms as and when required. Platform Administration including Integration with External Systems.
Job Description : Full-chip DFT working experience with multiple design Tape Outs. Block level and Chip level SCAN insertion, DRC, Coverage Analysis and improvements. Expertise in Scan Compression(EDT/OPMISR+), MBIST, BSCAN, ATPG implementation and verification. Hands-on Experience with industry-standard DFT EDA tools and flows. Good Knowledge of cross-functional domains (SYN, LEC, STA, PD) with ownership of constraints developments and LEC. Excellent problem-solving and debugging skills. Proactive in nature. Develop/automate flows and scripts in Perl/Tcl to enhance the DFT methodologies and processes. Leading junior teams, Mentoring/Training and Project leadership. Excellent Customer interaction, Communication and Teamwork skills. Desired Skills : ATPG (at-speed and stuck-at), At Speed Scan, Design for Testability (DFT).
Prior Experience in Demand Planning/Forecasting in Product Based/Consultancy organizations. Statistical Forecasting techniques (Time series, Holts Winter, Regression analysis, ARIMA, ARIMAX etc.) Good communication and presentation skills. R /Python, Machine Learning Techniques (Random Forest/Decision Trees, Deep Learning). Visualization skills: Power BI/Tableau would be preferable. Database: MS SQL/Oracle SQL. Exposure to Cloud solutions like AWS/Microsoft Azure will be an added advantage. Ability to design analytics solutions, simulation, and modelling to address business problems.
Design Verification. Strong SV/UVM fundamentals. Experience in building Test benches from scratch. Assertions-driven verification. Coverage-driven verification. Any protocol Experience. Highly motivated, self-starter with good interpersonal skills and a strong team player. Excellent communication, critical thinking, and problem-solving skills.