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Advanced Micro Devices, Inc
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MTS Silicon Design Engineer

MTS Silicon Design Engineer

Advanced Micro Devices, Inc

5 - 10 years

35 - 40 Lacs

Bengaluru

Posted:1 month ago| Platform:

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Skills Required

Unix Graphics C++ Linux SOC Verilog Workflow Perl Python Physical design

Work Mode

Work from Office

Job Type

Full Time

Job Description

Front-End Silicon Design & Integration (FEINT) Engineer

The role:

A Front-End Silicon Design and Integration (FEINT) Engineering role in our Security IP (SECIP) team, where a large number of embedded micro-processor subsystems, hardware accelerators and other IPs vital to improve system performance and functionality are designed and verified. These IPs provide high performance functions to System on Chip (SoC) products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our FEINT engineers will perform RTL synthesis and PPA analysis in order to improve the QoR of RTL designs. They will also create, adopt and automate RTL static design rule checks, perform ECO and LEC checks, as well as support SOC integration of the IPs.

The person:

A talented FEINT engineer with strong records of technical ownership and execution to drive synthesis, PPA analysis, ECO, and static verification assignments to completion. A forward-thinking engineer who tends to optimize/improve the workflow, anticipate/analyze/resolve technical issues, enjoy a competitive pace while empowering and mentoring team members. A strong written and verbal communicator with strong problem solving and attention to detail skills along with professional interpersonal communication capability.

Key responsibilities:

Develop RTL synthesis strategy and scripts to perform synthesis, timing path analysis and PPA analysis (performance, power, area) at subsystem level as well as at block level RTL designs to drive for continued improvement of QoR (quality of result)
Develop ECO strategy, perform netlist and/or conformal assisted RTL ECOs, perform LEC on resulting netlists and resolve discrepancies
Develop, adopt and automate RTL static design rule checks in collaboration with Back-End Integration and Physical design teams, triage and debug design rule violations with RTL design team, support IP integration with SoC team
Develop and adopt FEINT design and verification infrastructure, methodology and tools

Preferred experience:

BSc with a minimum of 5 years relevant experience, or MSc with a minimum of 3 years
Proven understanding of RTL design, synthesis, and ECO principles
Excellent knowledge with FE design tools such as Design/Fusion Compiler, Prime Time, Power Artist, etc.
Proficient with Verilog, C/C++ and other scripting languages (e.g. Tcl, Ruby, Perl, Python and Makefile)
Excellent skills with Unix/Linux environment
Familiar with RTL coding techniques for competitive PPA-measured QoR
Familiar with RTL coding style for clean check on design rules (LINT, CDC, etc.)
Good understanding of gate level circuit design and physical level design concept and methodology
Familiar with VCS/Verdi and SPG based (dynamic/static) verification environments
Excellent communication skills (both written and oral)
Self motivated, and committed to achievement

Academic credentials:

Bachelors Degree or Masters Degree in Electrical Engineering, Computer Engineering, or possibly a related field
Masters Degree preferred

#LI-PS1

Benefits offered are described:

AMD benefits at a glance .

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MTS Silicon Design Engineer