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Wafer Space - An ACL Digital Company
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Physical Design Engineer

Physical Design Engineer

Wafer Space - An ACL Digital Company

3 - 12 years

0 Lacs

Pune Maharashtra India

Posted:1 day ago| Platform:

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Skills Required

design synthesis timing checks drc lvs planning extraction power signal integrity analysis verification routing layout automation perl tcl

Work Mode

On-site

Job Type

Full Time

Job Description

3-12 years of experience

Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure

Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM

Must have participated in all stages of the design (floor planning, placement, CTS, routing, physical verification, IREM)

Well-versed with the timing closure (STA), timing closure methodologies

Good Understanding of DRC, LVS, ERC and PERC rule files for lower-tech node layout verification

Experience in lower tech node (

Good automation skills in PERL, TCL, and EDA tool-specific scripting

Able to take complete ownership of Block/sub-system for a complete execution cycle

Detailed

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Physical Design Engineer