Lead Design Engineer

3 years

0 Lacs

Pune, Maharashtra, India

Posted:1 week ago| Platform: Linkedin logo

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Skills Required

design cadence technology optimization power ip development automation maintenance regression flow benchmarking synthesis timing analysis verification scripting python perl tcl unix logic architecture communication

Work Mode

On-site

Job Type

Full Time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities Digital design implementation of state-of-the-art Cadence IPs using Cadence EDA tools - Genus, Innovus, Tempus, Voltus and other backend tools PPA characterization and optimization of these performance-oriented and power-oriented best-in-class IP cores for advanced process nodes, such as 7nm/5nm/3nm/2nm Development, automation and maintenance of EDA flows and scripts for physical implementation Manage regression infrastructure that tracks quality of the RTL/flow development as well as the PPA of the key designs Participate in benchmarking PPAs for customer engagements Required Skills – Educational Qualification: MS/MTech/BE/ BTech in Electronics from reputed institutes 3+ years of relevant experience in ASIC design environment Should have knowledge of complete ASIC Design Flow, including Synthesis, Physical Designing , Timing Analysis, Power Analysis and Formal Verification Experience with Cadence digital design tools will be an added advantage Hands on scripting languages like Python, Perl, TCL, Unix shell etc Strong understanding of digital logic design, processor design, and computer architecture is desirable Should have excellent communication, analytical and problem solving skills Should be self-motivated and good team player We’re doing work that matters. Help us solve what others can’t. Show more Show less

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Cadence
Cadence

Software, Electronic Design Automation

San Jose

Approx. 8,000 Employees

176 Jobs

    Key People

  • Anirudh Devgan

    President and CEO
  • Tom Beckley

    Senior Vice President

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