Lead Design Engineer

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by utilizing your skills and expertise. You will be responsible for hands-on layout experience in various analog IP components such as Opamps, Bandgaps, Data converters, LDO, PLL, and more. Your role will involve understanding the impact of layout on the circuit regarding speed, capacitance, power, and area. Knowledge of analog layout techniques like matching, shielding, and familiarity with DSM technology methodology will be essential. Experience with the latest technology nodes, specifically 28nm and below, is preferred. Additionally, you will be expected to possess good communication skills, work effectively as a team player, and have experience with scripting and automation. High-speed analog layout experience in areas like Serdes, power management, and PLL will be beneficial. Understanding layout effects on the circuit and various techniques, floorplan constraints, and IP integration at the chip level will be part of your responsibilities. Qualifications for this role include a degree in BE/BTech/ME/MS/MTech in Electrical/Electronics. Strong written, verbal, and presentation skills are essential, along with the ability to establish close working relationships with customers and management. You should exhibit strong analytical and problem-solving skills and be open to exploring unconventional solutions to get the job done. Operating with integrity and pushing to raise the bar will be key aspects of your role. Join us in our mission to tackle challenges that others cannot solve and be a part of work that truly matters at Cadence.,