5.0 - 9.0 years

0 Lacs

hyderabad, telangana

On-site

As a member of the Cadence team, you will have the opportunity to contribute to the world of technology by utilizing your skills and expertise. You will be responsible for hands-on layout experience in various analog IP components such as Opamps, Bandgaps, Data converters, LDO, PLL, and more. Your role will involve understanding the impact of layout on the circuit regarding speed, capacitance, power, and area. Knowledge of analog layout techniques like matching, shielding, and familiarity with DSM technology methodology will be essential. Experience with the latest technology nodes, specifically 28nm and below, is preferred. Additionally, you will be expected to possess good communication skills, work effectively as a team player, and have experience with scripting and automation. High-speed analog layout experience in areas like Serdes, power management, and PLL will be beneficial. Understanding layout effects on the circuit and various techniques, floorplan constraints, and IP integration at the chip level will be part of your responsibilities. Qualifications for this role include a degree in BE/BTech/ME/MS/MTech in Electrical/Electronics. Strong written, verbal, and presentation skills are essential, along with the ability to establish close working relationships with customers and management. You should exhibit strong analytical and problem-solving skills and be open to exploring unconventional solutions to get the job done. Operating with integrity and pushing to raise the bar will be key aspects of your role. Join us in our mission to tackle challenges that others cannot solve and be a part of work that truly matters at Cadence.,

Posted 6 days ago

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Analog Circuit Design Lead Wipro

7.0 - 10.0 years

20 - 35 Lacs

Bengaluru

Hybrid

Requirement : Analog Circuit Design Lead Experience Range : 7 - 12 Yrs. Work Location(s) : Bengaluru, Karnataka Candidates who are ready to join Immediately Requirements: Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization. Must have led the entire Analog IP development cycle and team. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc. Analog/custom layout design in advanced CMOS process. Ability to understand design constraints and implement high-quality layouts. Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...). Characterization . Hands-on experience on lower FINFET technology nodes and design/PPA trade-offs

Posted 2 months ago

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