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Mirafra
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Imm Openings: Design Verification Engineers (5 to12 Yrs) HYD/B'Lore

Imm Openings: Design Verification Engineers (5 to12 Yrs) HYD/B'Lore

Mirafra

5 - 10 years

30 - 45 Lacs

Noida Hyderabad Bengaluru

Posted:2 months ago| Platform:

Apply

Skills Required

System Verilog UVM NOC PCIE Dram Test Case Development Assertions Gls

Work Mode

Work from Office

Job Type

Full Time

Job Description

experienced Design Verification Engineers

If you're passionate about digital design and verification and want to work on cutting-edge SoC projects, this is the opportunity for you!

Key Responsibilities:

Develop and execute
test plans
and
testbenches
using
SystemVerilog/UVM
Perform
functional and code coverage analysis
Debug RTL and testbench issues efficiently
Collaborate with design and architecture teams to ensure verification completeness

Required Skills:

Strong coding skills in
Verilog
Hands-on experience with
SystemVerilog
and
UVM-based verification
Experience in
SoC/IP level verification
Good understanding of
design verification methodologies
, assertions, and coverage
Familiarity with
debugging tools
,
simulation
, and scripting (Python/Tcl/Perl)

Preferred Skills:

Exposure to
high-speed protocols
(PCIe, USB, Ethernet)
Knowledge of
formal verification
or
power-aware verification
is a plus

Why Join Mirafra?

Apply Now

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