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Analog Devices
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Senior Engineer, Design Verification Engineering

Senior Engineer, Design Verification Engineering

Analog Devices

4 - 7 years

13 - 17 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

jtag python electronics sv data validation usb prototyping amba communication protocols design verification engineering uvm spi design engineering ethernet hap vendor product development uart debugging shell scripting perl i2c scripting languages

Work Mode

Work from Office

Job Type

Full Time

Job Description

The Engineering Enablement team is responsible for providing tools, methodologies, and support to engineering teams to accelerate product development across the company. This position is for an opening in the Systems Verification and Validation team within the Engineering Enablement organization in the Vertical BU .This team works to define and promote the adoption of verification best practices, including Metric-driven verification, UVM, Formal, FUSA, Security, Emulation and FPGA Prototyping methodologies . This role is more focused on driving Emulation and FPGA Prototyping solutions across ADI.

Job Responsibilities :

Lead, Develop and deploy best-in-class Emulation/FPGA prototyping tools and methodologies across ADI Product Lines as part of Verification Excellence Program (VXP)
Develop and deploy Accelerated Verification IPs, Synthesizable BFMs and help in integration of memory models of various interfaces
Engaging with EDA vendors to influence their development roadmaps to meet ADI s requirements into the future
Support the product lines in bring-up of new designs, debug issues and explore new methodologies that improve the overall verification flow
Training, deployment, and support of verification methodologies within ADI

Position Requirements :

Bachelors/master s degree in electrical/Electronics/VLSI with 4-7 years of experience
Exposure to emulation platforms like Palladium/Zebu/Veloce and prototyping platforms like Protium/HAPS is highly preferred.
Exposure to JTAG, UART and SpeedBridges (Ethernet/USB) validation is highly preferred
Expertised in one or more of scripting languages(shell,python,perl) is highly preferred
Proficient in SV, UVM, integration of third party VIPS, Accelerated VIPS is required
Experience with Vplan/Testplan development and development of verification environment from ground up is good
Experience in common communication protocols such as AMBA,I2C, SPI,UART and Ethernet is an added advantage
Should be able to communicate technical details very effectively with both customers (product line teams) and peers
Good debugging and analytical skills

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Senior Engineer, Design Verification Engineering