Senior Engineer, Design Verification Engineering

Job Description

Are you a highly skilled Formal Verification Engineer looking to make a significant impact across the entire product lifecycle Join Analog Devices in a senior role where you'll drive the formal verification of complex digital designs, from concept through to release. You'll collaborate with a wide technical community, gaining exposure to diverse technologies and products, all while building a promising career. Job Responsibilities: Formal Verification Planning and Execution: Develop and execute comprehensive formal verification plans for complex digital designs, including both block-level and system-level components. Define precise verification goals, metrics, and coverage targets to ensure exhaustive validation of design functionality. Model Development and Property Writing: Create robust formal models and assertions using industry-standard formal verification tools and techniques. Write and debug properties, constraints, and assumptions to rigorously verify design intent and proactively identify corner-case issues. Debugging and Issue Resolution: Analyze counterexamples and debug failures to pinpoint the root causes of design issues. Work closely with design and RTL teams to efficiently resolve issues and ensure complete alignment with design specifications. Tool and Methodology Expertise: Utilize advanced formal verification tools such as JasperGold, Questa Formal, or equivalent, to perform exhaustive verification. Stay updated on the latest advancements in formal verification methodologies and tools, actively driving their adoption and continuous improvement within the team. Collaboration and Communication: Collaborate effectively with architects, designers, and validation engineers to deeply understand design requirements and constraints. Documentation and Reporting: Document formal verification strategies, methodologies, and results for future reference and auditability. Generate detailed reports summarizing verification coverage, key findings, and actionable recommendations. Position Requirements: Bachelor's or Master's degree in Electrical/Electronics/VLSI with 4-6 years of relevant experience. Demonstrated experience with Formal tools such as Cadence Jasper, Synopsys VC Formal, Siemens Questa Formal, with prior implementation experience on SoCs, CPUs, GPUs, or other high-performance computing devices. Proficiency in writing SystemVerilog Assertions (SVA) or Property Specification Language (PSL). Solid understanding of digital design concepts, RTL design, and hardware description languages (Verilog, SystemVerilog, VHDL). Strong analytical and debugging skills to effectively identify and resolve complex design issues. Ability to analyze counterexamples and provide actionable feedback to design teams. Excellent communication and interpersonal skills to work effectively in a collaborative team environment. Familiarity with scripting languages (Perl, Python, TCL) for automation. Experience in common communication protocols such as ARM AMBA, I2C, SPI, UART is preferred.