HCL TECH Hiring- DV Engineer/RTL Engineer- Hyd/Bangalore/Chennai

We are hiring on below Design Verification Engineer/ RTL Design Engineer - Engineer/Lead/Senior Lead . Please find the JD Details below - Please share us your details below in Table with your update resume.

JD - Design Verification Engineer - Engineer/Lead/Senior Lead

JD - RTL Design Engineer- Engineer/Lead/Senior Lead

Qualifications:

• Bachelors degree in electrical engineering, Computer Engineering, or a related field (masters degree a plus)
• Experience in design verification for ASICs or SoCs
• Strong understanding of digital design principles (combinational logic, sequential logic)
• Proven ability to develop and debug complex verification environments
• Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM)
• Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus
• Excellent analytical and problem-solving skills
• Strong communication and collaboration skills to work effectively in a team environment
• In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines)
• Proven ability to develop, debug, and optimize complex verification environments
• Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal)
• Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl)
• Experience with formal verification tools and techniques is a plus
• Excellent analytical and problem-solving skills with a meticulous attention to detail
• Strong communication, collaboration, and leadership skills to effectively contribute and guide the team

Benefits:

• Competitive salary and benefits package
• Opportunity to work on leading-edge technologies and projects
• Collaborative and dynamic work environment
• Potential for professional development and career advancement

Qualifications:

• Bachelor’s degree in electrical engineering, Computer Engineering, or a related field (Master's degree a plus)
• Experience in RTL design for ASICs/SoCs
• Proven experience in designing and verifying complex digital circuits
• Proficiency in Verilog or VHDL
• Experience with verification methodologies (e.g., UVM)
• Strong understanding of digital design concepts (combinational logic, sequential logic, state machines)
• Experience with SDC (Standard Delay Constraint) format for timing closure
• Experience with scripting languages (e.g., Python, Perl) is a plus
• Excellent communication, teamwork, and problem-solving skills

Benefits:

• Competitive salary and benefits package
• Opportunity to work on cutting-edge technologies
• Collaborative and fast-paced work environment
• Potential for professional growth and development