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verification engineering strategies verilog report metrics support regression testing tracking development agile jira azure devops electrical leadership writing architecture git communication simulation recognition automation programming scripting matlab signal

Work Mode

On-site

Job Type

Full Time

Job Description

FPGA Verification Team Lead



Duties and Responsibilities:

  • Lead and mentor FPGA verification engineers
  • Plan and implement verification plans, strategies, and methodologies
  • Work closely with FPGA designers and system architects
  • Develop and maintain verification environments and agents using System Verilog UVM methodologies
  • Monitor and report verification progress, coverage metrics, and quality indicators.
  • Support regression testing, bug tracking, and issue resolution during the development cycle.
  • Track verification progress using Agile tools (e.g., Jira, Azure DevOps) and provide regular status updates and metrics.



Technical Requirements:

  • Bachelor’s degree in electrical engineering, Computer Engineering or Computer Science
  • 10+ years of experience in FPGA or ASIC verification, with at least 2 years in a leadership or team lead role
  • Strong hands-on experience in writing System-verilog UVM agents and full UVM environments from scratch
  • Strong hands-on experience in writing verification plans and coverage plans
  • Solid understanding of FPGA architecture and RTL design
  • Familiarity with version control systems (e.g., Git) and issue tracking tools (e.g., Jira).
  • Excellent leadership, communication, and organizational skills
  • Strong experience with simulation tools such as Xcelium, Questasim or VCS
  • Strong debug capabilities

• Strong hands-on experience in writing System-Verilog UVM agents and full UVM environments from scratch

• Strong hands-on experience in writing verification plans and coverage plans



Preferred technical Requirements:

  • Graduated with honors or equivalent distinctions
  • Academic honors, scholarships, or recognition demonstrating intellectual capability
  • Knowledge of automation frameworks and CI/CD tools: Azure DevOps, Atlassian, GIT
  • Experience in programming and scripting languages: Bash, Python
  • Experience in using MATLAB models and generators as part of the verification flow
  • Experience in DevOps tools like Azure DevOps
  • Good knowledge of signal processing

· No of years of experience: 10 - 15 years

· Managerial experience: 3 - 4 years

· Technical Lead experience: 4 - 5 years

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