Engineer

HCLTech

2 years

0 Lacs

Kochi Kerala India

Posted:1 month ago| Platform:

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Skills Required

dft design test architecture logic jtag synopsys synthesis simulations support verification atpg cadence verilog vhdl tcl timing constraints

Work Mode

On-site

Job Type

Full Time

Job Description

Job Description:

DFT Engineer

Key Responsibilities:

Develop and implement DFT architecture for complex ASICs and SoCs.
Integrate and verify DFT features such as:
Scan insertion and ATPG
Memory BIST (MBIST)
Logic BIST (LBIST)
JTAG/IEEE 1149.1 (Boundary Scan)
Test compression techniques (e.g., Tessent, Synopsys DFTMAX)
Work closely with RTL, synthesis, and backend teams for DFT implementation and sign-off.
Run and debug simulations for scan and BIST logic.
Work with Automatic Test Equipment (ATE) teams to bring up and validate silicon.
Support post-silicon debug and yield improvement efforts.
Collaborate with cross-functional teams including verification, physical design, and validation.

Required Skills:

2+ years of hands-on experience in DFT implementation and test methodology.
Strong knowledge of scan insertion, ATPG, and fault grading.
Experience with DFT tools such as:
Synopsys (DFTMAX, TetraMAX)
Mentor Tessent
Cadence Modus
Proficiency in Verilog/VHDL, TCL, and shell scripting.
Understanding of digital design and SoC architecture.
Familiarity with STA and timing constraints related to DFT.

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