1121 Dft Jobs - Page 36

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a dynamic engineer with working experience in SOC-level functional verification and strong understanding of AXI and High-speed IO protocols like PCIe and USB. You should have a passion for working with the best of the brains in the industry in developing end to end solutions and deploying them at our premier customer base. Your technical excellence, analytical skills, coupled with strong communication and interpersonal skills, make you a valuable asset to any team. You excel in communication, teamwork, and multitasking, and have experience working in cross-functional, multi-site environments. What You’ll Be Doing: Working closely with a world-class R&D team, you’ll be at the center of developing and bringing an end-to-end solution to our wide variety of customers in the domain of Silicon Lifecycle Management (SLM). Working closely with customers, you will bring the detailed requirements into the factory to enable R&D for a strong, robust, and successful product development. Working closely with product development team, you will validate and end-to-end solution both internally (before shipment) as well as in customer environment. Driving the deployment and smooth execution of SLM solutions into customers’ projects. Enabling customers to realize the value of silicon health monitoring throughout the lifecycle of silicon bring-up, validation, through in-field operations. The Impact You Will Have: Enhancing Synopsys’ Silicon Lifecycle Management (SLM) IP portfolio and end-to-end solution. Driving the adoption of Synopsys’ SLM solutions at premier customer base worlwide. Influencing the development of next-generation SLM IPs and solutions. What You’ll Need: BSEE/MSEE in Electrical Engineering, Computer Engineering, or related field. 4+ years of hands-on experience with SoC-level functional verification or Design-for-Test (DFT) or both. Good knowledge of AXI, APB Background in verification, with at least sub-system level verification Debugging abilities to identify issues in functional verification. Knowledge of DMA, ideally should have verified a sub-system with DMA Knowledge of High-speed IO sub-systems like PCIe and USB A thorough understanding of memory mapping concepts is essential. End to end knowledge of how transactions/data flow between the HSIO interface to/from memory Knowledge and experience with Memory BIST/DFT/ATE/SLT/any other test solutions Ability to evaluate technical suggestions from customers and work with internal teams (product management/R&D) to make decisions Customer facing experience is a plus – educating/guiding customer on technical details of a solution Good to have: Hands-on debug experience of silicon is a plus Some programming experience to write/debug simple drivers in C Detailed knowledge of the PCIe and USB protocols Architecture/micro-architecture experience Working with FPGAs The Team You’ll Be A Part Of: As part of the Silicon Lifecycle Management (SLM) solutions team, you will collaborate with global R&D teams to develop world-class IPs and end-to-end solutions to address silicon health issues at premier data center, AI, and automotive customers. Our team is dedicated to bringing solutions to enhance the life of a silicon anywhere it belongs. Show more Show less

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of ASIC digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and running lint/cdc/rdc checks using VC-Spyglass and synthesis flow using Design Compiler/Fusion Compiler. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Setting up and running FPGA prototyping flows to map RTL designs to Xilinx FPGAs. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 2 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying Verilog and System Verilog design. Experience of working with minimum supervision and owning and delivering for front-end activities in IP/SOC. Experience of leading technically for front-end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Meet the Team Join Cisco's engineering team as an Electrical Product Engineer , where you'll collaborate with hardware, mechanical, software design teams, manufacturing teams, and cross-functional partners. Together, we ensure that products meet cost, quality, and delivery requirements while driving innovation. Be part of a team that delivers world-class solutions and creates a meaningful impact. Your Impact As an Electrical Product Engineer, you will play a critical role in ensuring product manufacturability and supporting New Product Introduction (NPI) and sustaining engineering efforts. Your responsibilities will include: Design Review: Analyze and review product design and architecture from Design for Manufacturing (DFM), component technology, and End of Life (EOL) perspectives. NPI Support: Provide technical support for prototypes during NPI to ensure cost and quality targets are achieved. Sustaining Engineering: Manage change management activities and drive quality improvements for both factory and field performance metrics. Value Engineering: Lead activities to enhance cost margins through component selection, process efficiency, and design changes. Supply Chain Support: Ensure supply chain continuity and resiliency by addressing potential risks and gaps. Minimum Qualifications Bachelor's degree in Electrical/Electronics Engineering or a related field. Strong understanding of Electronic Product Design and architecture. Knowledge of hardware interfaces such as PCIe, Ethernet, SATA, I2C, and high-speed serial interfaces. Proficiency in PCB design, stack-ups, and Allegro; knowledge of Valor and DFM is a plus. Understanding of PCBA Manufacturing, system build processes, and NPI workflows. Experience with product development processes from concept to launch phase. Proficiency in DFx principles including DFM, DFR, DFSC, and DFT. Hands-on experience in test automation using scripting languages like Python. Excellent verbal and written communication skills. Preferred Qualifications Familiarity with network routers and switches. Experience with manufacturing test solutions, test fixture development, ICT, and BSCAN. Knowledge of hardware and system testing, component-level debugging, and fault isolation. Strong understanding of FMEA (Failure Modes and Effects Analysis) and Design FMEA methodologies. Responsibilities Perform new product and sustaining engineering activities. Develop and execute end-to-end manufacturing test strategies. Conduct Design for Testability (DFT) assessments and create mitigation plans to ensure maximum test coverage. Develop and implement test automation scripts and processes. Create and manage BOM structuring and address BOM risks. Drive cost avoidance strategies (pre-A0) and sustain cost reduction initiatives. Collaborate with design teams to define and deploy optimized test solutions, including Ethernet interface testing (10G/100G/200G/400G/800G) using Traffic Test Analyzers (e.g., Spirent/IXIA). Lead debugging processes for test engineers at remote manufacturing sites. Plan, define, and manage test capacity and budgets. Stay updated on industry innovations to incorporate new trends and technologies into the product lifecycle. Who You Are A self-driven team player who thrives in a collaborative environment. A continuous learner willing to take on new challenges. Flexible to work across time zones to meet global business needs. Who You'll Work With You will work closely with cross-functional teams, including hardware/software design engineering , supply chain teams , and manufacturing operations teams , to develop and deploy manufacturing tests that meet the highest quality and efficiency standards. Why Cisco #WeAreCisco. We are all unique, but collectively we bring our talents to work as a team, to develop innovative technology and power a more inclusive, digital future for everyone. How do we do it? Well, for starters – with people like you! Nearly every internet connection around the world touches Cisco. We’re the Internet’s optimists. Our technology makes sure the data traveling at light speed across connections does so securely, yet it’s not what we make but what we make happen which marks us out. We’re helping those who work in the health service to connect with patients and each other; schools, colleges, and universities to teach in even the most challenging of times. We’re helping businesses of all shapes and sizes to connect with their employees and customers in new ways, providing people with access to the digital skills they need and connecting the most remote parts of the world – whether through 5G, or otherwise. We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that). We know that powering an inclusive future starts with us. Because without diversity and a dedication to equality, there is no moving forward. Our 30 Inclusive Communities, that bring people together around commonalities or passions, are leading the way. Together we’re committed to learning, listening, caring for our communities, whilst supporting the most vulnerable with a collective effort to make this world a better place either with technology, or through our actions. So, you have colorful hair? Don’t care. Tattoos? Show off your ink. Like polka dots? That’s cool. Pop culture geek? Many of us are. Passion for technology and world changing? Be you, with us! #WeAreCisco Show more Show less

ATE Test Engineer with experience in Teradyne- Ultraflex-RF Job Description In your new role you will: Develop and document Test plan for new IoT devices. Design and debug ATE Test Hardware and Software Production & Reliability. Debug new silicon on Automated Test Equipment. Bring quality and cost-effective Test solution for mass production. Oversee test related activities (HW & SW) with both internal and external Test house. Implement Test programs, modify and release into offsite production. Your Profile You are best equipped for this task if you have: Good understanding of semiconductor device fundamentals (Analog/Digital and Circuit Theory) Sound understanding of Semiconductor Design for Test (DFT) techniques such as ATPG and PMU blocks like BUCLK and LDO s with Trimming procedure. Expertise in Semiconductor Testing Methodology, using Teradyne- Ultraflex-RF. Ultraflex + is added advantage. Good programming skills in writing and debugging test programs and ATE hardware related issues. Provide test engineering expertise and troubleshooting support to both internal and external customers. Competency in programming with Scripting languages (ie., Perl/Python) and high-level languages (ie., C/C++, JAVA, Visual Basic) Develop and debug characterization and production test programs for SOC Connectivity products contains Digital/Mixed signal/PMU/NVM/Radio blocks. Cross-functionally collaborate with project team members across development sites and product roles of IP design, applications, DFT, Product engineering, and Test engineering Good verbal and written communication skills are expected. Familiar with UNIX/LINUX environment, commands and shell scripts. Contact: Jyoti.vimal@Infineon.com We are on a journey to create the best Infineon for everyone.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence Design Systems is looking for a highly motivated engineer to be part of the Modus R&D team, with a focus on validating and supporting Design-for-test (DFT) technologies. Candidate must have 2+ years of experience in DFT/ATPG/ASIC Design flows and knowledge of RTL Verilog/VHDL coding styles, Synthesis. This position requires excellent communication skills (written and oral) to interface with Product Engineers (PEs) and R&D and will occasionally also involve direct customer support responsibilities. Will work on complex problems that require innovative thinking, debugging customer reported problems and collaboration with R&D to propose out-of-box solutions with emphasis on robustness, PPA and scalability. Role Responsibility Work as a DFT Product Validation Engineer on insertion and validation of DFT technologies such as 1500 Wrapper, Compression, RTL DFT, Low Pin Count Test, Hierarchical Test, LBIST etc. using Cadence Synthesis tool Genus and ATPG using Cadence Test tool Modus on in-house and customer designs. Create testplans for verification of new features and execute them by creating new test cases requiring application of Design & DFT skills; Report bugs/enhancements in tool. Collaborate with R&D and Product Engineering teams to review feature specifications, testplans & customer issues. Debug issues reported by customers and suggest/implement measures to plug the gaps. Position Requirements B.E/B.Tech with 2+ years or M.E/MTech in Electronics/Electrical of experience Strong in Digital electronics, Verilog Good understanding of DFT techniques and methodologies Familiarity with Test standards like 1149.1, 1500, 1687 is a plus Experience with Cadence Test or other Test tools is preferred Modus is a DFT (Design for Testability) software tool from Cadence used by leading chip design companies during DFT synthesis & ATPG (Automatic Test Pattern Generation) phase of chip design We’re doing work that matters. Help us solve what others can’t. Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Micro-Arch, RTL Design ownership of SMMU IP for the next generation System-on-chip (SoC) for smartphones, tablets, and other product categories. System Memory Management Unit (SMMU) does virtual to physical address translation, dynamic allocation, and access control of DDR memory, designed as per ARM SMMU architecture spec Job responsibilities include Work with Hardware and Software teams to understand the design requirements, specification, and interface details for SMMU IP Develop micro arch design specification optimized for performance, area, power, Software use cases Implement design spec in RTL coding language, qualify code through all required quality checks like Lint, CDC, Synthesis/DFT/low power checks Work with SoC level performance modeling team on latency, bandwidth analysis, fine tune HW configuration like cache, buffer sizing Debug and root cause post silicon issues in collaboration with emulation, software test teams Required skillset includes VLSI logic design expertise ARM system architecture, Memory Management, Virtual Memory concepts, Core sight architecture, power management fundamentals Knowledgeable about on-chip interconnect protocols like APB/AHB/AXI/ACE/ACE-Lite Strong debugging, Analytical and problem-solving skills Good understanding of the ASIC design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification Communication and collaboration skills to work with a large world-wide design organization Desired skillset includes Experience in designs optimized for low power - Dynamic clock gating, Logic/ Memory power collapse Proficiency in Scripting languages (Python or Perl) for Automation initiatives, C/C++/SystemC for performance models Working knowledge of Synthesis, DFT, LEC, functional cover points/assertions, formal verification Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Title: Senior Engineer Metallurgist Location: Shirwal Pune Maharashtra Department: Quality / Metallurgy / Heat Treatment Reports To: Quality Manager / QA Plant Head Experience 5 to 8 years. Qualifications & Experience: Bachelor’s / Diploma in Metallurgy / Materials Science / Mechanical Engineering. Key Responsibilities: Lead and manage metallurgical lab operations including Metallography, Micro hardness, Induction hardening mould checking. Define and validate heat treatment processes such as Induction Hardening, Carburizing, Annealing, Tempering, and Stress Relieving. Manage and optimize surface treatment processes like Phosphating, Powder Coating, ED Coating, and Electroplating. Conduct and analyze failure investigations using microstructural analysis, hardness testing, and root cause analysis techniques. Ensure lab equipment is calibrated and maintained as per schedule (Spectrometer, Profile Projector, DFT meter, etc.). Conduct CQI assessments (CQI-9, CQI-11, CQI-12, CQI-15) for in-house and supplier processes. Analyze mechanical properties using Impact, Tensile, Jominy, SST, and Roughness testing. Evaluate and select material grades such as Carbon Steel, Alloy Steel, Tool Steel, Spring Steel, etc. Lead metallurgical failure analysis and generate technical reports for internal and customer use. Technical Skills: Proficient in Metallography, Heat Treatment, and Surface Treatment processes. Skilled in Spectrometry, Microstructure Analysis, Hardness Testing, and Salt Spray Testing. Strong understanding of Welding Metallurgy and associated destructive and non-destructive testing. Familiarity with manufacturing processes such as Forging, Casting, CNC, and VMC. Ability to interpret technical drawings and specifications, including GD&T and metallurgical standards. Minimum 4+ years of relevant experience in metallurgical lab functions, heat treatment, and quality engineering. Experience working with automotive OEMs and Tier-1 suppliers is an added advantage. Job Type: Full-time Pay: ₹400,000.00 - ₹600,000.00 per year Benefits: Provident Fund Schedule: Day shift Experience: Metallurgist: 10 years (Preferred) Automotive engineering: 10 years (Preferred) Work Location: In person

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL - DFT Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: The person is responsible for ensuring the integrity of a design by analyzing signal connectivity, specifically related to Design for Testability (DFT) features, utilizing Spyglass tools to identify and report potential violations within the test logic. Required Skills: Expertise should include and not limited to the following Strong understanding of digital circuit design principles and timing analysis concepts Experience with RTL design, synthesis Proficiency in scripting languages like TCL, Perl, or Python for automation Excellent problem-solving and debugging skills Strong communication and teamwork abilities to collaborate with cross-functional teams TekWissen® Group is an equal opportunity employer supporting workforce diversity. Show more Show less

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary Be a member of the team that plays a significant role in ensuring the quality of Connectivity SoCs through structured DFT, Automatic Test Pattern Generation (ATPG) and Memory Built-In Self-Test (MBIST) techniques. Primary Responsibilities Will Include, ▪ Interface with design team to ensure DFT design rules and coverages are met. ▪ Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. ▪ MBIST verification (including repair), test pattern generation through Mentor tool. ▪ ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. ▪ Work with the Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. ▪ Responsible for supporting post silicon debug effort, issue resolution. ▪ Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. ▪ Developing, enhancing and maintaining scripts as necessary Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Of 2-6 Years’ Experience In ASIC/DFT – simulation and Silicon validation ▪ Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement ▪ In depth knowledge and hands-on experience in ATPG - coverage analysis. ▪ In depth knowledge of Memory verification, repair and failure root-cause analysis. ▪ Experience With Any Of These Tools Is Required ▪ ATPG - TestKompress ▪ MBIST - Mentor ETVerify ▪ Simulation - VCS (preferred), modelsim. ▪ Expertise in scripting languages such as Perl, shell, etc. is an added advantage ▪ Ability to work in an international team, dynamic environment with good communication skills ▪ Ability to learn and adapt to new tools, methodologies. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3070714 Show more Show less

About the role: Allegion is seeking a highly motivated Senior Hardware Engineer to join our dynamic team, who will play a pivotal role in our engineering team, working collaboratively within a cross-functional environment to design and develop high-quality hardware and product solutions. This individual will possess strong technical skills in hardware design and a comprehensive understanding of the product design and development cycle. The ideal candidate is an organized self-starter who thrives in a fast-paced design culture. What you’ll do • Play a key role in design and development of hardware solutions, often working as part of a larger team to ensure successful project outcomes. • Develop and refine Hardware architectures, conducting studies to define and meet functional requirements. • Design and develop embedded electronics including wireless communications, ensuring integration and functionality. • Evaluate and optimize system performance, focusing on key performance indicators and design improvements. • PCB Design support with a focus on manufacturing and testing efficiency, collaborating effectively with manufacturing partners and ECAD Engineers. • Utilize design tools for automation and simulation to enhance product development processes. • Ensure defined product development processes and life cycle management are followed. • Collaborate with teams across different locations to manage all phases of the development process, ensuring alignment and project success. • Conduct testing and analysis to enhance hardware functionality and product reliability. • Demonstrate strong communication, collaboration, and leadership skills, fostering a positive and productive team environment. What we are looking for We are seeking a highly motivated Senior Hardware Engineer with at least five years of experience in hardware design and development. The ideal candidate will have a proven track record in contributing to complex projects, with strong problem-solving skills and expertise in embedded hardware and low power wireless designs. We value individuals who can manage and lead product development processes while ensuring quality and reliability. Strong organizational skills, attention to detail, and the ability to collaborate effectively with cross-functional teams and external partners are essential. Excellent communication and leadership abilities are crucial for fostering a collaborative team environment. Education B.E/B Tech or higher in EEE or ECE Preferred Skills Required Knowledge, Skills, and Abilities: • Expertise in designing / developing Embedded Systems based on Microcontroller/ Microprocessor, associated subsystems such as the Switching Power Supply, Electromechanical drives, Sensors, I/O interfaces, and wireless and wired communications modules. • Hands-on experience in design and verification of various communication protocols like UART, SPI, I2C, RS232, USB etc. • Experience in designing multi-layer PCB, with good understanding of DFM, DFT in accordance with industry standards like IPC and good collaboration with Contract Manufacturers. • Hands-on experience in EDA tools like Altium, LTSpice, PSpice etc. • Knowledge in short-range Wireless technologies like Wi-Fi, BLE, UWB, Zigbee or Z-wave. • Knowledge in RF performance criteria and concepts such as Output Power, Sensitivity, Spurious, Harmonics, Intermodulation, S-parameters, Smith charts and Tuning networks. • Commendable understanding of Design for EMI/EMC and troubleshooting compliance related failures. • Knowledge in configuring and using specialized test equipment like Power Analyzers, High Speed Oscilloscopes, Spectrum & Network Analyzers, RF Shield rooms/chambers. • Knowledge in Product Compliance and Reliability Testing, Root cause analysis, DFMEA, Encapsulation techniques, Manufacturing testing, and high-volume manufacturing processes and resulting design considerations. • Knowledge in manufacturing engineering, quality engineering and reliability engineering. • Seasoned in electronic product development processes & life cycle management. • Works collaboratively across multiple locations and technical teams to manage all the phases of Development process. • A role model in effective Communication, Collaboration, Networking, Emotional Resilience, Negotiation, working within a team environment and cross functionally. Work Culture Allegion is committed to building and maintaining a diverse and inclusive workplace. Together, we embrace all differences and similarities among colleagues, as well as the differences and similarities within the relationships that we foster with customers, suppliers, and the communities where we live and work. Whatever your background, experience, religion, age, gender, gender identity, disability status, sexual orientation, or any other characteristic protected by law, we will make sure that you have every opportunity to impress us in your application and the opportunity to give your best at work, not because we’re required to, but because it’s the right thing to do Show more Show less

Introduction As a Hardware Developer at IBM, you’ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable IBM customers to make better decisions quicker on the most trusted hardware platform in today’s market. Your Role And Responsibilities We are seeking highly motivated Test engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, delivery of DFT patterns and testing the patterns for IBM’s microprocessor chip design team. Preferred Education Master's Degree Required Technical And Professional Expertise 4–9 years of experience in ATE test development, silicon debug, and production support for complex SoC or ASIC devices. Strong expertise in test program development, test vector translation, timing setup, and ATE bring-up workflows. Proven ability in debugging test failures, analyzing yield and parametric issues, and resolving silicon bring-up and characterization challenges. Experience with RMA debug – reproducing, analyzing, and isolating failures in customer-returned or field-returned silicon. Hands-on experience with PVT (Process, Voltage, Temperature) characterization, using ATE. Experience in pattern generation, pattern retargeting, and vector-level debug using standard ATE tools (e.g., Teradyne, Advantest). Strong knowledge of pin margin analysis, voltage/timing margining, and correlation between simulation and ATE results. Proficient in automation and scripting using VB (Visual Basic), Perl, Python, and TCL for test flow automation, log parsing, and pattern manipulation. Effective collaboration with cross-functional teams including design, validation, product engineering, and silicon debug to ensure test robustness and quality. Excellent debug and bring-up skills – considered key requirements for this role. Detail-oriented with solid analytical and problem-solving abilities. Strong communication skills and ability to work across global teams. Preferred Technical And Professional Experience Experience with Teradyne UltraFlex (UFlex) tester is a plus. Familiarity with microcontroller architecture, embedded firmware, and functional verification concepts. Experience in post-silicon validation, system-level debug, and yield optimization workflows. Knowledge of processor-based test flows, scan diagnostics, and test time optimization Show more Show less

Alternate Job Titles: Senior Digital Design Engineer ASIC Design Engineer High-Speed SerDes Design Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a highly motivated and experienced ASIC Digital Design Engineer with a strong background in digital design for high-speed serial interfaces. You have a deep understanding of USB, PCIe, Ethernet, Display, and HDMI protocol standards, and you thrive in a collaborative environment. Your expertise in Verilog RTL design, microarchitecture, and timing constraints development makes you a valuable asset to any team. You are adept at using tools like Spyglass for CDC/RDC/Lint and have excellent debugging skills. Your ability to propose and implement design updates based on various requirements, coupled with your experience in test coverage and physical design timing closure, sets you apart as a leader in your field. With a passion for innovation and a keen eye for detail, you are ready to take on new challenges and contribute to the success of Synopsys. What You’ll Be Doing: Driving and working on digital design for high-speed serial interface PHY IPs for USBx, PCIex, Ethernet, Display, and HDMI protocol standards. Proposing micro-architecture of design/design updates based on customer requirements, analog requirements, system performance improvements, Link layer interface changes, or overall robustness of design. Implementing RTL in Verilog and running Spyglass CDC/RDC/Lint. Collaborating with verification teams to test desired functionality and corner cases. Developing timing constraints, DFT insertion, and test coverage, and closing timing with physical design teams. Well versed in Micro-Architecture and Block Ownership, Design from scratch. The Impact You Will Have: Enhancing the performance and reliability of high-speed serial interface PHY IPs. Contributing to the development of cutting-edge technologies that power modern electronics. Driving innovation in digital design and influencing the future of semiconductor technology. Collaborating with cross-functional teams to deliver robust and high-quality designs. Ensuring that Synopsys remains a leader in the semiconductor industry through continuous improvement and excellence. Supporting customers by providing high-performance and reliable IP solutions that meet their needs. What You’ll Need: 5-8 years of relevant experience in digital design for ASICs. Strong knowledge of Verilog RTL design and microarchitecture. Experience with timing constraints development and synthesis flow. Proficiency in using Spyglass or similar tools for Lint/CDC/RDC. Proficiency in scripting and automation using TCL, PERL, or Python. Excellent debugging skills and attention to detail. Who You Are: A collaborative team player with strong communication skills. A problem solver with a proactive approach to challenges. A detail-oriented professional with a passion for innovation. A self-motivated individual who thrives in a fast-paced environment. An adaptable engineer who can handle multiple tasks and priorities. The Team You’ll Be A Part Of: You will be part of the High-Speed SerDes Digital Design Team, a group of talented engineers dedicated to developing high-performance serial link PHY IPs. The team focuses on innovation, quality, and collaboration to deliver industry-leading solutions. Together, you will work on challenging projects that push the boundaries of technology and make a significant impact on the semiconductor industry. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

About Tata Electronics Private Limited Tata Electronics Pvt. Ltd. is a prominent global player in the electronics manufacturing industry, with fast-emerging capabilities in Electronics Manufacturing Services, Semiconductor Assembly & Test, Semiconductor Foundry, and Design Services. Established in 2020 as a greenfield venture of the Tata Group, the company aims to serve global customers through integrated offerings across a trusted electronics and semiconductor value chain. With a rapidly growing workforce, the company currently employs over 65,000 people and has significant operations in Gujarat, Assam, Tamil Nadu, and Karnataka, India. Tata Electronics is committed to creating a socioeconomic footprint by employing many women in its workforce and actively supporting local communities through initiatives in environment, education, healthcare, sports and livelihood. About the Job Description: Job Overview: Person will be responsible for developing multiple test chips for IP verification and drive optimized full-chip architecture for modular design. Will continue to push the boundaries of innovation by developing architectures that inherently support testability, with the objective of achieving zero-defect silicon. This will be driven by a "correct-by-construction" mindset throughout the design process. The role necessitates a comprehensive understanding and active involvement in all facets of VLSI development, including microarchitecture and platform architecture, front-end design, and design convergence. Additionally, the candidate will be responsible for overseeing the physical design and verification processes. Job Description: Full chip design for multimillion gates SoC Digital design and development (RTL) Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification Manage IP dependencies, planning and tracking of all front-end design related tasks Driving the project milestones across the design, verification and physical implementations Minimum Qualifications: Minimum 12 years of solid experience Test Chip / SoC design Solid expertise and understanding of digital design concepts. Developing architecture and micro-architecture from specs Understanding of JTAG base test chip architecture for IP testability and enable programmable registers for IP testability Ability to review full chip top level test plans Hands-on working knowledge and expertise in FEV, Cadence LEC & Synopsys Design Compiler Synthesis. Ability to make effective decisions, even with incomplete information when time is of essence. Working knowledge of timing closure is a must. Work on key design collaterals such as SDC and UPF flows. Work with key stakeholders like PD, DFT and Verification to discuss the right collateral quality and identify solutions/workarounds. Demonstrated good post silicon bring up and debug experience Demonstrated good SoC/ Test-Chip integration exposure and its challenges Demonstrated good exposure to design verification aspects Having SoC specification to GDS to commercialization experience is highly desired Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas. Provides direction, mentoring, and leadership to a small to medium sized groups. Should possess strong communication and leadership skills to ensure effective communication with Program Perform RTL coding for SS/SOC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks. Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Conduct timely review of the RTL progress and work with program managers to provide weekly update on the progress towards RTL milestones completion. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Should possess expertise in front-end EDA tools sign-off and its flows. Ability to program with scripting languages such as Python or Perl is a plus. Highly motivated to seek out solutions and willing to learn new skills to fulfil job requirements. Proven interpersonal skills, leadership and teamwork. Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC Understanding of Memory controller designs and Microprocessors is an added advantage Understanding of Chip IO design and packaging is an added advantage Show more Show less

ASIC/SOC Front End Design Engineer Job description: 1. Setup ASIC QA flows for RTL design quality checks. 2. Understand the design: top level interfaces, clock structure, reset structure, RAMs, CDC boundaries, power domains. 3. Running Lint, Synthesis, LEC, Static timing analysis, CDC, RDC, DFT, CLP steps. 4. Come up with clock constraints, false paths, multi-cycle paths, IO delays, exceptions and waivers. 5. Checking the flow errors, design errors & violations and reviewing the reports. 6. Debugging CDC, RDC issues and come up with the RTL fixes. 7. Supporting DFX team for DFX controller integration, Scan insertion, MBIST insertion and DFT DRC & MBIST checks. 8. Handling multiple PNR blocks, building wrappers and propagating constraints, waivers, etc. 9. Flows or Design porting to different technology libraries. 10. Generating RAMs based on targeted memory compilers and integrating with the RTL. 11. Running functional verification simulations as needed. Job Requirements: 1. B.E/M.E/M.Tech or B.S/M.S in EE/CE with 3 to 5 years of relevant experience 2. ASIC design flow and direct experience with ASIC design in sub-20nm technology nodes 3. Modern SOC tools including Spyglass, Synopsys design compiler & primetime, Questa CDC, Cadence Conformal, VCS simulation 4. Experience in signoff of front end quality checks & metrics for various milestones of the project 5. TCL, Perl, Python scripting Experience: 3 to 5 years Location: Hyderabad Notice Period: Immediate Show more Show less

NVIDIA is seeking passionate, highly motivated, and creative senior design engineers to be part of its Graphics team working on the design of state of the art memory subsystem components used in their industry-leading Graphics Processors. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will be expected to make architectural trade-offs based on features, performance requirements and system limitations, come up with micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design. You will work with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and backend teams to accomplish your tasks. What You’ll Be Doing Own micro-architecture and RTL development of design modules. Micro-architect features to meet performance, power and area requirements. Work with HW architects to define critical features. Collaborate with verification teams to verify the correctness of implemented features. Co-operate with timing, VLSI and Physical design teams to ensure design meets timing, interface requirements and is routable. Interact with FPGA and S/W teams to prototype the design and ensure that S/W is tested. Work on post-silicon verification and debug. What We Need To See BS / MS or equivalent experience. 4+ years of design experience. Experience in RTL design of complex design units for at least two or three projects. Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB). Deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug. Expertise in Verilog. Ways To Stand Out From The Crowd Design experience in memory subsystem or network interconnect IP. Good debugging and problem solving skills. Scripting knowledge (Python/Perl/shell). Leadership experience in leading small 2-3 member teams. Good interpersonal skills and ability & desire to work as a part of a team. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status. JR1965573 Show more Show less

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Design and implement DFT IP w/ Verilog/SystemVerilog and/or VHDL Design and implement RTL for DFT IP incl. POST, IST Develop synthesis automation for DFT IP including synthesis and timing constraints, RTL insertion and verification Own and maintain, extend, and enhance existing DFT IP like LBIST We’re doing work that matters. Help us solve what others can’t. Show more Show less

Job Title: Senior Engineer Metallurgist Location: Shirwal Pune Maharashtra Department: Quality / Metallurgy / Heat Treatment Reports To: Quality Manager / QA Plant Head Experience 5 to 8 years. Qualifications & Experience: Bachelor’s / Diploma in Metallurgy / Materials Science / Mechanical Engineering. Key Responsibilities: Lead and manage metallurgical lab operations including Metallography, Micro hardness, Induction hardening mould checking. Define and validate heat treatment processes such as Induction Hardening, Carburizing, Annealing, Tempering, and Stress Relieving. Manage and optimize surface treatment processes like Phosphating, Powder Coating, ED Coating, and Electroplating. Conduct and analyze failure investigations using microstructural analysis, hardness testing, and root cause analysis techniques. Ensure lab equipment is calibrated and maintained as per schedule (Spectrometer, Profile Projector, DFT meter, etc.). Conduct CQI assessments (CQI-9, CQI-11, CQI-12, CQI-15) for in-house and supplier processes. Analyze mechanical properties using Impact, Tensile, Jominy, SST, and Roughness testing. Evaluate and select material grades such as Carbon Steel, Alloy Steel, Tool Steel, Spring Steel, etc. Lead metallurgical failure analysis and generate technical reports for internal and customer use. Technical Skills: Proficient in Metallography, Heat Treatment, and Surface Treatment processes. Skilled in Spectrometry, Microstructure Analysis, Hardness Testing, and Salt Spray Testing. Strong understanding of Welding Metallurgy and associated destructive and non-destructive testing. Familiarity with manufacturing processes such as Forging, Casting, CNC, and VMC. Ability to interpret technical drawings and specifications, including GD&T and metallurgical standards. Minimum 4+ years of relevant experience in metallurgical lab functions, heat treatment, and quality engineering. Experience working with automotive OEMs and Tier-1 suppliers is an added advantage. Job Type: Full-time Pay: ₹400,000.00 - ₹600,000.00 per year Benefits: Provident Fund Schedule: Day shift Experience: Metallurgist: 10 years (Preferred) Automotive engineering: 10 years (Preferred) Work Location: In person

Location Hinjewadi, Pune - Maharashtra, India Pacesetting. Passionate. Together. HELLA, one of the leading automotive suppliers worldwide, has shaped the industry with innovative lighting systems and vehicle electronics. In addition, the company is one of the most important partners of the aftermarket and independent workshops. What motivates us: Shaping the mobility of tomorrow and fostering the central market trends such as autonomous driving, efficiency and electrification, connectivity and digitization as well as individualization. Every day, 36,000 employees worldwide are committed to this with passion, know-how and innovative strength. YOUR TASKS Experience: 3 to 5 years in product development within the automotive industry, specifically BCM/Lighting. Key Responsibilities Hardware Development: Design and develop hardware for Body Control Module (BCM) and lighting products in 2W/3W applications, ensuring compliance with automotive standards. Requirement Documentation: Prepare detailed hardware architecture, subsystem, and module-level requirement documents. Worst Case Analysis (WCA): Perform WCA for electronic circuits using advanced simulation software to ensure reliability and robustness. Component Selection: Select components based on WCA, design requirements, and cost optimization strategies. Circuit Design: Design circuit schematics using CADENCE Allegro, ensuring adherence to industry standards and best practices. PCB Design: Guide PCB designers to meet Electromagnetic Compatibility (EMC) requirements, ensuring minimal interference and optimal performance. Cross-functional Coordination: Collaborate with cross-functional teams including software, mechanical, and validation teams to ensure cohesive product development. DFMEA: Conduct Design Failure Mode and Effects Analysis (DFMEA) for hardware design and support in creating system-level FMEA. Cost-effective Solutions: Develop cost-effective design solutions in collaboration with program management, aligning with customer RFQ specifications. Must Requirements Design Lifecycle Experience: At least one complete design lifecycle experience from initial concept through to production. Requirement Writing: Proficiency in writing detailed hardware subsystem and module-level requirements. Circuit Simulation: Expertise in using circuit simulation tools such as LTspice for validating design concepts. DC-DC Converters: Strong fundamental knowledge of various types of DC-DC converters, Constant Current (CC) drivers, High Side & Low Side drivers. PCB Design Fundamentals: Excellent understanding of PCB design fundamentals, particularly for EMC requirements. EMI/EMC Standards: Experience with Electromagnetic Interference (EMI) and Electromagnetic Compatibility (EMC) standards in India and Europe. Thermal Calculations: Proficiency in performing thermal calculations for electronic circuits to ensure reliability under varying conditions. Manufacturability & Testability: Knowledge of Design for Manufacturability (DFM) and Design for Testability (DFT) principles. Cost Optimization: Understanding of cost optimization for electronic parts to achieve efficient Bill of Materials (BOM). DFMEA: Detailed working knowledge of Design Failure Mode and Effects Analysis (DFMEA). Additional Exposure: Experience with AC-DC converters, motor controllers, and magnetics design is a plus. Communication Skills: Excellent communication skills for effective collaboration and documentation. Skills And Experience Hardware Requirements: Writing detailed hardware subsystem and module-level requirements. Simulation Tools: Proficiency in circuit simulation tools (e.g., LTspice). Power Electronics: In-depth knowledge of DC-DC converters, CC drivers, High Side & Low Side drivers. PCB Design: Expertise in PCB design fundamentals for EMC. EMI/EMC Compliance: Familiarity with EMI/EMC standards in India and Europe. Thermal Management: Ability to perform thermal calculations for circuits. DFM/DFT: Understanding of Design for Manufacturability and Design for Testability. Cost Optimization: Skills in optimizing the cost of electronic parts for BOM. DFMEA: Proficiency in DFMEA. Advanced Electronics: Exposure to AC-DC converters, motor controllers, magnetics design (plus). Communication: Strong communication skills for effective teamwork and documentation. Your Qualifications BE /B. Tech/ M.E/ M. Tech in Electronics/Electronics & Communication/Industrial Electronics 3-5 years of experience in Automotive Product development Industry English, both written and spoken. [German Language Preferred] Location 5 Days week - Work from Office from Hinjewadi Phase -1. Take the opportunity to reveal your potential within a global, family-run company that offers you the best possible conditions for progressing in your career. Please send us your application through our careers portal, citing reference number req16340. HELLA eMobionics Private Limited Rimsha Shaikh Show more Show less

Role Description Role Proficiency: Ability to e xecute any small to mid size customer project in any field of VLSI Frontend Backend or Analog design with minimal supervision Outcomes Work as an individual contributor to own any one task of RTL Design/Module and provide support to junior engineers in Verification/PD/DFT/Circuit Design/Analog Layout/STA/Synthesis/Design Checks/Signoff etc. Independently analyze and complete the assigned task in the defined domain(s) successfully and on-time On time quality delivery approved by the project lead/manager Measures Of Outcomes Quality –verified using relevant metrics by Lead/Manager Timely delivery - verified using relevant metrics by Lead/Manager Reduction in cycle time and cost using innovative approaches Number of trainings attended Number of new projects handled Outputs Expected Quality of the deliverables: Ensure clean delivery of the design and module in-terms of ease in integration at the top level Meet functional spec / design guidelines 100% of the time without any deviation or limitation Documentation of the tasks and work performed Timely Delivery Meeting project timelines as requested by the program manager Support the team lead in intermediate tasks delivery Team Work Participation in team work; supporting team members/lead at the time of need Able to perform additional tasks in-case any team member(s) is not available Innovation & Creativity Automate repeated tasks to save design cycle time as a necessary approach Participation in technical discussion training forum Skill Examples Languages and Programming skills:a. System Verilog Verilog VHDL UVM C C++ Assembly Perl TCL/TK Makefile Spice (any one) EDA Tools: a. Cadence Synopsys Mentor tool sets (one or more)b. Simulators Lint CDC/RDC DC/RTL-C ICC/Innovus/Olympus ETS/TK/FS PT/Tempus Calibre etc. (any one) Technical Knowledge: (any one)a. Partially implement IP Spec Architecture Design Micro Architecture Functional Spec Test Plan Verificationb. Strong in Bus Protocol AHB/AXI/PCIe/USB/Ethernet/SPI/I2C Microprocessor architecturec. Strong knowledge in Physical Design / Circuit Design / Analog Layout d. Strong understanding of Synthesis DFT Floorplan Clocks P&R STA Extraction Physical Verificatione. Strong knowledge of Soft / Hard / Mixed Signal IP Design Processor Hardening FPGA Design Technology: CMOS FinFet FDSOI - 28nm / 22nm / 16ff / 10nm and below Strong communication skills Good analytical reasoning and problem-solving skills with attention to details Able to deliver the tasks on-time per quality guidelines and GANTT in every instance. Required technical skills and prior design knowledge to execute the assigned tasks Ability to learn new skills in-case required technical skills are not present to a level needed to execute the project Knowledge Examples Frontend / Backend / Analog Design:a. Project experience in any of the design by executing any one of – RTL Design / Verification / DFT / Physical Design / STA / PV / Circuit Design / Analog Layout etc.b. Strong understanding of the design flow and methodologies used in designing Understanding of the technical specs and assigned tasks: Understand the assigned tasks and have strong knowledge to execute the project tasks assigned by the client / manager as per shown skill Additional Comments Experience- 4+yrs Analog Layout Candidate should work independently on block level and chip level Analog layout design, coordinating with the circuit designer & the project lead. Candidate should have minimum 3+ years of hands-on experience in Analog layout. Custom layout experience in DAC, ADC, Band gap, Regulators, LDOs etc. Knowledge of finfet or technology exposure to 28nm or below is an added advantage. Full Understanding of IC fabrication and reliability issues. Full familiarity with Cadence-Virtuoso, PVS, ASSURA and Calibre tools. Outstanding written and verbal communication skills. Skills Analog Layout,Finfet,Cadence Virtuoso Show more Show less

Expert in implementing Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. In your new role you will: Responsible for SoC DFT Architecture definition/implementation/verification/silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug, Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at/TDF/Bridging/Cell-aware/iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. Hands on experience in analysis and debug of above-mentioned test domains. Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies. The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Degree & Discipline: BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design. Experience in Industry: 12+ years of in DFT implementation, verification and post silicon debug areas. #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. This means we embrace diversity and inclusion and welcome everyone for who they are. At Infineon, we offer a working environment characterized by trust, openness, respect and tolerance and are committed to give all applicants and employees equal opportunities. We base our recruiting decisions on the applicant´s experience and skills. Please let your recruiter know if they need to pay special attention to something in order to enable your participation in the interview process. Click here for more information about Diversity & Inclusion at Infineon. Show more Show less

Job Details The Candidate will be involved in all aspects of DFT with prime focus on selected Deliverables. He/She will get exposure to SoC level DFT practices and Post-Silicon Debugs. The Team is responsible for delivering Ultra Low Power MCUs that will cater to today's IOT & Edge Processing Needs with applications varying from industrial to consumer wearable devices. Requirements BTech/ MTech with minimum 2years of Relevant Experience. Strong DFT Concepts with HandsON experience on DFT Tools & Methodologies. Experience on ATPG, Scan Insertion, DFT-DRCs, GLS, is preferred. Perl/TCL Scripting. Strong Analytical & Problem Solving Skills MBIST/LBIST is a plus More information about NXP in India... Show more Show less

Alternate Job Titles: DFT Solutions Engineer Design for Test Engineer DFT Project Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced Solutions Engineer with a proven track record in project execution and overall project management within the semiconductor industry. You excel in deploying Synopsys DFT technologies on customer designs, ensuring projects are completed on schedule and with high quality. You are adept at managing multiple projects simultaneously, recognizing and mitigating risks, and working proactively on contingency plans. You possess exceptional verbal and written communication skills, leadership abilities, and a strong teamwork ethic. Your proficiency in PowerPoint, Excel, and Word, along with your ability to work unsupervised, makes you a valuable asset to any team. You have a solid background in the implementation of DFT technologies and are eager to work cross-functionally with internal teams, gaining exposure and visibility on a global scale throughout the organization. What You’ll Be Doing: Deploying Synopsys DFT technologies on key customers’ designs and successfully executing the project. Acting as the focal point of contact and managing all external and internal communications across cross-functional teams. Planning and directing project schedules, identifying and escalating issues, and driving problems to resolution. Identifying and managing risks, ensuring the completion of projects on schedule and with high quality. Organizing interdepartmental activities and ensuring clear and concise communication. Working closely with internal teams (Applications Engineering, R&D) to meet customer requirements and achieve goals and targets. The Impact You Will Have: Ensure successful deployment of Synopsys DFT technologies on customer designs. Facilitate effective communication and coordination between cross-functional teams. Drive projects to completion, meeting deadlines and maintaining high standards of quality. Identify and mitigate risks to ensure project success. Contribute to the overall success of Synopsys by delivering high-quality solutions that meet customer needs. Enhance customer satisfaction and build strong, long-lasting relationships with key customers. What You’ll Need: Solid background and proven track record in the implementation of DFT technologies. Experience in deploying Scan Compression, On-chip DFT Fabric, ATPG, Diagnosis, MemoryBIST, LogicBIST, and Boundary Scan. Proficiency in project management and the ability to manage multiple projects simultaneously. Exceptional verbal/written communication, leadership, interpersonal, and teamwork skills. Good working knowledge of PowerPoint, Excel, and Word. Who You Are: A detail-oriented and process-driven professional with a strong engineering background. You possess excellent organizational skills and the ability to communicate effectively across various levels of the organization. You are a proactive problem-solver who can work independently and within a team. Your leadership abilities and teamwork ethic enable you to drive projects to successful completion, ensuring high-quality outcomes and customer satisfaction. The Team You’ll Be A Part Of: You will be part of a dynamic and innovative team that focuses on deploying Synopsys DFT technologies to key customer designs. This team works cross-functionally with internal teams such as Applications Engineering and R&D, and has a global presence within the organization. Together, you will strive to meet customer requirements and achieve project goals, contributing to the overall success of Synopsys. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Job Title: PCB Designer (Cadence Allegro) – 2 to 3 Years Experience Location: Bengaluru Job Type: Full-Time Experience: 2–3 Years Industry: Electronics / Semiconductor / Hardware Department: Engineering / Hardware Design Job Description: We are seeking a motivated and detail-oriented PCB Designer with 2–3 years of hands-on experience in Cadence Allegro to join our hardware design team. The ideal candidate will be responsible for translating schematic diagrams into precise PCB layouts that meet electrical, mechanical, and manufacturing requirements. Key Responsibilities: Create multi-layer PCB layouts using Cadence Allegro PCB Designer software. Collaborate with hardware engineers to interpret schematics and define layout constraints. Perform component placement, routing, and optimization based on electrical and thermal considerations. Generate and validate manufacturing outputs (Gerber, ODB++, drill files, BOM). Perform DRC (Design Rule Check), ERC (Electrical Rule Check), and resolve design issues. Work with the fabrication and assembly teams to resolve design-related manufacturing concerns. Maintain PCB libraries and ensure adherence to company design standards. Support design reviews and make necessary modifications based on feedback. Requirements: Bachelor’s Degree or Diploma in Electronics Engineering or a related field. 2–3 years of proven experience in PCB layout design using Cadence Allegro . Good understanding of signal integrity, power distribution, and EMI/EMC best practices. Familiarity with high-speed design, differential pairs, impedance control, and HDI boards is a plus. Strong attention to detail and ability to handle multiple design projects simultaneously. Effective communication and teamwork skills. Preferred Skills: Experience with schematic capture tools (e.g., OrCAD Capture). Knowledge of IPC standards and DFM/DFT practices. Experience in working with contract manufacturers and fabrication houses. Show more Show less

Role Summary: We are seeking a detail-oriented and innovative Electronics R&D Engineer to join our dynamic team focused on the development of home audio products including soundbars, portable speakers, TWS earbuds, and party speakers . The ideal candidate will support the end-to-end development cycle, from component specification and BOM creation to compliance and vendor coordination. Key Responsibilities: Design, evaluate, and optimize electronic circuits for consumer audio products Develop and manage comprehensive Bill of Materials (BOM) and product specification documentation Collaborate with cross-functional teams to ensure seamless electrical-mechanical integration Interface with vendors and OEM partners for part development, sourcing, and feasibility reviews Ensure adherence to relevant regulatory and compliance standards (BIS, CE, ROHS, WPC, etc.) Participate in prototype development, validation testing, and iterative improvements Contribute to DFM/DFT/DFX reviews to ensure scalability and cost-effectiveness Stay abreast of emerging technologies and trends in consumer electronics and audio systems Required Skills & Competencies: Strong understanding of analog/digital electronics and embedded systems Proficiency in PCB design software (e.g., Altium Designer, Eagle, KiCad) Familiarity with Bluetooth/Wi-Fi modules, microcontrollers, and audio ICs Basic knowledge of product certifications, EMI/EMC requirements, and quality standards Proficient in MS Excel and engineering documentation tools Preferred Qualifications: Internship or academic experience in audio product development Exposure to ODM/EMS collaboration workflows Knowledge of compliance documentation and test procedures Show more Show less

DFT Lead / Manager Location: Bangalore Description Our main business focuses on automotive microcontrollers and SoCs. The solutions cover a wide range, such as Edge-ECU to ADAS applications, dedicated to creating a comprehensive solution for automotive chips. we will continue to integrate the latest electronic and electrical architecture (E/EA) designs from automakers, realize the demands of the next-generation software-defined vehicle, and apply a chip design-oriented, human-centric service-oriented architecture (SOA) to the automotive field. This approach aims to meet the diverse neaeds of users and provide consumers with a new user experience. Job Location: Bangalore We are seeking a skilled Design for Test (DFT) Architect/Lead/Manager to join our team. This role is pivotal in ensuring the testability and manufacturability of our ASIC/SoC products designed for the automotive industry. The ideal candidate will have extensive experience in DFT methodologies and will lead a team of engineers to develop robust test strategies that meet industry standards. Key Responsibilities: DFT Strategy Development: Design and implement DFT methodologies for ASIC/SoC products, focusing on automotive applications to ensure high quality and reliability. Architecture Design: Collaborate with hardware and software teams to integrate DFT features into the product architecture, ensuring compatibility with automotive testing standards. Team Leadership: Lead a team of DFT engineers, providing mentorship and technical guidance to enhance their skills and capabilities. Test Planning: Develop comprehensive test plans, including ATPG, BIST, and scan insertion strategies, to optimize fault coverage and reduce test costs. Collaboration: Work closely with design, validation, and manufacturing teams to align DFT strategies with overall product goals and requirements. Quality Assurance: Establish metrics and benchmarks for DFT processes, and ensure compliance with automotive industry standards (e.g., ISO 26262). Tool Development: Evaluate and implement DFT tools and methodologies to improve test efficiency and effectiveness. Continuous Improvement: Stay updated with industry trends and technologies in DFT and automotive testing, driving innovation within the team. Qualifications: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field. 10+ years of experience in DFT for ASIC/SoC design, with a strong background in automotive applications. Proven experience leading DFT teams and managing complex projects. In-depth knowledge of DFT techniques such as scan design, boundary scan, BIST, and fault simulation. Familiarity with automotive industry standards and regulations (e.g., ISO 26262). Proficiency in using DFT tools and EDA software. Strong problem-solving skills and ability to work collaboratively in a fast-paced environment. Excellent communication skills, both verbal and written. Contact: Uday Mulya Technologies muday_bhaskar@yahoo.com "Mining The Knowledge Community" Show more Show less