1121 Dft Jobs - Page 33

Engineer / Sr Engineer (Linux BSP), eInfochips, 4 - 10 years, Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore - ACHNET Are you sure you want to cancel? Are you sure you want to cancel this Profile? You can always come back later Edit Profile The first thing people see You do not have permission to access the Talent Management menu. This section is restricted to Admins and Editors only. If you believe you should have access, please contact your administrator for assistance. YOUR BROWSER IS NOT SUPPORTED To view this experience, please upgade to the latest one of these browsers Engineer / Sr Engineer (Linux Bsp) DESCRIPTION Job Description, Role Responsibilities POSITION TITLE: EXPERIENCE: Role: LOCATION: Engineer / Sr Engineer (Linux BSP) 4-10 Years Linux BSP Ahmedabad, Pune, Noida, Hyderabad, Chennai, Indore Company Profile eInfochips An Arrow Company (www.einfochips.com) is a leading global provider of product engineering and semiconductor design services. With over 500+ products developed and 40M deployments in 140 countries, eInfochips continues to fuel technological innovations in multiple verticals. The company s service offerings include digital transformation and connected IoT solutions, Including IoT Security, across various cloud platforms, including AWS and Azure. Our work culture is built over years of experience in providing innovative solutions to our clients and our indomitable spirit to excel in all aspects of our engagement. We believe that our success lies upon the skills and quality of our people we work with. Silicon engineering services: ASIC / FPGA Design Development, Design Verification Validation, Physical Design DFT Embedded systems engineering services: Hardware Design, System Software, System Verification Validation, Multimedia Software engineering services: Cloud Enablement, IoT Mobility, Application Software, QA and Test Automation, BI and Data Visualization Extended services: New Product Development, Lifecycle Management, Product Sustenance IPs: DevOps for IoT, IoT Gateway Framework, IoT Device Lifecycle Management, Video Management Software, Reusable Camera Framework, Test Automation Framework, Reference Designs EVMs, Verification IPs, OptiX Physical Design Framework About Arrow Electronics Arrow Electronics (www.arrow.com) guides innovation forward for over 220,000 leading technology manufacturers and service providers. With 2021 sales of $34.48 billion, we develop technology solutions that improve business and daily life. Our strategic direction of guiding innovation forward is expressed as Five Years Out (Five Years Out | Arrow Electronics), a way of thinking about the tangible future to bridge the gap between what s possible and the practical technologies to make it happen. www.einfochips.com Key Responsibilities Responsible for design and development of real time embedded software/firmware and PC/mobile based software application. To Analyse domain specific technical or low level requirement and modification as per end customer or system requirement. Participate in High level and low level software design Perform software testing including unit, functional and system level requirement including manual and automated Performs software requirement to design to coding to testing traceability Performs code review following coding guidelines and static code analysis Troubleshoots software problems of limited difficulty. Documenting technical deliverable like software specifications, design document, code commenting, test cases and test report, Release note etc. throughout the project life cycle. Follow defined process for software Development life cycle Develops software solutions from established programming languages or by learning new language required for specific project. Experience / Skills Required Strong knowledge for Linux device drivers, Linux Kernel Programming, Linux Kernel Internals, Yocto / Buildroot or any other build systems Experience working with development tools like oscilloscope, protocol analyser, emulator, signal generator, JTAG programmer, GIT, SVN, JIRA. Experience working with different embedded microprocessor based on Qualcomm, TI, NXP, NVIDIA, Intel or similar Experience of Board support package, Device driver and boot loader development/porting. Understanding of hardware schematic, datasheet of hardware component to derive firmware/software specific solution Strong sense of ownership, passionate, fast learner, analytical mind set, perfection seeker. Personal Attributes The ideal candidate should have strong Team-work characteristics, being both action and results oriented. He/she will be a hands-on, roll-up-the-sleeves type engineer with a whatever it takes to get it done attitude. The successful candidate must be effective operating in a multi disciplined technology environment coupled with an obsession for responsiveness to Project requirements. The successful candidate should be open to learn new processes and technologies. In addition, the right candidate will: Incumbent works under general supervision Incumbent has substantial experience to resolve problems and concepts Incumbent can work on complex concepts and implementation www.einfochips.com Be a highly energetic self-starter Be an open and excellent communicator Have exceptional interpersonal skills Be a consummate team player Interface well with Client Engineer Team members and other Business Units of eInfochips Finally, this individual must have an uncompromising level of personal integrity. Education A Graduate degree in Electronics and communication/Information Technology/Computer-Science is required. A Masters technical degree is highly desirable.

Work together with system architects and micro architects to define high level specifications that are implementable. Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. Provide support to functional validation teams in post silicon debug. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency. Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Emulation Engineer [Location: Noida] Experince: 10-20 Years [ Location: NOIDA] We are seeking a diligent Emulation leader to join our team at Renesas. Responsibilities include enhancing build/debug emulation methodology and flows, develop capabilities to run simulation testbench with emulation build, working with design/verification teams for XTOR building, selecting hardware, interfacing with software/platform teams, and setting high-level technical vision, along with executing the system-level-scenarios to ensure the quality (zero-bug) silicon tape-out. Responsibilities: Create full chip emulation and FPGA prototype models for the complex automotive SoC designs Create the test sanity suite to validate the models, having various integrated transactors and memory models Develop and apply automation aids, flows and scripts to improve emulation ease of use for the users Innovate improvements to emulation methodology, working with partners across other geographies Train and mentor engineers to deliver high quality and increase productivity Build strong collaboration with other R&D teams such as Design, Verification, digital IP, Design Enablement, and Validation to achieve project milestones Drive SoC verification using emulation (Hardware Assisted Verification), includes working with design, system-architect, verification teams to develop and execute the test plans for system-level-scenarios on emulation/prototype platform Work with the EDA vendors to deploy next generation emulation technologies Qualifications Qualifications: M.Tech/B.Tech Degree in Electrical/Electronic Engineering and a minimum of 4+ years relevant industry experience Emulation experience on any/all available platforms (Palladium, Protium, Veloce or Zebu, EP) including design bring-up, build flow, debug, performance and throughput tuning Experience with Verilog, VHDL complex SoC design Experience with System Verilog, UVM, C/C++ verification environment Knowledge of communication/interface protocols would be a plus: MIPI (CSI/DSI), PCIe, UCIe, ENET, LPDDR5/4, Hyper/Octal Flashes, eMMC, SD, UFS Knowledge of DFT and GLE flows would be a plus Know-How of the AI workload and its performance aspects would be a big plus Proficient in writing scripts using any languages (Perl, TCL, bash, Python) Experience with waveform debug tools, simvision/Verdi Strong communication skills and ability to work as a team Company Description Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industry s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier .

Work together with system architects and micro architects to define high level specifications that are implementable. Contribute to RTL development including running tool flows like lint, CDC, Conformal low power and DFT checks Work closely with functional verification teams on test-plan development and debug. Understand timing constraints, run synthesis and deliver synthesized netlist to PD team and provide constraints support for PD teams. UPF writing, power aware equivalence checks and low power checks. Collaborate with other functional teams including DFT, physical design and emulation teams to achieve project milestones. Provide support to functional validation teams in post silicon debug. Qualifications MTech/BTech in EE/CS with hardware engineering experience of 1 to 15 years. Experience in micro-architecture development, RTL design, front-end flows (Lint, CDC, low-power checks, etc.), synthesis/DFT/FV/STA Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency. Experience in protocols like AHB/AXI/CHI, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers. Strong domain knowledge of clocking, system modes, power management, debug, security and other architectures is a must. Any of following experience would be a plus: High Speed Peripherals like DDR, PCIe, Ethernet, GPU, VPU (Video Processing Unit); NIC/FlexNOC interconnect; Flash memory subsystems. Experience with post-silicon bring-up and debug is a plus. Able to work with teams across the globe and possess good communication skills Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Basic qualifications: Strong academic and technical background in electrical engineering. A Bachelor s degree in EE / Computer is required, and a Master s degree is preferred. 3 years experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! Required experience : Hands-on and thorough knowledge of synthesis, place and route, timing, extraction and other backend tools and methodologies for technologies 16nm or less. Proven expertise in synthesis, timing closure and formal verification (equivalence) at the block and full-chip level. Full chip or block level ownership from architecture to GDSII, driving multiple complex designs to production. Experience with Cadence and/or Synopsys physical design tools/flows. Familiarity and working knowledge of System Verilog/Verilog. Experience with DFT tools and techniques. Experience in working with IP vendors for both RTL and hard-mac blocks. Good scripting skills in python or Perl Preferred experience: Good knowledge of design for test (DFT), stuck-at and transition scan test insertion. Familiarity with DFT test coverage and debug. Familiarity with ECO methodologies and tools. Your base salary will be determined based on your experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

As a Hardware at , you ll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today s market. Your role and responsibilities As Logic deisgn engineer for Power Management, you will be responsible for design and development of power management and sustainability features for high performance Processors chips. 1. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions 2. Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature 3. Guide junior engineers. Represent as Power engineer in various forums. 4. Signoff the Pre-silicon Design that meets all the functional, area and timing goals 5. Participate in silicon bring-up and validation of the hardwar 6. Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-8 years of work experience of one or more areas Power management Architecture/ microarchitecture/ Logic design - Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. 1. Experience of working on Power Management designs handling Power/Performance States, Stop states of Core and Cache, Chip and System thermal management and power supply current over-limit management 2. Experience in working with research, architecture/ FW/ OS teams 3. Experience in low power logic design 4. Experience in working with verification, validation for design closure including test plan reviews, verification coverage 5. Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high- performance design and timing closure of high frequency designs 6. Experience in silicon bring-up ABOUT BUSINESS UNIT

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! NVIDIA is looking for a best-in-class ASIC STA Engineer to join our outstanding Networking Silicon engineering team, developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency for today's AI platforms! Come and take a part in designing our groundbreaking large scale and innovating chips, enjoy working in a meaningful, growing and highly professional environment where you make a significant impact in a technology-focused company. What You Will Be Doing Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff. Take part in top level floor plan and clock planning. Optimize, together with CAD signoff flows and methodologies. Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence. Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency. What We Need To See B.SC./ M.SC. in Electrical Engineering/Computer Engineering. 3-8 years of experience in physical design and STA Proven experience in RTL2GDS and STA design and convergence Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.) Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required. Great teammate. NVIDIA has some of the most forward-thinking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Are you ready to become the engineer you always wanted to be? Come and be part of the best physical design team in the industry! JR1995153 Show more Show less

ACL Digital is looking for a talented and experienced STA (Static Timing Analysis) Engineer to join our growing VLSI team! If you have experience in timing analysis and have worked on full-chip designs , we want to hear from you. Role & Responsibilities: Drive full-chip STA from RTL to GDSII Develop and validate timing constraints (SDC) for complex SoCs Perform timing closure and sign-off using tools like PrimeTime Collaborate with RTL, physical design, and DFT teams for ECOs and timing fixes Analyze timing reports, debug violations, and propose optimization strategies Key Requirements: 5–10 years of hands-on experience in Static Timing Analysis Proven track record in full-chip STA and timing sign-off Strong knowledge of timing constraints, multi-mode/multi-corner (MMMC) flows Familiar with scripting (TCL, Perl) and STA tools (Synopsys PrimeTime preferred) Excellent analytical, debugging, and cross-team communication skills Location: Pune/Bangalore Notice period: Immediate Why ACL Digital? At ACL Digital, you’ll be part of a fast-paced team delivering next-gen semiconductor solutions. We offer opportunities to work on cutting-edge technology with top-tier clients across the globe. Show more Show less

Emulation Engineer [Location: Noida] Experince: 8-12 Years [ Location: NOIDA] We are seeking a diligent Emulation leader to join our team at Renesas. Responsibilities include enhancing build/debug emulation methodology and flows, develop capabilities to run simulation testbench with emulation build, working with design/verification teams for XTOR building, selecting hardware, interfacing with software/platform teams, and setting high-level technical vision, along with executing the system-level-scenarios to ensure the quality (zero-bug) silicon tape-out. Responsibilities: Create full chip emulation and FPGA prototype models for the complex automotive SoC designs Create the test sanity suite to validate the models, having various integrated transactors and memory models Develop and apply automation aids, flows and scripts to improve emulation ease of use for the users Innovate improvements to emulation methodology, working with partners across other geographies Train and mentor engineers to deliver high quality and increase productivity Build strong collaboration with other RD teams such as Design, Verification, digital IP, Design Enablement, and Validation to achieve project milestones Drive SoC verification using emulation (Hardware Assisted Verification), includes working with design, system-architect, verification teams to develop and execute the test plans for system-level-scenarios on emulation/prototype platform Work with the EDA vendors to deploy next generation emulation technologies Qualifications M. Tech/B. Tech Degree in Electrical/Electronic Engineering and a minimum of 4+ years relevant industry experience Emulation experience on any/all available platforms (Palladium, Protium, Veloce or Zebu, EP) including design bring-up, build flow, debug, performance and throughput tuning Experience with Verilog, VHDL complex SoC design Experience with System Verilog, UVM, C/C++ verification environment Knowledge of communication/interface protocols would be a plus: MIPI (CSI/DSI), PCIe, UCIe, ENET, LPDDR5/4, Hyper/Octal Flashes, eMMC, SD, UFS Knowledge of DFT and GLE flows would be a plus Know-How of the AI workload and its performance aspects would be a big plus Proficient in writing scripts using any languages (Perl, TCL, bash, Python) Experience with waveform debug tools, simvision/Verdi Strong communication skills and ability to work as a team Company Description Renesas is an embedded semiconductor solution provider driven by its Purpose To Make Our Lives Easier . As the industry s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog Connectivity, and Power. With a diverse team of over 21, 000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, To Make Our Lives Easier .

Analog and Connectivity Business Unit (AC) is looking for a Staff Product Engineer to join our team to drive the product development of state-of-the-art Sensor Signal Conditioning products. This is a unique and exciting opportunity to work with a cross-functional team to bring a product to volume production starting from product conception to production release. The job scope includes but is not limited to, development of the test plan to ensure datasheet specifications are met. Own the qualification plan and the execution to comply with various JEDEC/AEC quality standards. Own product quality assessment through reliability tests. Collaborate with multi-functional teams such as Design, Test, Applications and Failure Analysis teams during first silicon debug and to root cause field failures. Creation and maintenance of product BOM. Monitor production data to address yield and quality deficiencies using statistical analysis. KEY RESPONSIBILITIES Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers Definition of ATE test, qualification and manufacturing plans Product release into manufacturing with adherence to stringent tier 1-customer requirements Datasheet and automotive compliance reports Real time customer support for design, product and quality related issues Temperature/Voltage/Process characterization and production limit setting Product new product introduction and yield ownership Product BOM release and maintenance Excursion management for both suppliers and customers Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste Qualifications 12+ years experience in product engineering. A strong analog circuit background is a must. Familiarity with ATE tester platforms (eg. Advantest 93K) Knowledge of analog and mix-signal circuitry and the common building blocks, device physics, test methodology and DFT knowledge Experience with common lab test equipment (DC power supply, oscilloscope, multi-meters etc). Bench characterization experience is a plus Familiarity with JEDEC/AEC qualification standards and stress test conditions. Experience with qual hardware/software development would be preferred Experience in yield management tools such as Spotfire, JMP. Apply statistical analysis to isolate the issue and make data-driven decisions Ability to managing supplier excursions and customer escalations through problem solving Knowledge of Semiconductor Failure Analysis is preferable Strong verbal and written communication skills A good team player. Effective in fast paced, dynamic work environment EDUCATION: BS in Electrical/Electronic Engineering MS in Electrical/Electronic Engineering is preferred Company Description Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what s next in electronics.

Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers Definition of ATE test, qualification and manufacturing plans Product release into manufacturing with adherence to stringent tier 1-customer requirements Datasheet and automotive compliance reports Real time customer support for design, product and quality related issues Temperature/Voltage/Process characterization and production limit setting Product new product introduction and yield ownership Product BOM release and maintenance Excursion management for both suppliers and customers Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste REQUIREMENTS: 7+ years experience in product engineering. A strong analog circuit background is a must. Familiarity with power management IC testing would be a plus Familiarity with ATE tester platforms (eg. Teradyne J750, Advantest 93K) Knowledge of analog and mix-signal circuitry and the common building blocks, device physics, test methodology and DFT knowledge Experience with common lab test equipment (DC power supply, oscilloscope, multi-meters etc). Bench characterization experience is a plus Familiarity with JEDEC/AEC qualification standards and stress test conditions. Experience with qual hardware/software development would be preferred Experience in yield management tools such as PDF Exensio, JMP. Apply statistical analysis to isolate the issue and make data-driven decisions Ability to managing supplier excursions and customer escalations through problem solving Knowledge of Semiconductor Failure Analysis is preferable Strong verbal and written communication skills A good team player. Effective in fast paced, dynamic work environment Qualifications BS in Electrical/Electronic Engineering MS in Electrical/Electronic Engineering is preferred Company Description Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what s next in electronics.

Manage multiple new products through their full product lifecycle, Product Compliance to Sustainment of production released parts Generate Characterization, Qualification, Bench-to-ATE Correlation and Test Limit plans for new products based on REA guidelines and JEDEC standards Drive measurements/data collection and statistical analysis for Characterization, Qualification, Correlation, Production Test Limit setting, and any other specialized testing for datasheet parameters Cost reduction via yield improvement and test time reduction from safe launch study at both NPI and MP stage. Excursion management (Low yield and RMAs) and MRB lot disposition. Work with DE/TE team to design and implement production test solutions. Continually look for opportunities to improve the NPI process. Focus areas include streamlining Test, Qualification and Characterization plans and strategies, reducing documentation overhead, and leveraging NPI efficiencies such as Qualification by Similarity (QBS) Be a mentor to junior Product Engineering team members to accelerate their technical and career growth Contribute technical expertise to business critical projects as required to advance MID (Memory Interface Division) business objectives Qualifications Preferred with 10+ years experience from Product Engineer, Quality Engineer, Test Engineer, Validation Engineer and FA Engineer in fabless. Deep knowledge of Digital / Analog Product Characterization Technique. Hands-on experience to work on Characterization Plan, PVT test, Report. Strong statistical data analysis background for NPI/MP products. Hands-on experience from PDF (TIBCO Spotfire, Exensio), JMP, Galaxy Examinator, VB, etc. Strong working knowledge of Product / Package Qualification Process. Hands-on experience from HTOL / ESD / LU / HTS / TC / ELFR / UHAST / Endurance / Retention, etc. Experienced in ATE testing on V93K (PS1600 /PS9G/PSSL) ATE testers in CP/FT test. Hands-on experience from ATE test debug analysis with Test program , STDF, datalog, etc. Experienced in Bench testing of Electrical Characteristics, Tx/Rx Jitter, Eye Diagram for Memory Interface Products (RCD, DB, TS, SPD, etc) Familiar with Digital / Analog Product DFT / DFM method. JEDECT Spec and Product Datasheet. Deep knowledge of CMOS Process in HKMG / FINFET process. Ability to manage complex projects in parallel and on schedule . Preferred with Project Management experience. Solid organizational skills with attention to detail for risk management Good communication / reporting skills Self-motivated to work independently and in a team environment with project teams from different regions / timezones High energy, driven-to-succeed personality in fast pace environment Experience working with databases and creating regular reports Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

: We are looking for a highly skilled and experienced Physical Design Lead to join our VLSI team. The ideal candidate will have a strong background in physical design and a deep understanding of the VLSI design flow. This role involves leading a team of engineers and working closely with cross-functional teams to ensure the successful implementation and optimization of physical designs. Key Responsibilities: Lead the physical design team in the implementation of complex digital designs, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Collaborate with RTL design, verification, and DFT teams to ensure design quality and robustness. Develop and implement physical design methodologies and best practices to improve design efficiency and quality. Perform static timing analysis, power analysis, and signal integrity analysis to ensure design performance and reliability. Interface with foundry and EDA tool vendors to resolve design issues and improve design flow. Mentor and coach junior engineers, providing technical guidance and support. Participate in design reviews and provide feedback to improve design quality and efficiency. Qualifications Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Ability to understand design specifications, can contribute to design planning, partitioning, and setup a feasible seed for convergence PD cycle. Extensive experience in physical design, including floorplanning, placement, clock tree synthesis, routing, and timing closure. Good understanding of EDA tools such as Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, Calibre, Red Hawk. Strong understanding of static timing analysis, power analysis, and signal integrity analysis. Excellent problem-solving skills and attention to detail. Ability to work effectively in a team environment and communicate clearly with cross-functional teams. Experience in mentoring and coaching junior engineers is a plus. Company Description About Renesas: Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world-leading MCUs, SoCs, analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Technical Manager role requiring 15+ years of experience of Digital design in Analog Mixed signal ICs for developing Power Management ICs as part of 2. 6B$ Power Business Unit at Renesas. Primary responsibilities include leading team which will fully own defining the microarchitecture to developing all Digital components of power management ICs, starting from System requirements. Due to the complex nature of Chips and significant Analog as well as Digital contents, collaboration with cross-functional teams to ensure successful integration of Digital and Analog components in ICs, is a must. The candidate will work on a wide range of exciting and cutting edge PMICs, including Linear and Switching DC-DC converters powering the next generation of most sought-after phones and handheld devices. This is an early-stage growth opportunity where in the candidate will get to learn, build and over time contribute and influence the charter for Renesas s massive Power product portfolio. Essential Functions: Manage the Digital Design team in terms of costs, methods and staffing to support device/silicon design requirements and to meet design deadlines as set by the program schedule. Mentor direct reports, giving appropriate guidance and support, and reviewing technical and behavioural performance regularly Must have experience of defining Dig-Ana boundary and Digital design scope for Power Management ICs/Analog intensive ICs Must have experience of defining the micro-architectures and sub-blocks for the ICs to ensure optimized Digital design, RTL design and Gate level netlist etc. Must be aware of Power Sensitive digital design and doing Power estimation for the Digital I/Ps Must be able to handle Clock Domain Crossing across multiple clock domains seamlessly and in a glitch free manner. Should be able to lead/collaborate for Logic Synthesis, Formal verification, Power estimation and STA. Should have experience of OTP, MTP, Efuse read/writes, controller design and data bus handling, Register read/write, Trimming of Analog parts/functions, DFT architecture and integration. Should be able to create Sequences (including Power UP/Down) and State Machines and Transitions to/from any state to another based on the IC requirements. Should be an expert of one or more Power Chip Communication I/Ps and protocols e. g. I2C, PMBUS, SVI3, SVID etc. Should be able to implement and analyse filters feedback loops in Digital, conversant with Z-domain analysis. Must have done multiple silicon debugs, root cause analysis of issues, design to silicon correlation etc. Should understand commonly used control loop architectures (Constant Freq, Constant ON/OFF Time, Current mode etc) and pros/limitations of each. Must be able to bring in innovative ideas to improve designs to meet challenging specifications and achieve better system performance. Should be able to setup Digital design flows and methodologies including checklists, reviews to ensure quality designs and take them all the way to Silicon success. Qualifications Bachelor s or master s degree in electrical engineering 15+ years in Digital Design and experience of working on Mixed Signal ICs, especially PMICs. Solid understanding and design experience of complex AMS designs. Chip design, Verification, Silicon validation, debugs, Qual support and taking ICs to production. Must be a technical leader, people manager team player, mentor and should strive towards fostering a highly creative and productive working environment Collaboration with Senior leadership to develop team objectives in accordance with wider company strategy. Ability to work with Senior Management to develop and work to budget. Cross cultural awareness and sensitivity. Results-oriented and able to deliver on-time under tight schedule pressure. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and adopt physical design friendly partitioning. Lead RTL design and integration of multi-subsystem SoCs , supporting complex architectures with multi-core, multi-power, and multi-reset domains . Demonstrate strong proficiency with front-end flows , including Lint, CDC, low-power (UPF) checks, synthesis, DFT , and Static Timing Analysis (STA) . Drive the development of robust Safety, Security, and Debug architectures for advanced SoCs with multiple interconnects. Design and integrate standard interface protocols such as AHB, AXI, CHI , and memory interfaces including ROM, RAM, Flash, LPDDR/DDR3/4 . Engage cross-functionally with DFT, physical design, verification, emulation, and validation teams to ensure first-time-right silicon and on-time project delivery. Support post-silicon debug, bring-up, and validation , working closely with lab and silicon validation teams. Continuously evaluate and adopt new design methodologies and best practices to improve productivity and shift-left the design cycle. Mentor junior engineers, review their work, and provide technical leadership and guidance across multiple design projects. Provide overall leadership and tracking of the team s goals. Contribute to the innovation quotient of the team via Desing Patents, Industry Standard Publications, AI-enabled design methodologies etc. Qualifications M. Tech/ B. Tech in Electrical Engineering or Computer Science with 12+ years of RTL design experience. Proven expertise in Verilog/SystemVerilog RTL design, integration, and microarchitecture. Strong understanding of SoC architecture, AMBA protocols (AXI, AHB, APB), clock/power domains, and memory subsystems. Experience with EDA tools for synthesis, lint, CDC, RDC, and timing analysis. Familiarity with UPF/low-power design, formal verification techniques, and static/dynamic checks. Excellent leadership, communication, and project management skills. Experience working with global cross-functional teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.

Job Title: Electrical Engineer(ECAD) Location: Pune, Maharashtra About Us: We are a global technology company driving energy innovation for a balanced planet. Together, we create amazing technology that unlocks access to energy for the benefit of all. Our inclusive culture is the key to our success. We collaborate with our internal community of colleagues, alumni, and our valued external partners to support each other and achieve our goals. We aim to raise the bar high. We look for people who are committed to innovation and success and act with integrity to become and be a part of one of the most diverse group of experts in our industry, anywhere around the globe. Global in outlook, local in practice – and with a united, shared passion for discovering solutions, we hire talented, driven people and support them to succeed, personally and professionally. About Schlumberger Technical Services India (STSI): SLB is committed to moving farther and faster in facilitating the world's energy needs today and forging the road ahead for the energy transition. STSI’s determination to transformation is the start of a journey towards a culture of continuous performance improvement. Over the years, STSI has also developed key expertise and support roles in higher scale work both in business vertical (within a PG) and horizontal (across PGs). To position itself as a critical support Centre for EMS capable of strong value addition while also being recognized as having their own excellence in key services, STSI has identified the need to attain a recognition as a Centre of Excellence (CoE). Job Responsibilities: The role of the Electrical Designer is: • Design Printed Circuit Board Assemblies (PCBAs) using toolsets Cadence Allegro and Altium. • Design PCBAs from schematic to Gerber generation, layer stack up and DFA, DFM, DFT analysis. • Design and edit PCBAs as per customer requirements and all applicable Schlumberger standards. • Make and maintain electrical drawings such as wiring harnesses and connectors using AutoCAD. • Prepare and update BOMs in the Schlumberger Product File Database. • Study and understand component datasheets to collect information for the circuit design. • Learn and follow all relevant standards specific to Schlumberger for PCB Design and library creation. • Update the Internal checklists and standards as per continuous feedback from the customers. • Effectively coordinate with interfacing personnel and/or groups, and provides timely updates to the team lead. Academic Qualifications: Diploma in Electrical or Electronics Engineering from a premier Diploma college in India. Experience:3-5 Years Skills:- Required • Experience in PCB design for multilayer boards. • Good knowledge of Cadence Allegro. • Sound Electrical or Electronics knowledge. • Attention to quality and detail is paramount. • Knowledge of English with good oral and written communication skills. Desired (Optional) • Knowledge of IPC standards (Institute for Interconnecting and Packaging Electronic Circuits). • Knowledge of EMI/EMC & Signal integrity issues for analog and digital boards including high frequency boards. • Understands the schematics and basic functionality of schematic flow. • Knowledge of CAD tools Altium, MentorGraphics and AutoCAD is preferred. • Knowledge of CAD tool ProE is a plus. This is an office-based position, with the expectation to come in four days a week. SLB as an employer: SLB is an equal employment opportunity employer. Qualified applicants are considered without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, or other characteristics protected by law. Show more Show less

Renesas is a global semiconductor company providing hardware and software solutions for a range of cutting-edge technologies including self-driving cars, robots, automated factory equipment, and smart home applications. We are a key supplier to the world’s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas is a global, multi-billion dollar, publicly traded company headquartered in Japan, and has subsidiaries in 20 countries worldwide. Renesas is a dynamic, multi-cultural technology company where employees learn, mentor, innovate and thrive. Renesas is extending our share in fast-growing data economy-related markets such as infrastructure and data center and strengthening our presence in the industrial/IOT and automotive segments. Our solutions drive products developed by major innovators around the world. Join us and build your future by being part of what’s next in electronics. Job Description Analog and Connectivity Business Unit (A&C) is looking for a Staff Product Engineer to join our team to drive the product development of state-of-the-art Sensor Signal Conditioning products. This is a unique and exciting opportunity to work with a cross-functional team to bring a product to volume production starting from product conception to production release. The job scope includes but is not limited to, development of the test plan to ensure datasheet specifications are met. Own the qualification plan and the execution to comply with various JEDEC/AEC quality standards. Own product quality assessment through reliability tests. Collaborate with multi-functional teams such as Design, Test, Applications and Failure Analysis teams during first silicon debug and to root cause field failures. Creation and maintenance of product BOM. Monitor production data to address yield and quality deficiencies using statistical analysis. KEY RESPONSIBILITIES • Full PE product lifecycle ownership from concept to end of life with a focus on ensuring the delivery of the highest quality products to our end customers • Definition of ATE test, qualification and manufacturing plans • Product release into manufacturing with adherence to stringent tier 1-customer requirements • Datasheet and automotive compliance reports • Real time customer support for design, product and quality related issues • Temperature/Voltage/Process characterization and production limit setting • Product new product introduction and yield ownership • Product BOM release and maintenance • Excursion management for both suppliers and customers • Use commercially available yield tools for yield improvement and monitoring, generate weekly reports and review with PE teams • KPI achievement in product related deliverables including NPI execution and velocity, product cost (Gross margin improvements), product quality performance and failure analysis cycle times • PAT, SYL, SBL, SPC limit and disposition optimizations to protect quality without excessive waste Qualifications • 12+ years experience in product engineering. A strong analog circuit background is a must. • Familiarity with ATE tester platforms (eg. Advantest 93K) • Knowledge of analog and mix-signal circuitry and the common building blocks, device physics, test methodology and DFT knowledge • Experience with common lab test equipment (DC power supply, oscilloscope, multi-meters etc). Bench characterization experience is a plus • Familiarity with JEDEC/AEC qualification standards and stress test conditions. Experience with qual hardware/software development would be preferred • Experience in yield management tools such as Spotfire, JMP. Apply statistical analysis to isolate the issue and make data-driven decisions • Ability to managing supplier excursions and customer escalations through problem solving • Knowledge of Semiconductor Failure Analysis is preferable • Strong verbal and written communication skills • A good team player. Effective in fast paced, dynamic work environment EDUCATION: • BS in Electrical/Electronic Engineering • MS in Electrical/Electronic Engineering is preferred Additional Information Renesas is an embedded semiconductor solution provider driven by its Purpose ‘ To Make Our Lives Easier .’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘ To Make Our Lives Easier .’ At Renesas, you can: Launch and advance your career in technical and business roles across four Product Groups and various corporate functions. You will have the opportunities to explore our hardware and software capabilities and try new things. Make a real impact by developing innovative products and solutions to meet our global customers' evolving needs and help make people’s lives easier, safe and secure. Maximize your performance and wellbeing in our flexible and inclusive work environment. Our people-first culture and global support system, including the remote work option and Employee Resource Groups, will help you excel from the first day. Are you ready to own your success and make your mark? Join Renesas. Let’s Shape the Future together. Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement. Show more Show less

Role: DFT Engineer Experience Required: 5-15 Years Location: Bangalore, Hyderabad, Noida, Ahmedabad, and Pune Will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests, and Pattern validation w/wo Timing, DFT mode timing analysis, and sign off. Be responsible for a comprehensive DFT plan Incumbent to work with DFT and cross-functional teams To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field ESSENTIAL SKILLS & EXPERIENCE Strong fundamentals on DFT and ASIC cycle. Sound expertise in Tcl, Perl, and Shell scripting. Technically sound & good team player Hands-on experience with DFT implementation using standard EDA and flow is a must. Interested candidates can send in their profile to bindu@logicalhiring.com or careers@logicalhiring.com References are welcome! For other open roles, please visit - www.logicalhiring.com

Change the world. Love your job. Texas Instruments is seeking Design Verification Engineer. In this role you will confirm the accuracy of designs for analog and mixed signal electronic parts, components, or integrated circuitry for analog and mixed signal electronic equipment and other hardware systems before pattern generation/mask development. The role will require working independently from the product development team who designed the devices to confirm adherence to known design rules, procedures, and best practices. You will be required to undertake complete ownership of IP/subsystem/SOC DV ownership right from spec definition till the post silicon verification and solving the customer issues on need basis. This includes: Active involvement with architecture team during the spec definition phase Verification strategy definition along with Verification plan to meet 100% spec to regression traceability along with signoff metrics SubSystem/SOC verification covering functional and firmware scenarios in RTL and GLS. DV Environment ownership: TB development/enhancements including checkers and coverage monitor definitions along with DV flow updates as per the project needs. Develop and maintain comprehensive verification environments using UVM Active collaboration with cross functional teams - Architecture, RTL, PD, DFT, Systems, Analog, FW and Application teams to ensure comprehensive verification of specific IP/Subsystem/SOC starting from spec definition till post silicon verification closure activities Mentor junior verification engineers and review their work. Establish verification methodologies and best practices QUALIFICATIONS Minimum requirements: Minimum of 3-4 years of experience in Digital IP Sub-system/SOC DV with a Bachelor or Master’s degree in EE/ECE/CS or related specializations Experience in one or many of the following: C based Digital DV, scripting (Python/Perl/Shell) knowledge, UVM/System Verilog, AMS/GLS/CPF/UPF based verification, Post silicon verification etc Preferred qualifications: Strong in digital design fundamentals, computer organization & architectures and bus protocols. A good understanding of analog functionality and exposure to analog IC design methods. Ability to solve problems using a systematic approach Excellent debugging skills with Verilog/VHDL designs Work experience on C based environment with ARM/DSP processor-based systems including power aware simulations is a plus. Experience in Motor control/ BLDC motor driver devices including commutation, sensorless control and feedback systems are an added advantage Experience with Cadence tools (Xcelium/vManager/Formal applications/safety simulator) or similar tools/DV flows Effective communication skills to interact seamlessly with all stakeholders Ability to quickly ramp on new systems and processes Ability to work in teams and collaborate effectively with people in different functions Ability to take the initiative and drive for results Strong time management skills that enable on-time project delivery ABOUT US Why TI? Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com. Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. JOB INFO Job Identification 25001296 Job Category Engineering - Product Dev Posting Date 06/05/2025, 01:11 PM Apply Before 06/06/2025, 01:30 PM Degree Level Bachelor's Degree Locations BANG Bagmane Tech Park, Bangalore, 560093, IN ECL/GTC Required Yes

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Preferred Qualifications Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3+ years of Hardware Engineering or related work experience. 2+ years of experience with circuit design (e.g., digital, analog, RF). 2+ years of experience utilizing schematic capture and circuit simulation software. 2+ years of experience with hardware design and measurement instruments such as oscilloscopes, spectrum analyzers, RF tools, etc. Principal Duties And Responsibilities Applies Hardware knowledge and experience to plan, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Integrates features and functionality into hardware designs in line with proposals or roadmaps. Conducts simulations and analyses of designs as well as implements designs with the best power, performance, and area. Collaborates with teams (e.g., design, verification, validation, software and systems engineering, architecture development teams, etc.) to implement new requirements and incorporate the latest test solutions in the production program to improve the yield, test time, and quality. Evaluates, characterizes, and develops the manufacturing solutions for leading edge products in processes and bring-up product to meet customer expectations and schedules. Evaluates reliability of materials, properties, and techniques and brings innovation, automation, and optimization to maximize productivity. Assists in the assessment of complex design features to identify potential flaws, compatibility issues, and/or compliance issues. Writes detailed technical documentation for Hardware projects. Level Of Responsibility Works independently with minimal supervision. Decision-making may affect work beyond immediate work group. Requires verbal and written communication skills to convey information. May require basic negotiation, influence, tact, etc. Tasks require multiple steps which can be performed in various orders; some planning, problem-solving, and prioritization must occur to complete the tasks effectively. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3065645 Show more Show less

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined execution. As a Graphics physical design engineer, you will innovate, develop, and implement GPU cores using state-of-the-art tools and technologies. You will be part of a team responsible for the complete Physical Design Flow and deliveries of complex, high-speed, low power GPU COREs. Tasks also involve the development and enablement of low power implementation methods, customized P&R to achieve area reduction and performance goals. Additional responsibilities in this role involves good understanding of functional, test (DFT) mode constraints for place and route, floorplanning, power planning, IR drop analysis, placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and closure, RC extraction, signal integrity, cross talk noise and delay analysis, debugging timing violations for multi-mode and multi-corner designs, implementing timing fixes, rolling in functional ECOs, debugging and fixing violations and formal verification. The individual also should have deep knowledge on scripting and software languages including PERL/TCL, Linux/Unix shell and C. This individual will design, verify and delivers complex Physical Design solutions from netlist and timing constraints to the final product. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum Qualifications Bachelor's/Master’s degree in Electrical/Electronic Engineering from reputed institution 12+ years of experience in Physical Design/Implementation Minimum Requirements: Physical Implementation activities for high performance GPU Core, which includes Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure and power optimization. Should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Strong expertise in timing convergence of high frequency data-path intensive Cores and advanced STA concepts Well versed with the Block level PnR convergence with Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in latest technology nodes Good understanding of clocking architecture. Should be able work in close collaboration with design, DFT and PNR teams and resolve issues wrt constraints validation, verification, STA, Physical design, etc. Well versed with Tcl/Perl Scripting Experience of working as part of a larger team and working towards project milestones and deadlines; Handle technical deliverables with a small team of engineers. Strong problem-solving skills and good communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers. 3071473 Show more Show less

As a DFT Technical Lead , you will be responsible for overseeing the DFT implementation and verification activities for complex SoCs/ASICs, collaborating with cross-functional teams and architects. Your role will involve leading teams technically, providing training and mentoring, and interfacing with customers. Under general supervision, you will engage in engineering work, applied research, and the development/design of new integrated chips, including architectural design, logic design, circuit design, physical design, verification, fabrication, and packaging. Roles & Responsibilities: Hands-on expertise in Full Chip SCAN , Compression , MBIST , ATPG , and other DFT-related skills. Over 10 years of experience, with strong hands-on involvement in full chip DFT design , implementation , vector generation/verification , JTAG , boundary scan , and simulation . Proficient with Scan , Compression , ATPG , and simulation tools such as Mentor , Synopsys , or Cadence . Knowledge of Logic BIST is a plus. Proven track record of participation in successful tape-outs of SoC/ASIC chips at 14nm or below, consistently meeting test targets. Strong understanding of front-end SoC/ASIC design and implementation, including Synthesis and Static Timing Analysis (STA) . Experience in developing and automating flows and scripts in Perl/Tcl to enhance DFT methodologies and processes. Excellent problem-solving , debugging , and proactive approach to challenges. Demonstrated leadership in mentoring/training junior teams , managing projects, and taking on technical leadership roles. Strong customer interaction , communication , and teamwork skills.

Quality Test Engineer – Job Criteria Hindustan Amusement Machines Job Purpose To ensure all amusement rides are manufactured, assembled, and tested according to safety, durability, and design specifications, and comply with national and international standards (BIS/ASTM/EN). This role is responsible for checking structural integrity, painting & FRP quality, safety systems, and ride performance before dispatch. Key Responsibilities Inspect raw materials, fabricated parts, FRP components, and mechanical/electrical assemblies. Conduct in-process and final quality checks as per approved checklists. Perform load, vibration, noise, endurance, and safety system testing. Measure paint thickness, FRP quality, and alignment tolerances. Document test results, prepare QC reports, and tag approved items. Coordinate with the design, engineering, and safety teams for continuous improvement. Ensure compliance of components with internal standards and applicable safety codes. Maintain calibration and quality testing tools and equipment. Technical Skills Required Ability to read technical drawings and mechanical diagrams. Proficiency with measuring tools (vernier caliper, micrometer, DFT meter, vibration meter). Knowledge of welding quality inspection and NDT methods. Experience with FRP and mechanical safety system checks. Understanding of electrical and mechanical failures in inspection. Familiarity with BIS, ASTM, and EN ride safety standards. Experience Minimum 2 years in quality control/testing in mechanical or amusement ride manufacturing. Hands-on experience in ride testing or rotating equipment QC preferred. Soft Skills Detail-oriented with excellent documentation skills. Strong problem-solving and root cause analysis abilities. Ability to work independently and under pressure.

Radiant Semiconductors is a leading Semiconductor Design and Services Company with a strong presence across India and the USA. Backed by 200+ skilled engineers, over 7 years of industry relevant experience, were specialised in Design Verification, Design For Test (DFT), PD and Analog Design. We deliver tailored solutions through flexible engagement models, serving top Semiconductor Companies worldwide by our leadership team with 18+ years of expertise in product development. Role: Junior DFT Engineer Location : Bengaluru, Candidate should be flexible to work PAN India Eligibility Criteria Qualification : B.E/ B.Tech, M.Tech/M.E (Will get preference) Stream : Electronics Engineering or Related Fields Post Graduation Year : 2024 or Prior (Up to 2020) Academic Requirement : Minimum 65% throughout academics Background : Strong foundation in VLSI Design, Digital Electronics, Scan & DFT Fundamentals What we offer Competitive Salary Package aligned with Industry Standards Comprehensive Family Health Insurance Coverage Opportunity to work on high-impact semiconductor projects with top-tier global clients Professional training with the focus on industry standard EDA tools Opportunity to continuous learning and mentorship support from Industry experts Employee Recognition: Get acknowledged and rewarded for innovation, performance, and dedication Selection Process Online Registration Written Test (Shortlisted Candidates) Technical Interview (Selected Candidates) HR Discussion & Final Offer Important Dates Last Date to Application- 14th June Written test (Shortlisted Candidate )- 27th June Technical Interview (Selected Candidates)- 28th June HR Discussion & Final Offer- 28th June Click on the link to Apply now and become a part of Radiants Dynamic DFT team: https://forms.gle/ZCNcACE9Eigx5iuq6

Skill: RTL design skills using verilog, SV, PCIe, CXL, ARM subsystem, SATA, DDRx etc, synthesis and timing closure , low power design flow, partition and upf creation. unit level testing and DFT concepts