615 Design Verification Jobs - Page 25

Role Purpose The purpose of the role is overall development of the target Architecture through defining the technology roadmap for own business/ domain. Recognized as the subject matter expert for a specific domain and provides expert advice & guidance to different business stakeholders Do Develop architectural application for the new deals/ major change requests in existing deals Creates enterprise wide business/ domain architecture deliverables (enabling, diagnostic and actionable) focused on the target audience and its issues and opportunities Look for opportunities to use high-level business and operating models (business capability and value chain), combined with or relating to business, people, information, technology and solutions. Contributes to the Target Architecture, by developing and maintaining the technology roadmap for area of expertise and ensuring that roadmap remains aligned to the Business Strategy Recognizing innovative use of technology for increasing performance measures Works with other IS and business stakeholders to drive the development and adoption of the target architecture for own domain Establish domain specific standards, near/mid-term strategy, and roadmaps, in adherence to, and in support of Enterprise standards, strategy, and roadmaps. Guide a solution from concept to delivery - envision and create solutions that meet requirements Prove the feasibility of a design; and can ultimately be implemented and supported in the Production environment Oversee product/ platform engineering, protocol map development, virtualization as per the business solution requirements Apply architectural and engineering concepts to design a solution that meets operational requirements, such as scalability, maintainability, security, reliability, extensibility, flexibility, availability, and manageability. Participate and lead research and development efforts (proof of concept, prototypes), as subject matter experts, when introducing new technologies, in conjunction with team and Product Owners Partners with IT and line of business functional groups to communicate and clarify business needs, contributes to the development of long-range system plans, and ensures that IT products, services and processes are aligned with line of business needs. Define high-level migration plans to address the gaps between the current and future state, typically in sync with the IT budgeting or other capital planning processes Provides technology consulting to solution architects, junior staff members, and others who are using or modifying multiple domain technologies within a solution, insuring the technology operates coherently to meet overall needs Interaction with EA, OEMs, Technical leads for defining business solutions Depending on the clients need with particular standards and technology stacks create complete RFPs Clearly articulate and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Provide solution of RFPs received from clients and ensure overall design assurance Develop a direction to manage the portfolio of all the business/ domain requirements including systems, shared infrastructure services in order to better match business outcome objectives Analyse technology environment, enterprise specifics, client requirements to set a collaboration solution for the big/small data Provide technical leadership to the implementation of custom solutions through thoughtful use of modern technology Define and understand current issues and problems and identify improvements Evaluate and recommend solutions to integrate with overall technology ecosystem keeping consistency throughout Understand the root cause problem in integrating business and product units Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Collaborating with sales and delivery leadership teams to identify future needs and requirements Tracks industry and application trends and relates these to planning current and future IT needs Understanding enterprise requirements and provide solutions for technical ecosystem Creating Intellectual Property in forms of services, patterns, models and organizational approaches. Bring knowledge of automation in application by embracing Agile and dev-ops principles to reduce manual part Responsible for successfully applying the technology in their domain to solve business problems in a supportable, cost effective, way Analyze the current technology environment to detect critical deficiencies and recommend solutions for improvement. In addition, analyze the technology industry and market trends to determine their potential impact on the enterprise as well as on the enterprise technology architecture Develop a direction to manage the portfolio of to-be-solutions including systems, shared infrastructure services, applications in order to better match business outcome objectives Provide platform to create standardize tools, uniform design and techniques are maintained to reduce costs of maintenance Seamless integration and advising of new and existing systems to eliminate potential problems and maintain data structure and bring value in terms of development Serve as technical owner and point of contact for domain specific solutions and provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Enable Delivery Teams by providing optimal delivery solutions/ frameworks Build and maintain relationships with executives, technical leaders, product owners, peer architects and other stakeholders to become a trusted advisor Collaborate with enterprise architect for translating business strategy to execution Develops and establishes relevant technical, business process and overall support metrics (KPI/SLA) to drive results Bring value in terms of quality in development activities by leveraging cloud based and scalable infrastructure Identify technical, process, structural risks and prepare a risk mitigation plan for all the projects Ensure quality assurance of all the architecture or design decisions and provides technical mitigation support to the delivery teams Recommend tools for reuse, automation for improved productivity and reduced cycle times Leads the development and maintenance of enterprise framework and related artefacts Develops trust and builds effective working relationships through respectful, collaborative engagement across individual product teams Provide architectural oversight of projects; ensure requirements are in alignment with business strategies and business architecture roadmap/framework. Ensure solutions developed across organization are aligned to enterprise architecture standards and principles, leverage common solutions and services, and meet financial targets (cost and benefits). Negotiate, manage and coordinate with the client teams to ensure all requirements are met and create an impact of solution proposed Demonstrate thought leadership with strong technical capability in front of the client to win the confidence and act as a trusted advisor Mandatory Skills: VLSI Physical Place and Route. Experience: 8-10 Years.

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the worlds mostinnovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as theyprovide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days arethe same.

Understand the design specification , PowerOn Specification, and Power management specification. Understand boot firmware and reset flow. And/or Power management flow. Develop skills in IBM BIST verification tools and apply them successfully Develop the verification environment and test bench Debug fails using waveform, trace tools and debug RTL code Work with Design team in resolving/debugging logic design issues and responsible for deliveries Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 3-6years of experience in Design Verification - demonstrated execution experience of verification of logic blocks Strong in SoC verification Chip reset sequence and initialization, and/or Power management. Knowledge of verification (any) methodology, Knowledge of HDLs (Verilog, VHDL) Good programming skills in C/C++, Python/Perl Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Hardware debug skills backed by relevant experience on projects Exposure in developing testbench environment, write complex test scenarios Good communication skills and be able to work effectively in a global team environment Drive verification coverage closure Preferred technical and professional experience Knowledge of Chip-Initialisation , SCAN , BIST is a plus Scripting Expertise backed up relevant experience in the same Writing Verification test plans Functional and code coverage analysis and debug

Role & responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Preferred candidate profile Bachelors/ Masters degree or higher in EEE/ECE 4+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platforms: UVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Role & responsibilities Job Summary: We are seeking a highly skilled Design Verification Engineer (DV) to join our growing team and play a vital role in ensuring the quality and functionality of our advanced ASICs and SoCs. This position requires a strong foundation in verification methodologies and the ability to handle complex verification tasks. You will be instrumental in developing robust verification plans and environments to guarantee the success of our next-generation integrated circuits. Responsibilities: Develop and implement comprehensive verification plans utilizing industry-leading methodologies (UVM, Formal Verification) Design and create high-quality verification environments (testbenches) to achieve exceptional code coverage Utilize advanced verification tools (simulators, formal verification tools) to thoroughly verify RTL functionality Debug and analyze verification failures with a keen eye to identify and resolve the root cause of design issues Collaborate effectively with RTL design engineers to ensure efficient bug resolution and verification plan adherence Lead and mentor junior DV engineers within the team, fostering a collaborative and knowledge-sharing environment Participate in code reviews and champion best practices for verification code quality Stay current with the latest advancements in verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 7+ years of solid experience in Design Verification for ASICs or SoCs In-depth knowledge of digital design principles (combinational logic, sequential logic, finite state machines) Proven ability to develop, debug, and optimize complex verification environments Expertise in Verilog or VHDL with a strong understanding of verification methodologies (UVM, Formal) Extensive experience with simulation tools (ModelSim, Cadence Incisive, Synopsys VCS) and scripting languages (Python, Perl) Experience with formal verification tools and techniques is a plus Excellent analytical and problem-solving skills with a meticulous attention to detail Strong communication, collaboration, and leadership skills to effectively contribute and guide the team Benefits: Competitive salary and benefits package commensurate with experience Opportunity to work on leading-edge technologies and projects with a high impact Collaborative and dynamic work environment that fosters continuous learning Potential for professional development and career advancement

We're Hiring: Design Verification Trained Freshers (M.Tech/M.E) | AI Product Team | Siplont Technologies Are you a Masters graduate (M.Tech/M.E) with training in Design Verification and a passion to work on cutting-edge AI-driven semiconductor products ? Join Siplont Technologies , where were building the future of intelligent chip design! What We're Looking For Freshers trained in Design Verification (SV/UVM) Strong understanding of Digital Design, Verilog, SystemVerilog, UVM Passion for AI-based hardware development Excellent problem-solving and debugging skills Commitment to long-term career growth with us Why You Should Join Us Be part of a next-gen AI-focused product team Learn directly under an industry stalwart with 30+ years of experience in Design Verification Our technical leader has: Worked with top semiconductor giants Led 20+ successful chip tape-outs Spearheaded multiple global verification teams Build your career where innovation meets mentorship Key Skills You'll Work On SystemVerilog , UVM , Verilog RTL Verification , Testbench Architecture Assertions , Functional Coverage Exposure to AI, ML-integrated chip design Debug using Simulators (VCS/Questa) and Waveform tools At Siplont, we don’t just offer jobs — we offer career journeys . If you’re passionate about silicon and serious about staying long-term to grow into a core contributor to AI-enabled chip design , this is your chance . Preferred candidate profile

Overview UVM Based verificaton at SOC level Responsibilities As a Senior Design Verification Engineer, you will define verification methodology and implement the corresponding verification plan for the SoC. You will participate in the design verification and bring-up of the SoC by writing relevant tests, coverages, assertions, developing automation infrastructure, debugging code, test benches, test harnesses, while interacting with the extended team. You will work closely with multi-disciplinary groups including Product Design, Audio Technology, Computer Vision, Hardware and Software Engineering, to create a multi-model SoC that enables development of world-class hardware devices. Requirements Bachelor’s/ Master’s degree or higher in EEE/ECE 5+ years or more of practical semiconductor design verification including System Verilog, UVM, GLS, assertions and coverage driven verification. Experience using multiple verification platformsUVM test bench, emulator, software environments Experience with industry standard IO interfaces like AMBA, CXL, USB, MIPI, PCIE, DDR etc. Experience defining verification methodologies Experience with test plan development, test bench infrastructure, developing tests and verifying the design Experience with writing directed/constrained-random tests Experience identifying bugs in architecture, functionality, and performance with strong overall debug skills Experience verifying at multiple levels of logic from SoCs to full system testing Experience with industry standard tools and scripting languages (Python) for automation Experience in SOC Architecture is a strong plus Experience with ARM/RISCV Experience with debugging system level issues Experience with industry standard IO interfaces like AMBA, USB, MIPI, PCIE etc. Experience with formal verification techniques Excellent verbal and written communication skills

Essential Duties and Responsibilities: Leads the evaluation and development of Disposables by designing and conducting research programs; applying principles of mechanics, thermodynamics, hydraulics, heat transfer, and materials. Ensures successful integration of mechanical design entities with electrical and consumable components. Leads the troubleshooting and problem solving efforts related to mechanical aspects of the design and interfaces with other design constituents. Ensures Systems that are optimized for production, reliability, regulatory compliance and cost. Responsible for development and documentation of mechanical systems architectures. Provides leadership to effectively transition products to manufacturing and ensure robust products and manufacturing processes. Performs in-depth mechanical engineering analysis and calculations. Manages integration of deliverables from sub-system design teams and external partners. Resolves competing constraints between interrelated functions (engineering, purchasing, manufacturing, regulatory, marketing, etc.) required to deliver the product to market. Defines protocols and conduct the necessary testing required to validate the safety and effectiveness of the design(s). Develop test plans, test protocols, and test reports for product integration testing, also develops the infra required for the testings. Develops, modifies, and approves mechanical documentation, specifications and drawings. Coach and mentor junior engineers and lab technicians to execute project deliverables. Ensure compliance with all local state federal and Baxter safety regulations policies and procedures actively build on uh personal skills advertise and competencies ensure that technical lessons are reviewed learned and disseminated create and document novel test methodologies and provide feedback and recommendations for product design changes Define plan and lead activities for test method and measurement system development and validation fixture design and testing optimization in support of design verification lead end to end responsibilities of all platform level testing and lab management have product design ownership encompassing creation and execution of verification protocols summarize the results enable formal design reviews and own the verification portion of the design history file demonstrate proficiency in sporting design variants through relevant statistical measures interpret and analyze design verification data with respect to product performance and operational stability in manufacturing plants application of engineering first principles and advanced engineering methods to gain deep understanding of the underlying technical issues and to propose and implement robust solution collaborate with the design development system engineering and cross functional team to ensure product requirements are verifiable and measurable ensure deliverables are reliable across the design space is adequately pressure tested to satisfy user regulatory and business requirements understand system and subsystem design sensitivity and identify the address earlier potential design integration and transfer risks create and document normal test methodologies and provide feedback and recommendations for product design team changes

1. M. Tech / B. Tech in the field of VLSI/Electronics engineering. 2. Proficiency in UVM/SV and C/C++ based functional verification. 3. Experience in UPF based low power design verification. 4. Automation skills in PERL and/or TCL and/or Shell. 5. Team player, with good problem solving and communication skills. Job Description: 1. Drive functional verification at IP/SoC level using UVM/SV test bench. 2. Work closely with design team to define comprehensive feature test plans. 3. Perform functional and code coverage for logic verification sign-off. 4. Must have worked on ARM/RISC-V CPU based designs. 5. Must have performed gate level sim at SoC level. 6. Pre and Post-silicon debug/verification experience will be a plus. Interpersonal Skills: 1. Energetic, self-motivated 2. Pro-active, oriented on execution 3. Attentive to details and quality 4. Team player 5. Good communications and reporting skills

1. M. Tech / B. Tech in the field of VLSI/Electronics engineering. 2. Proficiency in UVM/SV and C/C++ based functional verification. 3. Experience in UPF based low power design verification. 4. Automation skills in PERL and/or TCL and/or Shell. 5. Team player, with good problem solving and communication skills. Job Description: 1. Drive functional verification at IP/SoC level using UVM/SV test bench. 2. Work closely with design team to define comprehensive feature test plans. 3. Perform functional and code coverage for logic verification sign-off. 4. Must have worked on ARM/RISC-V CPU based designs. 5. Must have performed gate level sim at SoC level. 6. Pre and Post-silicon debug/verification experience will be a plus. Interpersonal Skills: 1. Energetic, self-motivated 2. Pro-active, oriented on execution 3. Attentive to details and quality 4. Team player 5. Good communications and reporting skills

Design analog and mixed-signal system blocks of DC-DC converter power stages and POL ICs Job Description In your new role you will: Design analog and mixed-signal system blocks of DC-DC converter power stages and POL ICs including POR, Bandgap, LDO, Oscillators, drivers,current sensing, test modes etc. Assist in defining the requirements for analog and mixed-signal blocks , aligning them with IP Module architecture, and ensuringcompliance with requirements through documentation. Provide essential support to physical design engineers, post-silicon validation, production testing, and other critical activities extending beyond the design phase. Communicates with cross functional/inter disciplinary team as needed to make sure the team is aware of the assumptions and progress made by the design team. Balance innovation with execution: to ensure that the projects aredelivered in a timely manner. Your Profile You are best equipped for this task if you have: A Master s degree in Electrical/Electronic Engineering, microelectronic, or comparable with focus on electronics. 5+ years of experience in analog IC design with proven track record of delivering high performance DC-DC converter Power IC solutions. Good Analytical skills and very good understanding of Analog Designlike biasing, small signal and large signal analysis. Proficiency with industry-standard design verification and simulation tools. Understanding of process technologies and device behavior which are important for high voltage, high power operation and reliability issues.

Position: Design Verification Engineer (IS90FF RM 3489) Responsibilities & Required Experience: Define test plan/design, test cases, and develop test scripts for RPG product validation. Collaborate with architecture and design teams to define validation flows. Experience in PHY verification and high-speed blocks with IOs. Run and debug gate-level simulations. Familiarity with APB/AXI protocols and verification methodologies. Job Category: Others Job Type: Full Time Job Location: Bangalore Experience: 9+ YEARS Notice period: 0-15 days

Principal Physical Design Verification / ESD Engineer in Bangalore, KA, India Principal Physical Design Verification / ESD Engineer Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply! About the role: As a member of the PDV Team, youll own chip-level physical design verification, physical verification flow automation, physical design reviews and ESD coverage. What you ll achieve: Partition and chip-level level ownership of physical design verification (PDV), and physical design reviews Execute and debug final verification flows in preparation for gds tape out delivery on FinFet designs (DRC, LVS,DFM, Antenna, Density Fill Routines, XOR, etc.) ESD Verification and Sign-off at partition and chip level Design enhancements and DFM techniques Package level physical verification LVS / DRC check coding Support all PDV sign-off scripts at partition and at chip-level Work with multiple sites in a team environment, particularly with offices in the US, India, and Vietnam About you: M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience Background with FinFets and multi exposure metallization is required Familiarity with Cadence and Siemens tools is required Shell, Skill, Calibre and other programming knowledge Familiarity with Physical Verification flow automation Familiarity with ESD coverage techniques and verifications flows (Calibre PERC, Ansys Pathfinder) Familiarity with DFM techniques for yield enhancements Familiar in identifying and addressing issues often found at the chip level, some of which include: Density Latch up triggered failures Abutment conflicts Data integrity Short isolation and open/swapped nets What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

Principal Physical Design Verification / ESD Engineer in Pune, MH, India Principal Physical Design Verification / ESD Engineer Description Invent the future with us. Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow. Join us at Ampere and work alongside a passionate and growing team we d love to have you apply! About the role: As a member of the PDV Team, youll own chip-level physical design verification, physical verification flow automation, physical design reviews and ESD coverage. What you ll achieve: Partition and chip-level level ownership of physical design verification (PDV), and physical design reviews Execute and debug final verification flows in preparation for gds tape out delivery on FinFet designs (DRC, LVS,DFM, Antenna, Density Fill Routines, XOR, etc.) ESD Verification and Sign-off at partition and chip level Design enhancements and DFM techniques Package level physical verification LVS / DRC check coding Support all PDV sign-off scripts at partition and at chip-level Work with multiple sites in a team environment, particularly with offices in the US, India, and Vietnam About you: M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience Background with FinFets and multi exposure metallization is required Familiarity with Cadence and Siemens tools is required Shell, Skill, Calibre and other programming knowledge Familiarity with Physical Verification flow automation Familiarity with ESD coverage techniques and verifications flows (Calibre PERC, Ansys Pathfinder) Familiarity with DFM techniques for yield enhancements Familiar in identifying and addressing issues often found at the chip level, some of which include: Density Latch up triggered failures Abutment conflicts Data integrity Short isolation and open/swapped nets What we ll offer: At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus (i.e., variable pay tied to internal company goals), long-term incentive, and comprehensive benefits. Benefits highlights include: Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work. Generous paid time off policy so that you can embrace a healthy work-life balance Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day. And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process. Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.