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Allegis Group
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Design Verification

Design Verification

Allegis Group

2 - 7 years

12 - 22 Lacs

Hyderabad

Posted:1 month ago| Platform:

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Skills Required

Design Verification Verilog PCI UVM Axi Sv Pci / Pcie OVM PCIE System Verilog Pci Express Ip Verification

Work Mode

Work from Office

Job Type

Full Time

Job Description

Role :

Location:

Qualification:

Experience :

Work Mode :

Job Description

Strong Familiarity with
System Verilog and OVM/UVM Verification Methodology.
Knowledge of system-level architecture including buses like AXI/AHB/APB/ACE5
Excellent
waveform debug skills using front end industry standard design tools like VCS, NCSIM, Verdi, Model Sim
.
Proficiency in developing the TB environment
Good Knowledge on writing coverage and assertions
Good knowledge in scripting(Perl/Tcl/Python) and automation of verification flows/process
Knowledge on the PCIE is required.
Knowledge of mipi, video Ips like ISP/Encoder/Decoder would be useful.

Functional Skills

Ability to work with cross-functional teams

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