Design for Test Engineer

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Hi Connections,

We are hiring....

Job Title: Design for Test (DFT) Engineer

Location: Hyderabad / Bangalore

Department: Semiconductor / VLSI Design & Test

Employment Type: Full-Time

Experience: 3+years

Job Summary

We are seeking an experienced DFT Engineer to design, implement, and verify test architectures for complex SoC/ASIC designs. The role involves integrating scan chains, built-in self-test (BIST), boundary scan, and other testability features to ensure high-quality and manufacturable silicon. You will work closely with RTL, physical design, and verification teams to ensure robust test coverage and smooth silicon bring-up.

Key Responsibilities

● Define and implement DFT architecture for SoC/ASIC designs.

● Integrate scan chains, MBIST, LBIST, and boundary scan (IEEE 1149.1 JTAG).

● Develop DFT insertion flows using industry-standard tools (Synopsys, Mentor Tessent, Cadence).

● Perform ATPG (Automatic Test Pattern Generation) to achieve target fault coverage.

● Collaborate with physical design teams to meet timing, area, and power constraints for DFT logic.

● Debug and resolve test-related issues during pre-silicon verification and post-silicon bring-up.

● Generate and validate test patterns for manufacturing test environments.

● Work with foundry/test houses to ensure smooth transition to high-volume production testing.

● Maintain documentation for DFT architecture, patterns, and procedures.

Required Skills & Qualifications

● Bachelor’s/Master’s degree in Electrical/Electronics/Computer Engineering.

● 3+ years of experience in DFT for ASIC/SoC designs.

● Strong knowledge of scan-based testing, ATPG, MBIST, LBIST, and boundary scan.

● Proficiency with EDA tools: Synopsys DFT Compiler, Mentor Tessent, Cadence Modus.

● Understanding of fault models (stuck-at, transition delay, path delay).

● Familiarity with low-power DFT methodologies (UPF/CPF).

● Good understanding of STA and its impact on test logic.

Preferred Qualifications

● Experience with high-speed I/O test strategies.

● Knowledge of JTAG boundary scan for board-level testing.

● Exposure to post-silicon validation and ATE (Automatic Test Equipment) environments.

● Experience with scripting (TCL, Python, Perl) for flow automation.

● Understanding of security-related DFT techniques for preventing hardware attacks.

Interested guys, kindly share your updated profile to pavani@sandvcapitals.com or reach us on 7995292089.

Thank you.

Job Type: Full-time

Pay: ₹1,000,000.00 - ₹1,500,000.00 per year

Experience:

• SoC: 3 years (Required)

Work Location: In person

Speak with the employer
+91 7995292089