Design Engineer I

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
  

Job Responsibilities

Responsibilities

• Develop test plans, tests , and verification infrastructure for complex IP’s/sub-system/SOC’s.
• Create verification environment using UVM methodology.
• Create reusable bus functional models, monitors, checkers, and scoreboards.
• Drive functional coverage driven verification closure.
• Work with architects, designers and DFT teams.
  

Skill Sets

• BTech/ MTech with 2-7 years of experience. Or Equivalent
• IP/Sub-system/SOC level verification experience.
• Expert in developing test bench/test case using System Verilog & UVM.
• Experience with code coverage, functional coverage & assertions is desired.
• Experience in the following areas:
• UCIE or PCIE
• Bus protocols (AXI/AHB/APB)
• Exposure to industry standard verification tools for simulation and debug
• Good debugging and problem-solving skills.
• Good communication skills
  

We’re doing work that matters. Help us solve what others can’t.