Design Engineer 2

Cadence

1 - 3 years

0 Lacs

pune maharashtra india

Posted:5 days ago| Platform:

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Skills Required

design cadence integration verification checks engineering verilog logic debugging controller documentation synthesis timing constraints analysis development emulation communication

Work Mode

On-site

Job Type

Full Time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The selected candidate will be responsible for RTL Design & Integration, collaborating closely with Architects and the Verification team.
Ensuring the required design quality through Lint and CDC checks and following release checklists.

Skillset/Requirements

BTech/ MTech in Engineering with 1-3 years of practical experience in RTL Design.
Profound understanding of the end-to-end Digital design flow.
Proficiency in Verilog/System-Verilog RTL logic design, debugging, and providing functional verification support.
Knowledge of managing multiple asynchronous clock domains and their crossings.
Familiarity with Lint checks and error resolution.
Hands-on experience with APB and AXI protocols.
Experience in micro-controller based designs and associated logic is advantageous.
Additional experience in Digital microarchitecture definition and documentation is a plus.
Exposure to synthesis timing constraints, static timing analysis, and constraint development is beneficial.
Familiarity with FPGA and/or emulation platforms is advantageous.
Strong communication skills, self-motivation, and organizational abilities are essential.

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