561 Asic Jobs - Page 18

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: Proficient in IP level ASIC verification Proficient in debugging firmware and RTL code using simulation tools Proficient in using UVM testbenches and working in Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Developing UVM based verification frameworks and testbenches, processes and flows Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the UVM concepts and SystemVerilog language Good working knowledge of SystemC and TLM with some related experience . Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to video codec system or other multimedia solutions . Expertise in Verilog, System Verilog, and Object-Oriented Programming Experience with UVM or similar Verification Methodology Requires strong Computer Architecture knowledge Comfortable in python / perl and editing / maintaining scripts Experience working in a team environment through the ASIC Project lifecycle from Planning to Tape Out Experience with DRAM controllers, DDR Phys or DRAM Interface Protocols is a plus. Strong communication skills and the ability to work independently as well as in a cross-site team environmen ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

SystemC requirement with 2-10 years of experience in our team and looking for profiles Note, please apply only with the following skills SystemC experience (preferred). Firmware experience with decent C++ expertise and SoC knowledge. ESSENTIAL DUTIES AND RESPONSIBILITIES: Development of C++/SystemC models for complex ASIC IPs, SOCs and Flash Memories. Create System Level Tests and/or Standalone Unit Tests and verify the models. Keen on schedule and quality of the deliverables. Timely support to the stakeholders enabling software bring-up. QUALIFICATIONS: B.E/B.Tech or M.E/M.Tech in Electronics, Computer Science or related streams. 2 - 10 years of relevant experience. REQUIRED SKILLS: Proficient in SystemC/TLM, C++, C. Hands-on experience in development of functional/approximately timed models using SystemC/C++. Hands-on experience in embedded system test development using C. Proven ability to troubleshoot and analyze complex problems. Excellent grasp of Digital Fundamentals. Ability to multi-task and meet deadlines. Should be a Fast learner and a team player. Good written and verbal communication skills. PREFERRED SKILLS: Understanding of Computer Architecture, SoC, CPU (ARC/ARM/RISC-V/etc,), Bus Architectures, RTOS. Exposure to scripting languages like Python. Experience with Visual Studio programming environment Working Knowledge of Interface Protocols like PCIe, AXI, USB, UFS, NVMe, SD

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! We are seeking an innovative Senior Physical Design & Timing Methodology Engineer to help drive sign-off strategies for the worlds leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, insightful analysis, and automation. This work will influence the entire next generation computing landscape through critical contributions across NVIDIAs many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence. We have crafted a team of highly motivated people whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. If you are fascinated by the immense scale of precision, craftsmanship, and artistry required to make billions of transistors function on every die at technology nodes as deep as 3 nm, this is an ideal role. What you will be doing: Collaborate with technology leads, circuits and systems teams, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance. Understand corner case timing sign-off risks in the latest 3nm and deeper technology nodes. Develop strategies to mitigate and margin for them. Develop tools and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer. Extensively work with our ASIC Physical Design team to help develop methodologies, flows, and tools across a wide spectrum of domains - STA, constraints, floorplanning, timing and power optimization. Develop world class work flow solutions to aid analysis and improve flow efficiency. What we need to see: Master s Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent work experience 4+ years of relevant work experience Deep understanding of backend design process, especially advanced STA. In depth understanding of PT and/or Tempus Expertise in coding -- TCL, Perl, Python. C++ is a plus! Strong communication and interpersonal skills Ways to stand out from the crowd: Expertise in developing advanced STA flows #LI-Hybrid

In your new role you will: Defining, designing, and implementing very complex logic blocks. Performing architecture analysis and feasibility for these complex blocks. Working with the SoC lead for full chip implementation from launch to production . Performing RTL design, synthesis and DFT strategy, clocking strategy, validation and verification support. Utilizing industry standards and proprietary tools and methodologies for design, chip integration and design for test. Supporting cross functional teams, including product and test engineering, chip integration, circuit design, verification and validation, in taking SoC into production. Participating in customer design reviews Participate in detailed planning and monitoring to deliver on time milestones. Mentor and develop junior engineers.

Candidate will be responsible for building/maintaining highly configurable and reusable IO Subsystems (Note: An IO Subsystem is a logic IP that processes the IO Pads/IO Ring information and required logic to allow multiple on-chip peripherals to share the same IOs in a configurable manner) Candidate will be responsible for RTL design for integration of IO pads into SoC , building the required multiplexing logic and necessary power control signals integration. Strong fundamentals in DFT/Fault-grading and/or hands on experience. Significant Technical Contribution in to Logic IP/SoC Design &Architectural activities. Sound & Practical Written and Verbal Communication Skills. Your Profile You are best equipped for this task if you have: Must have worked in ASIC Design flow, with ASIC experience of 7 to 12years. Must be strong in scripting using Perl/Python Must be familiar with RTL design for ASIC development using Verilog. Must be familiar with LINT (LEDA/Spyglass),Clock-Domain -Crossing analysis, UPF, MVRC, Synthesis, Timing constraints and debugging S TAreports. Strong mindset towards automation of repetitive work. Strong fundamentals in DFT/Fault -grading and/or hands on experience. Significant Technical Contribution into Logic IP/SoC Design &Architectural activities. Sound & Practical Written and Verbal Communication Skills. Moderate Individual Contributor with Freedom to Act, Team work and Learn

Manage Silicon/Solution project through full life cycle from inception to mass production In your new role you will: Manage Silicon/Solution project through full life cycle from inception to mass production Lead product development projects with significant complexity, risk and noticeable impact for the WCS organization Look at the bigger picture, with business in mind, in order to identify challenges and work closely with your stakeholders to come-up with solutions Identify, scope, prioritize (drive, if necessary) manufacturing improvement i n yield, quality, cost and capacity Conduct a forward-looking risk management to identify possible mitigation measures and/or backup scenarios Assume full responsibility for your projects by continuously assessing the progress and adjusting the project plan to ensure that goals are met even in the face of challenges. You are best equipped for this task if you have: A degree in Electrical Engineering, Physics, Microelectronics or similar At least 6 years of professional experience related including 4 years of leading projects and project teams A formal PM certification (e.g. IPMA or PMI) or training or hands on Project Management experience is plus Hands-on project management experience in the arena of mixed signal ASIC development. Experience with IC Design, ASIC flow is a plus. Experience with larger cross functional projects and inter-disciplinary teams a plus. Leadership skills, a strong driver mentality and a proven ability for on-time delivery Experience in managing crisis situations and conflicts Great intercultural competencies and communication skills and bring your messages across with excellent English skills Ability to thrive in a matrix organization Willingness to travel if needed

Expert in implementing Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. In your new role you will: Responsible for SoC DFT Architecture definition / implementation / verification / silicon debug of SoC/Full Chip. Need to implement Scan insertion, LPCT, LBIST, Hybrid-TK, Compression Logic and DRC analysis of implemented Testability logic structures. Responsible for ATPG, DRC analysis, Test coverage debug , Memory BIST implementation and verification. Owner ship of JTAG/BSCAN/iJTAG, P1500 implementation and verification, Stuck-at / TDF / Bridging / Cell-aware / iddq fault models. Good debug skills in ZERO delay and SDF based scan/MBIST/JTAG simulations. Hands on experience in analysis and debug of above-mentioned test domains. Hands of experience in post silicon debug of scan/MBIST patterns/yield fall out You are best equipped for this task if you have: ASIC flow understanding. Experienced in LEC, CLP, power analysis flow is preferred The ability to work as an individual and as part of a team to deliver complex SoCs starting from the creation of the DFT spec, implementation, verification, and Post silicon debug. In addition, be self-motivated with the initiative to seek constant improvements in the DFT design methodologies . The candidate must also possess strong initiative, analytical/problem solving skills, team working skills, ability to multitask and be able to work within a diverse team environment. Scripting skills such as PERL/TCL/Python are preferred Degree & Discipline: BE/B.Tech Electrical/Electronic or ME/M Tech in VLSI design. Experience in Industry: 12+ years of in DFT implementation, verification and post silicon debug areas

Grounds up verification environment development using SV/ UVM is a must5+ yrs Bangalore/ Pune One of the Serdes of high speed protocols like PCIe or USB 3 or MIPI Testplanning, AMS Setup, Experience in wreal, RNM, Verilog A VCS Primesim AMS and Primesim XA tool lExperience in wreal, RNM, Verilog A, exp in System Verilog and UVM

Requisition #: 15086 Our Mission: Powering Innovation That Drives Human Advancement When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. Summary / Role Purpose As Senior Application Engineer, you will be part of the team deploying Ansys EDA products across all top Semiconductor companies. This involves working with Software developers, Architects, Product Specialists to get the product developed, and deploy it on leading edge SoCs across Semiconductor companies. Key focus areas will include all areas related to IP/SoC/3DIC Power Integrity, Signal Integrity, Reliability aspects like EM/ESD/Thermal, Advanced timing/jitter, Packaging - the top challenges for any chip design on advanced nodes like 7/5/3 nm. Key Duties and Responsibilities Be a senior member of Application Engineering Team that Works with Global-Customers / IP-providers / Foundries to understand design challenges of cutting-edge SoCs 3DICs on 7/5/3 nm and creates EDA product specifications. Works with Product development team to get state-of-the-art EDA products developed. Works on Ansys-Seascape platform - Semiconductor Industry s First and Only True Big-Data design Platform! Works with top Semiconductor companies around the globe to deploy EDA products for solving Power/Signal/Reliability challenges across Chip-Package-System at 7/5/3 nm. Works on RedHawk and RedHawk-SC to help users and to perform EMIR/power-integrity sign-off analysis. Provides expert guidance / consultation to Customers around the globe for solving design challenges. Minimum Education/Certification Requirements and Experience BS in Engineering, Electrical/Electronics Engineering, Computer Science, or related field with 5 years experience, MS with 3 years experience, or PhD 3+ years of prior experience in either of a) ASIC Physical design, b) Power-Integrity / Signal-Integrity / Reliability Closure c) Custom circuit design and simulation Bachelor s/Master s degree in Electronics Engineering/VLSI from Top Institutions Strong problem-solving skills Good programming skills Excellent verbal and written communication skills Preferred Qualifications and Skills Passion to learn and deploy new technologies. Ability for minimal travel At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential. We are ONE Ansys. We operate on three key components: the commitments to our stakeholders, the behaviors of how we work together, and the actions of how we deliver results. Together as ONE Ansys, we are powering innovation that drives human advancement. Our Commitments: Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values: Adaptability: Be open, welcome whats next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions: We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results INCLUSION IS AT OUR CORE We believe diverse thinking leads to better outcomes. We are committed to creating and nurturing a workplace that fuels this by welcoming people, no matter their background, identity, or experience, to a workplace where they are valued and where diversity, inclusion, equity, and belonging thrive. WELCOME WHAT S NEXT IN YOUR CAREER AT ANSYS At Ansys, you will find yourself among the sharpest minds and most visionary leaders across the globe. Collectively we strive to change the world with innovative technology and transformational solutions. With a prestigious reputation in working with well-known, world-class companies, standards at Ansys are high met by those willing to rise to the occasion and meet those challenges head on. Our team is passionate about pushing the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. At Ansys, it s about the learning, the discovery, and the collaboration. It s about the what s next as much as the mission accomplished. And it s about the melding of disciplined intellect with strategic direction and results that have, can, and do impact real people in real ways. All this is forged within a working environment built on respect, autonomy, and ethics. CREATING A PLACE WE RE PROUD TO BE Ansys is an SP 500 company and a member of the NASDAQ-100. We are proud to have been recognized for the following more recent awards, although our list goes on: Newsweek s Most Loved Workplace globally and in the U.S., Gold Stevie Award Winner, America s Most Responsible Companies, Fast Company World Changing Ideas, Great Place to Work Certified (Belgium, China, Greece, France, India, Japan, Korea, Spain, Sweden, Taiwan, and U.K.). For more information, please visit us at www.ansys.com Ansys is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. Ansys does not accept unsolicited referrals for vacancies, and any unsolicited referral will become the property of Ansys. Upon hire, no fee will be owed to the agency, person, or entity.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelors or Masters degree from a top-tier institute. 8-14 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in complete Netlist2GDS:Floorplan, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Hand on experience in lower technology nodes. Job Requirements: Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA. Managing and driving a small team for project execution and PPA targets Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

About The Role : Conducts verification of IP and/or SoC microarchitecture using formal verification tools, methodologies, and technologies based on model checking and equivalence checking algorithms. Creates comprehensive formal verification test and coverage plans including definition of formal verification scope, strategy, and techniques. Creates abstraction models for convergence on the design, carves out the right boundaries for the design, and tracks, verifies, and applies abstraction techniques. Develops formal proofs to implement the verification plan, reviews the completed proofs, and develops new formal verification methodologies. Performs convergence on design by creating formal verification methodology, abstraction, and simulation techniques. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Understands the binary decision diagram (BDD) and data flow graph (DFG) for data paths and resolves the BDD complexity on arithmetic. Applies understanding of modeling architecture to simplify and model the problem and uses tools to formally prove protocols and architectures. Qualifications Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum Qualifications: Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 10+ years of industry experience, OR Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related STEM degree plus 8+ years of industry experience The years of experience mentioned above must focus on formal verification Preferred Qualifications: Knowledge of GPU Formal verification experience in at least one of these areas:Arbitration logic, low power design, memory controller, transaction router/bridge. Inside this Business Group The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Strong knowledge of digital design and SOC architecture. Good understanding of OOP concepts Experience in HVL such as System Verilog, UVM/OVM & System C Experience in HDL such as Verilog Knowledge of ARM/DSP CPU architecture, High Speed Peripherals like USB2/3, PCIE or Audio/Multimedia Familiarity with Power-aware Verification, GLS, Test vector generation is a plus Exposure to Version managers like Clearcase/perforce Scripting language like Perl, Tcl or Python Analytical and Debugging skills Experience in Hifi Processor, Soundwire interface, ANC, DMA, I2S verification experience is a Plus. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. 12-15 years of experience with a Bachelor's/ Masters degree in Electrical/ Electronics engineering Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Summary: Position for 3-8 years of experience in design verification of complex Qualcomm propriety DSP/NPU IP DSP team is responsible for delivering high-performance DSP/NPU cores which are at the heart of Qualcomm's multi-tier SoC roadmap targeted for mobile space, AI, Automotive and more. Qualcomm is one of the largest fabless semiconductor design companies in the world, generating over $35 Billion in annual revenues from chipsets and royalties from intellectual property. Job Responsibilities: Drive design verification of DSP IP by working with a global DSP design team involving architecture, implementation, power, post silicon and back-end teams. Implement and improve System Verilog/UVM Testbench Architecture. Develop and deploy new verification methodologies, automation to continuously improve quality and efficiency. Develop design corresponding test plans, architect and develop verification environments, and meet coverage goals. Hands-on simulations and ability to debug not only IP level, but Subsystem and SoC level fails and bugs. Complete all required verification activities at IP level and ensure high quality commercial success of our products. Assertions, simulation, formal verification (static property checking), HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, emulation are all tools you will use on a daily basis. Responsible gate level simulation bring-up, gate level verification with timing simulations. Responsible for power aware RTL verification and gate level simulation. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Skillset/Experience: 3-8 years experience in processor/ASIC design verification Solid background and understanding of Digital Design, Processor Architecture , Processor Verification and Power aware verification. Expertise in System Verilog Testbench Architecture and implementation. Experience in writing C based and assembly level testcases is preferred. Exposure to power aware implementation and verification using UPF is a plus. Experience with advanced verification techniques such as formal and assertions is a plus. Gate-Level Simulation and Debug "” 0-delay, timing annotated and power aware. Experience in System Verilog/UVM, and with simulators from Synopsys/Mentor/Cadence . Scripting/Automation Skills "” Perl, Python, Shell, Make file TCI . Solid analytical and debugging skills, strong knowledge of digital design and good understanding of Object Oriented Programming (OOP) concepts. Experience in Hardware verification languages (HVL) such as SystemVerilog testbench (OVM/UVM) and SystemC and Hardware description languages (HDL) such as Verilog, SystemVerilog is preferred. Experience in verification of Processor subsystems is preferred. Experience in creating validation suite and building automation. Should have excellent inter-personal and communication skills. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. We are hiring across mutliple roles in the below domain: 1. Physical Design 2.RTL Design 3. Design Verification 4. STA/ Synthesis 5. DFT 6. FPGA Emulation 7. Validation Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. QCT is actively seeking candidates for VLSI Methodology and R&D positions. You will be part of the backend methodology team that develops innovative solutions for Qualcomms chip implementation flow. As a digital ASIC R&D Engineer, you will play a vital role in addressing challenges with Performance, Power, and Area (PPA) scaling tradeoffs to qualify technology entitlement of advance process nodes. You will be responsible for research and develop methods to improve efficiency of digital ASIC design flow and chip quality/yield. The job scope includes design automation, post-silicon debug and data mining. Required Skills Coding with Python, Perl, TCL and/or C++ Working knowledge in Digital VLSI implementation (netlist to GDS) STA Power Distribution Network (PDN) Hands on experience with EDA tools (Primetime, ICC2, Innovus, Tempus, etc.) Expected Experience: 2- 10 years of relevant industry experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Overview: Person will be responsible for developing next generation SoCs for mobile products and its adjacencies. The role will require the candidate to understand and work on all aspects of VLSI development from micro architecture and platform architecture, front end design, and design convergence. The person is also responsible for overseeing physical design and verification aspects. About The Role :: - Full chip design for multi million gates SoC- Digital design and development (RTL)- Good understanding of the design convergence cycle in terms of architecture, micro-architecture, synthesis, timing closure and verification- Manage IP dependencies, planning and tracking of all front end design related tasks- Driving the project milestones across the design, verification and physical implementations Minimum Qualifications: - Minimum 15 years of solid experience SoC design- Developing architecture and micro-architecture from specs- Understanding of various bus protocols AHB, AXI and peripherals like USB, SDCC- Understanding of Memory controller designs and Microprocessors is an added advantage- Understanding of Chip IO design and packaging is an added advantage- Familiarity with various bus protocols like AHB, AXI is highly desired- Ability to review top level test plans- Expertise in Synopsys Design Compiler Synthesis and formal verification with Cadence LEC- Working knowledge of timing closure is a must - Should have good post silicon bring up and debug experience - Should have good SoC integration exposure and its challenges - Should have good exposure to design verification aspects - Having SoC specification to GDS to commercialization experience is highly desired - Needs to makes effective and timely decisions, even with incomplete information.- Should possess a strong understanding of a particular technical area and accumulated significant experience in this area and other related areas.- Provides direction, mentoring, and leadership to a small to medium sized groups.- Should possess strong communication and leadership skills to ensure effective communication with Program Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification & Validation team is currently looking for self-motivated engineers who will perform ARM or DSP based SOC Pre-Si and Post Si validation including system level validation and debug. The ideal candidate should leverage his knowledge and experience to provide leadership, technical guidance, and execution of silicon validation of ARM or DSP based multiple SOC projects and platforms Experience in SoC pre/post silicon validation. ARM based System-On-Chip Pre-Silicon emulation and Post-Silicon ASIC Validation experience related to board bring up and debug. Perform system level validation and debug Debug experience with Lauterbach Trace32 environment. Test equipment like Logic analyzer, Oscilloscope and Protocol analyzers. Embedded software development of low level hardware drivers in C language. Working experience related to one or more of the following is required. ARM/DSP Processors/USB/PCIE, Ethernet Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 2-6yrs experience Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Spec: Understand Video Codec specification for respective blocks Micro-architect of sub-block design Understand all interfaces/Config for respective blocks Coding and debugging the functionality for all respective blocks Perform design optimizations for Power/Area/Timing/Performance Skillset looking for: Strong DSP/Multimedia Domain Knowledge on Video Codecs/Computer Vision along with Hardware Implementation is preferred. Experience in micro-architecting & designing complex datapath cores for ASICs/SoCs including AI/ML cores for CV applications Experience with RTL coding using Verilog/VHDL/system Verilog Familiar with the Synthesis and Formal Verification Simulation debugging with Verdi & log file. Exposure in scripting Familiar with the Linting, CDC, Low Power etc. Good team player. Need to interact with the verification engineers proactively Ability to debug and solve issues independently Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelors or Masters degree from a top-tier institute. 6-11 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job Requirements: Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA. Applicants : Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies : Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

ESSENTIAL DUTIES AND RESPONSIBILITIES Create architecture and design documents pertinent to the various phases of NAND development. Drive system level architecture decisions across NAND storage technologies. Become the subject matter expert, owner for NAND system engineering and provide technical leadership. Responsible for mentoring and innovation and defining the technical strategy. Follow Agile methodologies in development. Youll be on a scrum team responsible for NAND products. This includes innovation, design, implementation and debug of algorithms, data structures, drivers needed for our large and complex environment. Deliver on cutting-edge storage products. Work with cross functional teams to develop NAND solutions and products. Self-motivated to work both unsupervised and as part of an agile team. Collaborate to develop self and others within group. Participate in planning and coordinating significant technical investigations from problem statement to conclusions. Understand end to end product lifecycle.

About Marvell . Your Team, Your Impact Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system level knowledge, Marvells infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for multiple market segments. What You Can Expect Collaborate with the Architecture team to define the micro-architecture of the chip. Develop specifications and micro-architecture for one or more blocks. Implement RTL coding using best practices. Work with physical design teams for synthesis and timing signoff. Partner with verification teams on test plans, coverage analysis, and debugging. Support post-silicon validation for production qualification. Coordinate with project managers on task allocation and mentorship. Engage with multiple design centers to enhance methodologies. Collaborate with software teams to ensure compatibility with software use cases. Mentor and provide technical guidance to junior engineers. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and 12-15 years of related professional experience or Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 10-12 years of experience. Micro-architecture experience for complex Custom/ASIC products. Strong logic design and debugging skills; expertise in AHB, AXI, I2C, UART. Hands-on RTL design, synthesis, timing closure, formal verification, and gate-level simulations. Knowledge of PCIe, SPI, USB, DDR2/DDR3 is a plus. Proficiency in front-end design tools and methodologies. Scripting skills in Perl, Tcl, UNIX shell are a plus. Strong leadership, communication, and problem-solving skills. Ability to thrive in a fast-paced environment and drive team success Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-KP1

We are seeking a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team . This role requires strong analytical skills, attention to detail, and collaboration with cross-functional teams . Proficiency in EDA tools and digital design principles is essential. Location: Noida (Hybrid 3 days work in office) Experience: 6 to 15 years Key Responsibilities & Skills: Work with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes (3nm, 5nm, 16nm). Strong knowledge of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff . Experience with EDA tools such as Genus, Fusion Compiler, PrimeTime, Tempus, Conformal . Strong scripting skills in Perl, TCL, Python for automation and flow development. To apply, click on the Apply option or share your resume with Heena at heena.k@randstad.in

Seeking an experienced Embedded FW Developer for work on NVMe over Fabrics Controllers. Candidate should have strong knowledge and experience with all aspects of Embedded FW development - including Definition, Design, Implementation, Verification, and Troubleshooting. ESSENTIAL DUTIES AND RESPONSIBILITIES Coding, debugging, and integrating firmware, as well as the integration, regression, and requirement testing of complex SW/HW/ASIC/FPGA systems Analyze requirements to determine the feasibility of design and schedule Consult with ASIC/HW/FW engineers to evaluate interface between hardware and firmware, and operational and performance requirements of the overall system Develop firmware testing along with firmware development Document Firmware Architecture Review FW test plans and provide input Automation using scripting for efficiency, where relevant.

About Marvell . Your Team, Your Impact Marvell is empowering the global data economy. Whether at the network core or edge, our leadership technologies make it possible for the world s data to be processed, moved, stored and secured faster and more reliably. With leading intellectual property and deep system level knowledge, Marvells infrastructure semiconductor solutions are transforming the 5G, cloud computing, enterprise and automotive markets of tomorrow. Marvell Compute and Custom Solutions has been at the forefront of developing and delivering leading edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast-growing product lines, Marvell technology is powering the next-generation data processing and workload acceleration platforms for multiple market segments. What You Can Expect Lead DV efforts for blocks, subsystems, and top-level verification. Develop and maintain UVM-based verification environments. Define and review test plans with architecture and design teams. Verify designs using directed and constrained random techniques. Maintain regression, debug failures, and analyze coverage. Drive verification to meet coverage targets. Contribute to next-gen data processing and hardware accelerator verification. Focus on networking domain verification for future solutions. Ensure design closure using innovative and automated techniques. What Were Looking For Bachelor s or Master s degree in Computer Science, Electrical Engineering, or a related field with 8+ years of professional experience. Strong experience with Verilog, SystemVerilog, and UVM. Expertise in unit and subsystem verification, modern verification concepts. Proficiency in SystemVerilog, C, C++, and scripting (Perl, Tcl, Python preferred). Strong debugging skills and verification flow optimization. Collaborate with design teams on specs, test plans, and verification strategies. Develop and maintain UVM-based testbenches for ASIC SoCs. Execute verification, maintain regressions, and debug failures. Excellent verbal and written communication skills. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-KP1

About The Role : Develops the logic design, register transfer level (RTL) coding, and simulation for an IP required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure highquality integration and verification of the IP block. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications Qualifications:BE , MTech in EC/EE. 4+ years' experience. Expertise in PCIe , Ethernet domain is a plusMinimum Qualifications:Bachelor's in Electronics Engineering with at least 4 yrs of experience in the following areas (master's degree may offset experience partially).Documentation related to bachelor's degree completion will be required.Frontend Development and related areas.Knowledge in RTL IP design , previous experience in RTL designExpertise in System Verilog, RTL coding.Digital Design Techniques.Possesses strong analytical and debug skills.Intermediate to advanced English level.Motivated for innovations in domain knowledge Inside this Business Group The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers.