778 Asic Jobs - Page 19

You have a passion for modern, complex processor architecture, digital design as we'll as verification/design quality. You are a team player who has excellent communication skills, strong analytical & problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi site environment are keys to being successful in this role. KEY RESPONSIBILITIES: RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design Architect and design of power management features, cache, coherency. Design optimization for implementing power efficient IP, implementing the RTL using low power techniques Responsible for the inter IP integration issues resolution Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design Architecting, micro-architecting and documentation of the design features Lead design team from all aspects of the RTL deliverables. Mentor the junior members of the RTL team to meet the team goals Represents AMD to the outside technical community, partners and vendors Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion. PREFERRED EXPERIENCE: 12+ years of experience in Digital IP/ASIC design and Verilog RTL development Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. Should be we'll versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. Should possess expertise in front-end EDA tools sign-off and its flows. Familiarity with low power design and low power flow is an added plus. Ability to program with scripting languages such as Python or Perl is a plus; Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements; Proven interpersonal skills, leadership and teamwork; Excellent writing skills in the English language, editing and organizational skills required; Skilled at prioritization and multi-tasking; Good understanding of engineering terminology used within the semiconductor industry; Good understanding of digital design concepts; Knowledge of, or experience in, functional design verification or design is highly desired. ACADEMIC CREDENTIALS: masters degree preferred with emphasis in Electrical/Electronics Engineering, Computer Engineering, or VLSI design Engineering.

Middle Office, as part of Corporate and Investment Banking Operations, offers an exciting opportunity to support a diverse array of external and internal businesses. This role provides exceptional operational processing capabilities across all asset classes. The Regulatory Controls Team plays a crucial role in the comprehensive implementation of Regulatory Trade Reporting within the Equities Operations Group, ensuring compliance and efficiency in operations. As a Vice President in the Regulatory Controls Team within Middle Office, you will be responsible for the full end-to-end implementation of Regulatory Trade Reporting in the Equities Operations Group. You will lead remediation initiatives, manage regulatory queries, and represent the team in senior control forums, providing an opportunity to enhance your leadership and analytical skills in a dynamic environment. Job Responsibilities Monitoring existing controls and implementing new controls across various regulations (CFTC, MIFID, EMIR, HKMA, ASIC etc.) for EDG, Prime, and Cash Equities business. Leading remediation initiatives in partnership with the technology team to address reporting data quality issues. Governing and monitoring key regulatory metrics. Improving reporting quality through various completeness and accuracy checks via centrally coordinated controls testing activities. Managing external regulator and internal compliance queries, reviews, and testing. Representing on Senior Control Forums. Escalating issues and errors. Reviewing and signing off on attestations. Analyzing requirements, testing, and conducting post-go-live checks for new regulations, changes to existing regulations, strategic system transformation, migrations, and NBIAs. Managing vendor relationships. Planning budget allocations. Required qualifications, skills and capabilities Previous experience in the Financial Services industry with strong understanding of Equity Derivatives products Strong understanding of Dodd Frank CFTC Trade Reporting and EMIR Trade Reporting Excellent Business Analysis skills to drill down the complex Regulatory Reporting requirements for multiple jurisdictions Excellent problem solving skills in order to identify, understand and address operational and technical issues Strong product knowledge; thorough understanding of the end to end transaction cycle for derivative products CA/ MBA/graduate with 10 years experience in operations. Familiarity with a global banks process & operational environment including management and external reporting is a must. Strong business knowledge i.e. Investment Banking, including OTC product, process and system knowledge. Skilled in identifying talent, recruiting, coaching, mentoring, and developing team members Skilled in MS office applications including Outlook, PowerPoint, Excel, Word, Access and Project Flexibility for travel to region ( APAC / EMEA / Americas) for period of 2-3 months within short notice in case of business requirements.

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a learning machine that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life s work , to amplify human creativity and intelligence. As an NVIDIAN, you ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world! Design-for-Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post-silicon validation on some of the industrys most complex semiconductor chips. What youll be doing: As a member in our team, you will be responsible for the design and implementation of state-of-the-art designs in test access mechanisms, memory BIST and scan compression. Your responsibility will also include verification and silicon bringup of Scan ATPG and other DFT features. In addition, you will help develop and deploy DFT methodologies for our next generation products. Be apart of innovation to strive improve the quality of DFT methods. You will also need to work with multi-functional teams to incorporate DFT features into the chip. Occasional travel and also some late hours online meetings involved during critical milestones. What we need to see: BSEE or MSEE from reputed institutions or equivalent experience. 2+ Years of experience preferably in Design for testability (DFT) You should be well versed with static timing Analysis, ECO, ASIC/Logic Design Flow, HDL and Digital logic design. Experience in RTL and Gates verification and simulation. You need to be familiar with BIST architecture and JTAG/IEEE1149. 1/IEEE1500. Strong DFT knowledge in Scan ATPG, compression techniques and memory test. Strong analytical and problem solving skills. Expert coding skills in industry standard scripting languages. Extraordinary written and oral communication skills with the curiosity to work on rare challenges. NVIDIA is widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If youre creative and autonomous, we want to hear from you! NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. #LI-Hybrid

As a Logic design lead in the IBM Systems division, you will be responsible for the micro architecture, design and development of a high-bandwidth, low-latency on-chip interconnect (NoC) and chip-to-chip interconnect and integration into high-performance IBM Systems. Design and architect different interconnect topologies as driven by bandwidth, latency and RAS requirements Develop the features, present the proposed architecture in the High level design discussion Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW teams to develop the feature Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of relevant experience - At least 1 generation of processor interconnect design delivery leadership (eg UPI, axi, amba, NoC). - Expertise of SMP coherency - Experience in different on-chip interconnect topologies (e.g., mesh, crossbar) - Understanding of various snoop and data network protocols - Understanding of latency & bandwidth requirements and effective means of implementation - Working knowledge of queuing theory - numa/nuca architecture - Proficient in HDLs- VHDL / Verilog - Experience in High speed and Power efficient logic design -Experience in working with verification, validation, physical design teams for design closure including test plan reviews and verification coverage - Good understanding of Physical Design and able to collaborate with physical design team for floor planning, wire layer usage and budgets, placement of blocks for achieving high-performance design - Experience in leading uarch, RTL design teams for feature enhancements.

-Lead the Architecture, Design and development of processor L2 and LLC (Last Level Cache) for high-performance IBM Systems. - Design and architect L2 cache and LLC as driven by capacity, latency, bandwidth, and RAS requirements. - Develop the features, present the proposed architecture in the High level design discussions - Develop micro-architecture, Design RTL, Collaborate with Verification, DFT, Physical design, FW, SW teams to develop the feature - Signoff the Pre-silicon Design that meets all the functional, area and timing goals - Participate in silicon bring-up and validation of the hardware - Lead a team of engineers, guide and mentor team members, represent as Logic Design Lead in global forums. - Estimate the overall effort to develop the feature. - Estimate silicon area and wire usage for the feature Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise -4+ years of relevant experience - At least 1 generation of processor L2 cache or LLC design delivery leadership. - Expertise in cache coherence protocols for symmetric multiprocessors (SMP), covering both chip SMP and multi-socket SMP. - Experience with NuCA / NuMA (Non-uniform Cache / Memory architecture) architectures and implementations. - Working knowledge of memory consistency, store ordering, weakly and strongly ordered memory. - Experience in logical and physical design of caches including directories (tags, set associative memories), data SRAM, design for low latency, multiple parallel finite state machine design, deadlock-free designs.

Location: Bangalore, India Thales people architect solutions that enable two-thirds of planes to take off and land safely. We create in-flight entertainment systems that engross 50 million fliers every year and we develop the avionics that control the world s largest commercial aircrafts. Our simulators train the next generation of pilots for fighter jets, transporters and search and rescue helicopters. And, together, each and every member of our aerospace team makes a difference. Hardware Architect for Electronic design Thales India Engineering Competency Center (ECC) in Bangalore is seeking a Technical Lead/Sr Technical lead to be part of Hardware engineering team. In this role, you will be responsible for Hardware subsystems architectural design, trade-off analysis, feasibility studies, Proposal preparation, Project scheduling/costing, Project monitoring and managing and IVVQ for various Thales products (Defense and aerospace applications). You will be coordinating with the Solution/System Architect and the Project Design Authority (PDA) to ensure consistency with the Solution/System architecture and with the hardware, industry and procurement strategies. Necessary to technically and functionally co-ordinate with engineers of hardware disciplines such as Board design (digital, analog, RF and power supplies), FPGA design (FPGA, ASIC), low-level software (in agreement with the software architect), mechanical design, testability and means of tests, industrial design (in agreement with the Head of Industry). This position requires having good level of expertise in its hardware product design, development and qualification. Qualifications: B.Tech/B.E in Electronics, Instrumentation engineering or equivalent with 10 to 16 years of relevant experience. Higher qualifications of Masters or Post-graduation is desirable. Domain experience in Avionics systems or defense system is desirable. Responsibilities: Develop, stabilize and maintain hardware architecture for all phases of the life cycle from design to delivery to customer. Perform trade-off analysis of different technologies and feasibility studies to propose the best architecture design Implement architecture choices based on trade-offs between cost, supply chain, customer requirements and technology possibilities Lead and coordinate the architectural studies of Hardware under his responsibility Perform trade-off analysis of different technologies and feasibility studies to propose the best architecture design Identify risks and opportunities related to the hardware architecture Propose and implement risk reduction plans and opportunities for validation Preparing project proposal including schedule and efforts Preparation of the associated project documentation and reviews Coordinating with different stakeholders like Industrialization, IPO, suppliers, engineering, WPM, customer to prepare the optimal project proposals Integration of Hardware, Software and Firmware and performs IVVQ Collaborative work applying quality standards and internal processes Ensure compliance with standards, product development plans (reuse policy), material, industrial and purchasing strategies Skills experience: Must have strong experience in complete Hardware certified development life cycle (Technical feasibility, requirements writing, preliminary and detailed design, prototype manufacturing, test and evaluation, qualification and certification) Must have gained experience in piloting a lot of development work, involving in product testing in external labs for hardware products Must have experience in the IVVQ (Integration, Verification, Validation and Qualification) including requirements management Must have strong experience of integration of Hardware, FPGA firmware, mechanical packaging, low-level software and application software on Hardware unit. Must have good experience in bench test set-up, functional testing and performance evaluation Must have experience in developing IVV Test procedures (PVP/ATP), Test Reports (PVR/ATR), Qualification by similarity reports (QBSR) and other documents required by certification authorities for airborne products. Must have strong experience to troubleshoot on electronics and embedded hardware systems to find the root cause and to fix with a suitable solution. Must have experience to ensure the reporting progress of the project along with KPI. Must have experience to manage risks and opportunities at Hardware solution architecture. Must be rigorous, organized, autonomous and proactive, and motivated by a position within a multidisciplinary team. Must have demonstrated leadership skills on complex topics. Must have experience of working with multi-disciplinary team (BL engineering team, Lab technicians, external labs, Purchase team, Engineering teams and manufacturing teams) Must have experience in interfacing with external test facilities for environmental and EMI/EMC and other electrical tests as per MIL-STD/IEC61000/DO-160 standards. Should be familiar with Knowledge of production trades: procurement, manufacturing, delivery Knowledge of Certification DO254/DO160, Safety of aeronautical systems (ARP4761), and Knowledge of ARP4754B will be helpful. Product knowledge in avionics fields: civil and military calculators, displays, inertia, GNSS, probes will be helpful. Excellent communication and collaboration skills in an international multi-cultural environment (France, Canada, India, UK). Ability to work across different departments and establish effective relationships.

Software Engineer This role has been designed as Onsite with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today s complex world. Our culture thrives on finding new and better ways to accelerate what s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. : Aruba is an HPE Company, and a leading provider of next-generation network access solutions for the mobile enterprise. Helping some the largest companies in the world modernize their networks to meet the demands of a digital future, Aruba is redefining the Intelligent Edge - and creating new customer experiences across intelligent spaces and digital workspaces. Join us redefine what s next for you. What you ll do: We are looking for development engineers (Specialist) positions to lead and drive the development of the future enterprise networking products and solutions. Specialists play key hands-on roles in multi-discipline teams working on new and next generation products and solutions. This includes software design, SW development and test, customer interaction, and on-going product support. Projects typically involve coordination with cross-functional internal stakeholders. We are looking for Technical Lead (Expert) positions to lead and drive the development of the future enterprise networking products and solutions. Experts play key hands-on roles in multi-discipline teams working on new and next generation products and solutions. This includes owning product design, product feature definition, software design, SW development and test, customer interaction, and on-going product support. Projects typically involve coordination with cross-functional internal stakeholders. Key Responsibilities: Design new features, own end-to-end delivery of subsystems/software modules Leads a project team of software systems engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions within stipulated budget/time. Collaborates and communicates with management, internal, and outsourced development partners on software systems design status, project progress, and issue resolution Work often involves cross organizational team guidance: Hardware, Firmware, System management, Field Support, Documentation, Sales teams, Architects, other organizations, etc. to arrive at best solutions. Reviews and evaluates designs and project activities for compliance with systems design and development guidelines and standards; provides tangible feedback to improve product quality and mitigate failure risk. Strong ability to negotiate and build consensus in engineering community on technical decisions Leads multiple project teams of software systems engineers including review guidance and support for junior team member s. What you need to bring: Education and Experience Bachelors or Masters degree in Computer Science, Information Systems, or equivalent 12+ years of experience Required Domain Expertise: Enterprise networking products with expertise in L2/L3/Security Protocols Features Knowledge and Skills Experience designing and developing firmware for switches and/or network controllers. Strong Operating System experience - Linux, GreenHills, VxWorks etc Knowledge of ASIC architectures - e.g. Broadcom, etc Expert knowledge in C Extensive experience in overall architecture of firmware and interaction with hardware designs for products and solutions. Designing and integrating network solutions into overall architecture and hardware design across multiple platforms Mastery of advanced networking concepts - L2(xSTP, VLAN, LACP, LLDP, TRILL), L3 (OSPF, BGP, Tunnels), Multicast (PIM, IGMP), IPv6, Security (RADIUS/TACACS, SSH, Access Contrl), ACL/QoS. Experience on both platform dependent and platform independent networking protocol work. Ability to internalize standards (IEEE, IETF) and convert into deliverables - design/code etc History of innovation with multiple patents or deployed solutions in the field of software, firmware, or network design Experience with Network Development Tools - Sniffer, Traffic Generators, IXIA, Spirent etc Strong Network troubleshooting ability encompassing: OS, Network Stack, Sniffers, switches, external network. Strong Network troubleshooting ability Experience using version control system - ex. GIT/Clearcase Ability to create white papers and advanced training material for solutions. Excellent written and verbal communication skills. Excellent analytical and problem solving skills. Strongly Desired skills Identifies and evaluates new technologies, innovations, and solutions for alignment with technology roadmap and business value. Drives innovation and integration of new technologies into projects and activities in the software systems design organization. Demonstrated history of contribution to Intellectual Property and Innovation. Linux Device Driver experience Working knowledge of Assembly code Experience in writing Secure Software Experience in agile development methodology Additional Skills: Cloud Architectures, Cross Domain Knowledge, Design Thinking, Development Fundamentals, DevOps, Distributed Computing, Microservices Fluency, Full Stack Development, Security-First Mindset, Solutions Design, Testing Automation, User Experience (UX) What We Can Offer You: Health Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing. Personal Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have whether you want to become a knowledge expert in your field or apply your skills to another division. Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. Lets Stay Connected: Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE. #india #aruba Job: Engineering Job Level: TCP_02 HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity . Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities. HPE will comply with all applicable laws related to employer use of arrest and conviction records, including laws requiring employers to consider for employment qualified applicants with criminal histories.

Role: CAD Engineer (Frontend and Backend) Experience: 10+years Location: Bangalore Notice Period: Max 15days preferred Role Overview We are looking for a CAD Engineer (Frontend and Backend)to deploy and support our front-end tools, to develop scripts to automate regression and debug flows, and to work along with our design, implementation and verification teams. What youll do Deploy and support front-end tools, such as, RTL simulators, low power tools, static RTL checkers such as Lint, CDC/RDC/SDC/DFT, and formal verification. Develop scripts to automate regression and debug flows, and to enable Continuous Integration/Continuous Delivery (CI/CD) Streamline utilization of compute infrastructure using load distribution tools Identify and prioritize needs of internal users and develop capabilities for them Proficiently use scripts to integrate tools, repos and compute infrastructure Configure and maintain project progress Dashboards. Interface with EDA vendors for license and tool installations Deploy tools and methodologies across geographies for global teams working together What you need to have B.Tech/B.E in Computer Engineering (or allied discipline e.g. Electrical, Electronics) 10+ years of relevant experience in CAD or allied disciplines 4+ years in a CAD role for a several 100 million gate Silicon ASIC project Knowledge and understanding of ASIC flow Proficiency in python, bash, c, Makefiles Proficiency in administration of Linux systems (such as Redhat Enterprise) Proficiency in distributed version control such as Git and/or Mercurial (Hg) Eager to learn, fast pick up and timely execution Experience in working with the standard CAD tools that are prevalent in the industry Nice-to-haves Experience with Kubernetes or LSF Systems Experience with HW Design Flows, System Verilog, Verilog, EDA/CAD, and Flows Experience with Javascript, CSS, and Web development frameworks

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Senior Digital Design Engineer - PCIe We are seeking a Senior Digital Design Engineer with deep expertise in high-performance controller and bridge design, micro-architecture, RTL implementation, and IP integration. The ideal candidate will play a critical role in the development of cutting-edge connectivity solutions. Key Responsibilities: Design and implement high-performance digital solutions, including RTL development and synthesis. Collaborate with cross-functional teams on IP integration for processor IPs and peripherals Deep knowledge of processor boot process and peripheral implementation with boot firmware in mind Own block-level and full-chip designs from architecture to GDS, focusing on designs at nodes 16nm. Ensure timing closure, assess verification completeness, and oversee pre- and post-silicon debug. Utilize tools from Synopsys/Cadence to ensure first-pass silicon success and apply expertise in UVM-based verification flows Basic Qualifications / Experience Level: Bachelor s in Electronics/Electrical engineering (Masters preferred). 8+ years of digital design experience, with 4+ years focused on processor, peripherals and full chip implementation. Proven expertise in RTL development, synthesis, and timing closure. Experience with front-end design, gate-level simulations, and design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Required Expertise: Proven expertise in micro-architecture development and RTL development for block level and full-chip designs at advanced nodes ( Experience with front-end design, gate-level simulations, and supporting design verification through multiple ASIC T/O cycles . Hands-on experience with processor IP (ARM/ARC) Experience of working on PCIe is a must. Hands-on pre-silicon and post-silicon implementing peripherals for I2C/SPI/UART Hands-on experience with complex DMA engines and FW interaction. Strong proficiency in System Verilog/Verilog and scripting (Python/Perl). Experience with block-level and full-chip design at advanced nodes ( 16nm). Silicon bring-up and post-silicon debug experience. Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design verification. Strong work ethic, ability to handle multiple tasks, and a proactive, customer-focused attitude. Preferred Experience: Knowledge and experience implementing secure boot and security mechanisms like authentication and attestation is a plus. Knowledge of system-level design with ARM/ARC/RISC-V processors sub systems Experience of working on PCIe/UAL is a big plus. Understanding of PAD design, DFT, and floor planning. Experience in synthesis, and timing closure is a big plus. Experience with NIC, switch, or storage product development. Familiarity with working in design and verification workflows in a CI/CD environment. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Job Summary: As a Static Timing Analysis (STA) Engineer at Astera Labs, you will play a pivotal role in ensuring our digital ASIC designs meet stringent timing and performance requirements, with a strong emphasis on Design for Test (DFT). You will be responsible for timing analysis, identifying critical paths, and driving timing closure across complex ASICs and chiplets. This is a unique opportunity to contribute to the development of cutting-edge silicon for AI infrastructure. Key Responsibilities: Collaborate with design and architecture teams to define and refine timing constraints for DFT across complex ASICs and chiplets. Perform timing analysis and signoff in all DFT modes using industry-standard tools such as PrimeTime. Analyze and resolve timing violations, with a focus on test modes and scan paths. Integrate and validate timing constraints from third-party IPs and external vendors. Generate detailed timing reports, highlighting violations and providing optimization recommendations. Work closely with RTL, physical design, DFT, and verification teams to resolve timing-related issues. Contribute to the development and enhancement of STA methodologies, flows, and automation. Demonstrate a professional attitude with the ability to prioritize tasks, plan effectively for meetings, and work independently with minimal supervision. Exhibit an entrepreneurial mindset and a can-do attitude, acting quickly and decisively with the customer in mind. Collaborate effectively with cross-functional and globally distributed teams. Basic Qualifications: Bachelor s degree in Electrical or Computer Engineering with 8+ years of ASIC experience, or a Master s degree with 6+ years. Proven experience with block- and full-chip timing constraints, including test modes. Strong understanding of DFT architectures and hands-on experience closing timing specifically for DFT. Experience integrating third-party IPs and managing associated timing constraints. Proficiency in STA tools such as PrimeTime and scripting for automation. Preferred Qualifications: Experience with automated constraint generation and validation tools. Familiarity with high-speed interfaces such as PCIe, CXL, and DDR. Strong communication and collaboration skills in cross-functional, globally distributed teams. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

About Marvell . Your Team, Your Impact Central Engineering (CCDS) - ASIC India in Marvell is a Custom Logic Design and Methodology group responsible for delivering complex ASIC chips. This group provides technology development, EDA/methodology development and IP/Chip design development. India DFT team is a key part of Global DFT community with global ownership and responsibility for delivering generic and more advanced custom DFT architecture solutions, methodology and design. You will be working with this team to directly enable customer DFT requirements. What You Can Expect The candidate Marvell is looking for will have: Very good knowledge on SCAN/ATPG/JTAG/MBIST Good Knowledge and understanding on JTAG for IEEE1149. 1/6 standards Proficiency in Industry standard Tools for Scan insertion, ATPG, MBIST and JTAG. (Preferably Synopsys/Mentor tools) Proven experience on Test structures for DFT, IP Integration, ATPG Fault models, test point insertion, coverage improvement techniques Proven experience in Scan insertion techniques at block level and Chip top level Good hands on experience on Memory BIST generation, Insertion, verification on RTL/Netlist level Cross domain knowledge to resolve DFT issues with design, synthesis, Physical design, STA team Good knowledge on Perl/ Tcl scripting Proven experience on gate level simulations with notiming and SDF based simulations Experience with Post-Si ramp up and debug on ATE Very good team player capabilities and excellent communication skills to work with a variety of teams across the global organization High sense of responsibility and ownership within the team for successful Tapeout and Post -Si ramp up of the project. What Were Looking For Bachelor s degree in Computer Science, Electrical Engineering or related fields and at least 5 years of related professional experience. Master s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3-4 years of experience. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

asic Function Handle and administer Family Medical Leave Act standalone (as well as other leave) claims and adhere to federal and state regulatory and/or company plan requirements and established FMLA workflow procedures Complete eligibility decisions and review for entitlement, gather pertinent data when necessary, from employee, physicians office or employer through outgoing calls, email, fax or other supporting systems. Promptly review new FMLA and other leave claims within regulatory timelines, evaluate against appropriate leave plans and make initial claim decision. Perform leave administration tasks as required, including recertification of health condition, intermittent claim tracking, RTW confirmation, return phone calls, etc. Update systems to accurately reflect leave status and ensure appropriate diary documentation exists Business recommended TAT to complete the activity is up to 5 business days to maintain compliance measures The position is expected to do absence management and adjudication on Federal, State and company leaves. Interact with claim specialist, claim support specialist, QA, Claims Unit Leader (stateside supervisors), employees, employers/customer and physician s office Essential Functions: Analyze, validate and process transactions as per Desktop procedures (L3 L4) Analyze and research all discrepancies Research Investigate and resolve outstanding items Determine eligibility, entitlement and applicable plan provisions while meeting timeliness goals Clear and accurate written and verbal communication (Mix of scripted/unscripted) with employee, employer stateside resources by email and outgoing calls Establish action plans for each file to bring claims to resolution Utilize internal and external specialty resources to maximize impact on each claim file Use PC programs to increase productivity and performance Ensure that the assigned targets are met in accordance with SLA, Performance Guarantee and Internal standards Ensure that the quality of transaction is in compliance with predefined parameters as defined by Process Excellence Work as a team member to meet office goals to obtain disability s vision while demonstrating core values and meeting key measures Ensure adherence to established attendance schedules Close visual activity - viewing a computer terminal and extensive reading Any other essential function that may occur from time to time as directed by the Supervisor. Primary Internal Interactions UM for the purpose of reporting performance, escalation handling, clarifying concerns, and seeking feedback and support Manager for the purpose of settling issues left unresolved by the AM and monthly evaluation of performance Subject Matter Expert for the purpose of work thread related issues and escalated transactions QCA for the purpose of feedback and internal Performance Guarantee quality audit team Trainers for the purpose of Pre-process and Process DCA training Disability Customer Advocates for escalation resolution Primary External Interactions End customer to be contacted through emails/calls for information gathering/decision update Claims specialist other Stateside Teams on emails/calls SME / Trainers at the client end for training

As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Drive Full chip physical integration and verification (DRC/LVS, ERC, DFM checks) Work with fab and fab contacts for all the tapeout activities leading to final tapeout. Work closely with physical design implementation and signoff team to achieve faster TAT Work closely with CAD team to come up with new flows and methodologies in the physical verification domain PREFERRED SKILLSET: Experience : More that 12 years of relevant experience. Driven multiple tapeouts across different technology nodes Sound knowledge of full chip physical integration and verification flows Hands on experience on industry standard tools such as Calibre and ICV Sound understanding for DRC/LVS decks. Should be able to make updates as required. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

People Operations, Associate Bengaluru, Karnataka, India Apply Now Save Category: People Hire Type: Employee Job ID 10255 Date posted 06/11/2025 Share this job Email LinkedIn X Facebook We Are: You Are: You are a proactive and detail-oriented individual with a passion for People Operations. With 0 - 2 years of experience in HR operations, you have a solid foundation in managing the employee lifecycle from pre-onboarding through offboarding. Your experience with HRIS systems, ServiceNow, particularly SuccessFactors or similar tools, equips you with the skills to handle complex employee data and processes. You hold a BA/BS degree and have honed your ability to manage multiple tasks and deadlines with exceptional organizational skills. Your strong stakeholder partnering skills enable you to collaborate effectively with various teams, ensuring the delivery of impactful HR solutions. You are familiar with Microsoft Office and project management tools, and your excellent written and spoken communication skills make you a reliable and clear communicator. Your resourceful problem-solving abilities allow you to troubleshoot issues independently and drive meaningful solutions. What You ll Be Doing: Collaborate effectively with stakeholders to proactively determine and deliver relevant and impactful People (HR) operation solutions to business and system challenges. - Accurately perform employee lifecycle transactions/processes, including onboarding, offboarding, transfers/job status changes, timekeeping, time off and leave, extended workforce, and other responsibilities as assigned. - Recommend and draft employee lifecycle processes and procedures that enhance and optimize existing HR practices, ensuring they remain fit for purpose and benefit stakeholder teams. - Be a trusted resource for People (HR) systems, data, and process knowledge to interpret and analyze processes. - Drive People operation enhancements by supporting new module roll-out and optimization initiatives. - Manage requests, workflows, and develop a knowledge base and reporting metrics using ServiceNow. The Impact You Will Have: Streamline HR processes to improve efficiency and accuracy in employee lifecycle management. - Enhance stakeholder satisfaction by delivering timely and effective HR solutions. - Contribute to the optimization of HR practices, ensuring they are aligned with organizational goals. - Support the successful rollout and adoption of new HR modules and tools. - Provide valuable insights and data analysis to drive informed decision-making in HR operations. - Foster a collaborative and supportive HR environment, building trust with stakeholders and team members. What You ll Need: 0 - 2 years of People (HR) operations related APAC work experience. - BA/BS degree. - Experience with HRIS administration, particularly SuccessFactors or similar tools. - Knowledge of managing requests, workflows, developing knowledgebase, and reporting metrics using ServiceNow. - Exceptional organizational skills and attention to detail. - Proficiency in Microsoft Office suite and familiarity with project management tools. - Excellent written and spoken communication skills. Who You Are: Detail-oriented and organized. - Resourceful problem-solver. - Effective communicator. - Collaborative team player. - Proactive and initiative-driven. The Team You ll Be A Part Of: You will be part of a dynamic People Operations team focused on delivering exceptional HR services and solutions. Our team collaborates closely with various stakeholders to ensure smooth HR operations and continuous improvement of HR processes. We value innovation, teamwork, and a commitment to excellence in all our endeavors. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Now Save Relevant Jobs ASIC Digital Design, Architect Bengaluru, India Engineering Senior Software Engineer (R&D Engineering) Yerevan, Armenia Engineering R&D Engineering, Staff Engineer - Design Verification/ VIP Verification Engineers Noida, India Engineering

About KYOCERA AVX KYOCERA AVX is a leading global manufacturer of advanced electronic components designed to accelerate technological innovation and create a better future. A fully owned subsidiary of Kyocera Corporation, KYOCERA AVX has an extensive global presence with multiple research, development and manufacturing facilities in more than 15 countries. KYOCERA AVX products support a variety of environmentally friendly technologies aimed at conserving existing energy resources and creating reliable systems. KYOCERA AVX components are included in countless products that help ensure that this generation as well as future generations benefit from clean, environmentally friendly technologies. Manager RD - Electronics Full Time 410, Sector 8, Imt Manesar, Gurugram, Haryana 122050, Indien With Professional Experience 5/20/25 Company: KYOCERA AVX Components (New Delhi) Pvt Ltd. J ob Title: Manager RD - Electronics Location: Building No. 410, Sector-8, IMT Manesar, Haryana - 122 050 (India) Industry: Production Company, Electrical Engineering (ca. 220 employees) Employment Type: Full time Employees Union: No Job Summary The role is responsible for managing all electronic design and delivery activities for assigned automotive projects, ensuring high-quality standards, cost optimization, and compliance with industry regulations. This position requires a proactive professional who excels in a collaborative, fast-paced environment and is committed to delivering innovative and reliable automotive electronic designs. Responsibilities Leading a team of electronics engineers Design and development of electronic sensors for automotive applications (e.g., speed sensors, pedal modules, position sensors, ABS sensors) Evaluate customer requirements and align designs with electrical functionality standards also in global context Understand and compile overseas designs, comparing customer requirements with design specifications Review and optimize electronic schematics and PCB designs for cost and time efficiency Create and validate product specifications, including electrical requirements and EMC/EMI test plans based on CISPR, ISO IEC, and OEM standards Interface with process engineering teams to resolve PCB panel design issues and ensure manufacturability Resolve technical issues related to PCB design and support both design and manufacturing teams with solutions Oversee DFMEA, prototype build documentation (BOM, process flow, testing parameters, etc.), and ensure compliance with quality standards Conduct calculations, analysis, and evaluations to ensure a high-quality and robust circuit design Provide primary technical component/module information to support cost estimation and quotation processes Support standardization efforts by referencing engineering specifications and improving the quality of existing standards Collaborate with cross-functional teams (mechanical, electrical, and process engineering) to meet design and packaging requirements Coordinate with test labs for EMC/EMI testing and documentation Lead task tracking, planning, and delegation within the project team Requirements Education: Bachelor s or higher degree in Electronics Engineering or a related field (Masters preferred) Experience: 8+ years of relevant experience in automotive process and product development Experience in leading a team Experience in the field of circuit design, sensor technology Hands-on experience in PCB population, testing, debugging, and fabrication processes Knowledge: Expertise in hardware PCB design for automotive sensors, including design flows from library creation to Gerber release Comprehensive understanding of EMI/EMC standards (CISPR, ISO IEC, IPC, MIL) and optimization techniques for automotive applications Strong knowledge of automotive sensing technologies (e.g. Hall, inductive sensing) and switches (especially two wheeler) Knowledge of FTA analysis and FIT rate Skills: Proficiency in ASIC programming, analog/digital circuit design, and tools like Altium Designer, LTSpice, and CST Studio Suite Experience in multi-layer PCB design for automotive environment and signal integrity optimization Strong skills in documentation and BOM creation Advanced computer skills in MS Office and SAP Strong English communication skills, knowledge of German or Japanese is a plus Attributes: Outgoing, adaptable, and collaborative Proactive and detail-oriented, with a commitment to delivering high-quality solutions Willingness to travel domestically and internationally Are you interested Please send us your detailed application, including your salary expectations and earliest possible starting date. We are looking forward to meeting you.

Job Details: : Develops the logic design, register transfer level (RTL) coding, and simulation for an SoC design and integrates logic of IP blocks and subsystems into a full chip SoC or discrete component design. Participates in the definition of architecture and microarchitecture features of the block being designed. Performs quality checks in various logic design aspects ranging from RTL to timing/power convergence. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Follows secure development practices to address the security threat model and security objects within the design. Works with IP providers to integrate and validate IPs at the SoC level. Drives quality assurance compliance for smooth IPSoC handoff. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Minimum Qualifications: A bachelors degree in electrical/computer engineering, Computer Science or related field with 6+ years of experience (or) a masters degree with 4+ years of experience. Preferred Qualification: Relevant experience with skills in SoC flows, RTL integration and Globals (Clocking, Boot/Reset/Fabrics, DfD, Fuse, etc). Experience in subsystem design and HSIO protocols such as PCIe, UCIe is a plus. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: Xeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOC's and critical IP's sustain Intels Xeon and 5G networking roadmap. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

Job Details: : Performs functional logic verification of an integrated SoC to ensure design will meet specifications. Defines and develops scalable and reusable block, subsystem, and SoC verification plans, test benches, and the verification environment to meet the required level of coverage and confirm to microarchitecture specifications. Executes verification plans and defines and runs emulation and system simulation models to verify the design, analyze power and performance, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates and communicates with SoC architects, microarchitects, full chip architects, RTL developers, postsilicon, and physical design teams to improve verification of complex architectural and microarchitectural features. Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Incorporates and executes security activities within test plans, including regression and debug tests, to ensure security coverage. Maintains and improves existing functional verification infrastructure and methodology. Absorbs learning from postsilicon on the quality of validation done during presilicon development, updates test plan for missing coverages, and proliferates to future products. Qualifications: Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. listed below would be obtained through a combination of Industry job-relevant experience, internship experiences and or school work/classes/research. Education Requirement- Bachelors degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 10+ years of industry work experience, or- Masters degree in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 9+ years of industry work experience, or- PhD in Electrical or Computer Engineering, Computer Science, Math, Physics, or related field plus 8+ years of related work experience.Minimum Qualifications- 9+ years of experience in relevant Pre-Silicon validation position having gone through multiple project cycles to gather in-depth know how. Solid work experience in designing, verifying, and validating complex hardware systems. Solid programming skills in C/C++, Verilog, System Verilog, UVM, assembly, and Python. Proficient in debugging SOC, fabric, NOC, memory, various protocols like PCIE or Ethernet, or other complex ASIC designs. Knowledge of advanced computer architecture and micro-architecture concepts. Experience with writing directed and random test cases. Experience with design verification and validation methodologies and strategies. Good communication skills, and a team player. Able to work independently in a fast-paced team and environment. Desired - Deep knowledge of system architecture including CPU, Data path packet processing flows , Boot Flows, fabrics, interconnects, NOC, memory sub-systems, I/O peripherals (UART/SPI), bus protocols (AXI/APB), PCIE, Ethernet, DMA etc. Experience with boot, reset, clock and power management. Job Type: Experienced Hire Shift: Shift 1 (India) Primary Location: India, Bangalore Additional Locations: Business group: The Network & Edge Group brings together our network connectivity and edge into a business unit chartered to drive technology end to end product leadership. It's leadership Ethernet, Switch, IPU, Photonics, Network and Edge portfolio is comprised of leadership products critically important to our customers. Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Position of Trust N/A Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. *

HI Greetings for the day!!1 I am hiring for TOP MNC for VLSI Design Engineer, check the attached JD for more clarity, kindly revert with below details ON swati@thinkpeople.in Total Experience Rel Exp Current CTC Exp ctc Location Notice period Current org primary skill ; Skills : PD / DV / AMS / DFT / ASIC OR RTL Design: (please mention) JD; Analog Circuit Design Lead : TitleMandatory Skills Experience : 7+ years Responsibilities :1. Experience in entire Analog IP development including circuit design, layout, AMS verification, and characterization.2. Must have led the entire Analog IP development cycle and team.3. Circuit Design implementation of IPs including LDOs, Band Gap reference, Current Generators, POR, ADC/DACs, PLLs, Oscillators, General Purpose IOs, Temperature sensor, SERDES, PHYs, Die to Die interconnect, High-speed IOs, etc.4. Analog/custom layout design in advanced CMOS process.5. Ability to understand design constraints and implement high-quality layouts.6. Conceptualize and implement chip-level mixed signal simulation environments (testbenches, run scripts, etc...).7. Characterization.8. Hands-on experience on lower FINFET technology nodes and design/PPA trade-offs DFT Interface with ASIC design teams to ensure DFT design rules and coverages are met. Generate high-quality manufacturing ATPG test patterns for stuck-at (SAF), transition fault (TDF) models through the use of on-chip test compression techniques. MBIST verification (including repair), test pattern generation through Mentor tool. ATPG (SAF, TDF) and MBIST verification using unit delay and min/max timing corner simulations. Work with Product/Test engineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting post-silicon debug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG, MBIST and bring-up on ATE. Developing, enhancing and maintaining scripts as necessary. Preferred Experience : Bachelor's degree in Computer Science, Electrical/Electronics Engineering 7 to 12 years' experience in ASIC/DFT - simulation and Silicon validation. Should have worked in at least one Full chip DFT Detailed knowledge on DFT concepts, pattern simulation, Silicon debug and yield enhancement. In-depth knowledge and hands-on experience in ATPG - coverage analysis. In-depth knowledge of Memory verification, repair and failure root-cause analysis. Experience with any of these tools is required: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim. Expertise in scripting languages such as Perl, shell, etc. is an added advantage. Ability to work in an international team, dynamic environment with good communication skills. Ability to learn and adapt to new tools, methodologies. Ability to do multi-tasking & work on several high-priority designs in parallel. RTL Role : ASIC RTL Engineer / Digital Design Exp : 7 + Mandatory Skill : • RTL, Coding, Design, IP Design, SOC Development, Lint, CDC , Micro Architecture - Mandatory • PCIe/DDR/Ethernet - Any One • I2C,UART/SPI - Any One • Spyglass Lint/CDC / Synopsys DC / Verdi/Xcellium - Any One • Scripting languages like Make flow, Perl ,shell, python - Any One Good to have : • processor architecture / ARM debug architecture • debug issues for multiple subsystems • create/review design documents for multiple subsystems • Able to support physical design, verification, DFT and SW teams on design queries and reviews Details JD : Expertise in SoC subsystem/IP design Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog In depth knowledge on RTL quality checks (Lint, CDC) Knowledge of synthesis and low power is a plus Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB) Good understanding of timing concepts Knowledge of one or more of the interface protocols a. PCIe b. DDR c. Ethernet d. I2C, UART, SPI PD; Floor Planning/Innovus/Fusion Compiler Experience on programming in Tcl/Tk/Perl. Physical Design Methodologies and submicron technology of 28nm and lower technology nodes. DV Must Have: SV/UVM Test Bentch Developement Any Protocols: (PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM) • 8+ years of hands-on DV experience in System Verilog/UVM. •Must be able to own and drive the verification of a block / subsystem or a SOC. •Extensive experience in IP/sub-system and/or SoC level verification based on SV/UVM. •Must have extensive experience in verification of one or more of the following: •PCI Express or UCIe, CXL or NVM • AXI, ACE or CHI • Ethernet, RoCE or RDMA • DDR or LPDDR or HBM • ARM or RISC-V CPU based subsystem or SOC level verification using C/Assembly languages • Power Aware Simulations using UPF

Role & Responsibilities: Collaborate with cross-functional teams including hardware engineers, software developers, and medical experts to design, develop, and test embedded software and FPGA solutions. Develop firmware for FPGAs from vendors such as Xilinx Zynq, Lattice Semiconductor, and Texas Instruments , including SoC implementations and hardware/software co-design . Optimize and implement image and video processing algorithms on embedded platforms and FPGA architectures. Integrate and support FPGA/ASIC-based ISP blocks , ensuring high performance and accuracy in medical imaging applications. Work with SoCs with integrated ISP (e.g., Qualcomm, NVIDIA Jetson, Ambarella, MediaTek) and manage interaction with hardware accelerators. Design and develop firmware for STM32 microcontrollers , with a focus on motion control , real-time responsiveness , and precision actuation . Develop and implement motion control algorithms, including PID control and motor driver integration, for high-precision diagnostic instruments. Implement and optimize communication protocols such as SPI and UART to support system communication and control flows. Utilize real-time operating systems (RTOS) or bare-metal firmware development for deterministic system behavior. Perform thorough testing, debugging, and optimization using tools like oscilloscopes , logic analyzers , and JTAG debuggers . Support product design lifecycle activities including requirements specification , firmware documentation , and design reviews . Preferred candidate profile: Education: Bachelors or Masters degree in Electrical Engineering, Computer Science, or related field. A Ph.D . is a plus for R&D or algorithm-intensive roles, particularly in imaging or signal processing. Professional Experience: 3+ years of hands-on experience in embedded firmware development with strong C/C++ proficiency. Proven experience with FPGA design using VHDL/Verilog , and development with tools like Vivado, Quartus, or Diamond. Experience working with STM32 microcontrollers , including development environments like STM32CubeIDE and IAR Embedded Workbench. Core Technical Expertise: Deep understanding of: SoC and camera architectures Memory hierarchy, DMA engines, cache control, and hardware accelerators Motion control techniques for motor and actuator systems Image Signal Processing (ISP) pipelines: demosaicing, AWB, AE, gamma, sharpening, etc. Familiarity with Linux kernel camera subsystems (e.g., V4L2) . Ability to optimize embedded code for performance, power, and latency. Desirable Knowledge Knowledge of medical device standards and regulations such as ISO 13485 and IEC 62304 . Familiarity with image quality tuning tools (e.g., Imatest, DxO Analyzer). Experience with real-time data acquisition, frame synchronization , and multithreaded image capture pipelines . Soft Skills Strong problem-solving and debugging skills in complex embedded systems. Excellent communication and collaboration abilities, with experience working in interdisciplinary teams .

We are seeking an engineer to join our team that will thrive in a fast-paced work environment, using effective communication , problem-solving and prioritization skills. Individuals that are we'll organized, show great attention to detail, and employ critical thinking are we'll-suited for our team. Senior Member Technical Staff (SMTS) Embedded Software (Data Center GPU & SPSE) AMD India (SPSE) is looking for a strong technical leader to lead an Embedded Software development team to lead and deliver modular, quality oriented, and extensible FW infrastructure. You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. Closely collaborate with peer development and QA teams, architecture, customer support and product line management. As a key member of the Technical management staff, contribute to the vision and strategy of continuous integration, improved development processes, quality and productivity improvements. KEY RESPONSIBILITIES: Lead and drive the Embedded software development for all new and sustaining AMD EPYC Server, DC GPU Products. Responsible for Architecture, Design, Development and Mentoring team members to become successful at AMD. Responsible for partnering leveraging all the development work done by Core engineering in Data Center GPU , with a strong focus on enabling differentiating features for the success of Data Center GPU business. Partner with Platform team to bring-up the AMD Security processor firmware during SOC bring-up. Partner with HW and Silicon validation teams for verification of all features in the Silicon IP. Support the triage and debug of critical bugs from AMD security processor firmware side that require multi-team interactions. Support field requests / escalations from Customer application engineering team. Influence and support software engineers with design reviews, code reviews, and licensing reviews for open source as we'll closed source code offerings. Train and enable Applications Engineers and FAEs on software solutions with esp. focus on AMD differentiated features and technologies Provide product and technology feedback and consultancy into Enterprise product management, Enterprise Server Systems and SW efforts, and AMD technology and product planning Work on soft ware POCs (Proof of Concepts) for early enablement of new technology. PREFERRED EXPERIENCE: Exposure to systems architecture Solid programming skills in C experience or a strong desire to learn secure coding processes and basics of encryption technology are essential. Experience with source control systems such as git Industry experiences developing embedded firmware or device drivers. Experience with JTAG debuggers and other tools. Experience with pre-silicon development on FPGAs , microntrollers or simulation environments Experience with processor, board, or ASIC bring-up. An understanding of embedded firmware or device driver development. An understanding of assembly level programming and optimizations. An understanding of PCIe, SPDM, Virtualization, and IOMMU Experiences working with RTOS and other embedded OS environments. ACADEMIC CREDENTIALS: Bachelor s or Master s in Electrical Engineer, Computer Engineering, Computer Science, or a closely related field

Education: BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute Responsibilities: Translate requirements to design specification by working closely with system architects Translate the design specification to optimal digital micro-architecture RTL coding using Verilog and System Verilog Building reusable sub-systems and systems, and drive automation with hands-on contribution during the integration of IP Manage the complexity of Safety, Security and Low-power as overlays on vanilla sub-system architectures Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems Meet power, performance and area goals by micro-architecture optimization Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Work closely with DFT and PD teams for signoff Support Silicon validation Mentor junior design engineers Minimum Qualifications: BE/BS/Mtech/M.E degree in Electrical/Electronics/Computer science from a reputed institute 10 years of relevant experience Strong engineering background in embedded system design, including ASIC microarchitecture, computer architecture, SoC architecture, and custom or standard DSP or hardware accelerator microarchitecture Strong hands-on RTL coding experience and debugging skills Digital Subsystem, clocking and full chip integration experience Expertise in timing constraints development and critical path timing closure Experience with silicon and software product development and understanding the product development lifecycle Knowledge of industry standard bus protocols such as AHB, APB, AXI Experience in digital signal processing and Matlab modeling is highly desirable Excellent verbal and written communication skills to work effectively with teams spread geographically Experience in mentoring junior engineers

Education: BTech/MTech degree in Electrical/Electronics/Computer science from a reputed institute Job Responsibilities: Translate requirements to design specification by working closely with system architects Translate the design specification to optimal digital micro-architecture RTL coding using Verilog and System Verilog Continuously improve the development and support model employed on Digital Processing sub-systems to ensure a high level of scalability and efficiency in product engagements Support simulation, DFT and silicon verification and validation of sub-systems, test and evaluation of ASIC products and FPGA development systems Meet power, performance and area goals by micro-architecture optimization Work closely with DV team to develop test-plans Front end implementation - Lint/CDC , synthesis, Timing constraint development Support Silicon validation Job Requirements: BTech/MTech degree in Electrical/Electronics/VLSI with 3-6 years of experience from reputed institutes Strong hands-on RTL coding experience and debugging skills Expertise in timing constraints development and critical path timing closure Coding up in C tests on M3 Series Cortex based products. Expertise in automation and scripting languages like Perl, Python, and shell scripting Proficient in Version control systems, such as Perforce, SVN, SOS Proficient in Verilog, System Verilog and UVM Ability to manage multiple tasks and work effectively in a fast-paced environment Able to communicate effectively

As a Functional verification engineer, you will be working on IBM server processors/SOC or ASICs used in IBM servers. Leading the development of the verification environment, testbenches and writing testcases. Develop skills in IBM Functional verification tools and methodologies. Owning and Driving execution of subunits/unit level Verification Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality design Work with development team to ensure coverage criteria is met. Work with logic and development teams to identify test scenarios, create test plans and execute the scenarios. Work with IBM Verification community to improve Verification methodology. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 + years of experience in Functional Verification of processors or ASICs. Minimum 9+ years of experience in any of the following Computer architecture knowledge, Processor core design specifications, instruction set architecture and logic verification. Core architecture/micro-architecture verification Multi-processor cache coherency, Memory subsystem verification. IO subsystem knowledge, any of the protocols like PCIE/CXL, DDR, Flash, Ethernet etc AXI/AHB/ACE/ACE-lite fabric verification or any other SoC fabric verification. Gate level simulation and emulation. Track record in leading teams Clock domain crossing and reset domain crossing verification Knowledge of functional verification methodology - UVM/OVM/System Verilog/SystemC/ Knowledge of HDLs (Verilog, VHDL) Developed test-plans and test strategies for IP/unit/block level verification. Good object-oriented programming skills in C/C++, scripting languages like Python/Perl. Worked on multiple levels of verification (unit/element/sub-system/system level) Development experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflow Exposure in developing testbench environment, write complex test scenario, debugging and triaging fails Experience in driving verification coverage closure. Preferred technical and professional experience Stress testing and ability to identify corner case scenarios. Knowledge of high-speed SERDES and PHY Verification Good understanding of computer system architecture and microarchitecture. Knowledge in IP Integration and SoC level verification. Good understanding of the Server System

Candidate should have experience in Software development, tools development role, firmware development role or validation tools development.Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He/She will be working on processor Bringup Activities and own key debugs during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must work on coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical ExpertiseVery proficient in C programming, Strong Scripting skills. Over 5 years experience in hands on Software development using C, C++. Computer Architecture KnowledgeIn-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache CoherencyExperience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and ConceptsAtleast 2 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education