333 Asic Jobs - Page 11

Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Logic Design Engineer to join our MIC IDC Design team in Bengaluru In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer, As a PE Logic Design Engineer, youll play a pivotal role in designing and implementing the worlds best Registered Clocking Driver (RCD) products In this full-time role, youll report directly to our Logic Design Manager Our MIC IDC is dedicated to leverage over three decades of high-performance memory expertise to deliver cutting-edge memory interface chipset solutions, enhancing memory bandwidth and capacity for data centers and client applications alike, and your contributions will be instrumental in RCD product development, Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work Responsibilities Understand the spec requirements and convert into a micro architecture specification, Realize the RTL design using Verilog/System Verilog, Works with verification teams in defining the test plan and reviews the test coverage, Does pre implementation design checks like lint, CDC, RDC, constraint validation, Works with physical design team in defining the design and timing constraints and driving implementation till timing closure, Interact with cross functional circuit teams for new product development Participate in Architecture level discussions to define the specifications, Post silicon validation support in bringing up parts, Qualifications Minimum 10 years of solid ASIC logic/Digital design expertise with bachelors degree or masters degree Strong digital design fundamentals, Strong hands on expertise in HDLs like Verilog/System Verilog, Experience with EDA tools for simulation, synthesis, and timing analysis and logic equivalence check, Knowledge of High speed protocols is plus, Strong scripting abilities using Perl/Tcl/python is a plus Strong written and verbal communication skills Able to break down technical concepts to a larger audience is desired, About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP to advance data center connectivity and solve the bottleneck between memory and processing With over 30 years of semiconductor experience, we are a leading provider of high-performance products and innovations that maximize the bandwidth, capacity and security for AI and other data-intensive workloads Our world-class team is the foundation of our company, and our innovative spirit drives us to develop the cutting-edge products and technologies essential for tomorrows systems, Rambus offers a competitive compensation package, including base salary, bonus, equity and employee benefits, Rambus is committed to cultivating a culture where we actively seek to understand, respect, and celebrate the complex and rich identities of ourselves and others Our Diversity, Equity, and Inclusion initiatives are geared towards valuing the differences in backgrounds, experiences, and thoughts at Rambus to help enhance collaboration, teamwork, engagement, and innovation At Rambus, we believe that we can be our best when every member of our organization feels respected, included, and heard, Rambus is proud to be an Equal Employment Opportunity and Affirmative Action employer We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, or other applicable legally protected characteristics, Rambus is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans during our job application procedures If you require assistance or an accommodation due to a disability, please feel free to inform us in your application, Rambus does not accept unsolicited resumes from headhunters, recruitment agencies or fee-based recruitment services, For more information about Rambus, visit rambus For additional information on life at Rambus and our current openings, check out rambus /careers/,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a highly experienced and motivated professional with a solid background in SoC RTL Design With over 12 years of experience, you have honed your skills in RTL Design, Lint, CDC, RDC, Synthesis, and Constraints Development You possess a deep understanding of design concepts, ASIC flows, and stakeholder management Your technical expertise allows you to debug and diagnose violations and errors, set up flows and methodologies for RTL Signoff tools, and develop timing constraints You are an effective leader, capable of managing and growing a team, providing continuous feedback, and improving the quality of deliverables Your excellent communication skills help you interact with customers, peers, and management to understand needs, report status, and resolve issues efficiently, What Youll Be Doing: Manage and lead a team of 7-8 SoC/Subsystem RTL Design Engineers for various customer engagements, Work with Synopsys customers to understand their needs and define RTL Signoff and design scope and activities, Lead the team to perform various RTL Design and Signoff activities for SoC Subsystems such as SoC u-Architecture and Integration, RTL Design (Verilog/SystemVerilog), Lint, CDC, RDC, Synthesis, Constraints Development, Assist and mentor the team in day-to-day activities and grow the capabilities of the RTL Design team for future assignments, Review various results and reports to provide continuous feedback to the team and improve the quality of deliverables, Report status to management and provide suggestions to resolve any issues that may impact execution, Understand the complexity and requirements of RTL Quality Signoff and propose resource requirements to complete the activities, Work with peers to improve methodology and improve execution efficiency, Collaborate with other Synopsys teams including BU AEs and Sales to develop, broaden and deploy Tools, Train the team in design concepts and root-cause analysis, The Impact You Will Have: Drive the successful delivery of SoC Subsystems by leading a skilled team of RTL Design Engineers, Enhance the quality and efficiency of RTL Design and Signoff processes through continuous feedback and methodology improvements, Ensure customer satisfaction by understanding their needs and delivering high-quality solutions, Contribute to the growth and development of the RTL Design team, expanding their capabilities for future projects, Support Synopsysreputation as a leader in chip design and verification through successful project execution, Foster collaboration and innovation within the team and across different Synopsys departments, What Youll Need: E/B Technical expertise in various aspects of RTL Design and Signoff: LINT, CDC, RDC, Technical expertise on setting up flows and methodologies for quick deployment of RTL Signoff tools, Technical expertise in debugging and diagnosing violations and errors, Technical expertise in developing timing constraints and running preliminary synthesis for timing constraints check and area estimation, Ability to lead and manage a team to perform RTL Signoff on complex SoC/Subsystem, Experience with planning and managing various activities related to RTL Signoff and Design, Strong understanding of design concepts, ASIC flows, and stakeholders, Good communication skills, Who You Are: A proactive leader with excellent managerial skills, A team player who can mentor and guide engineers, An effective communicator who can interact with customers and stakeholders, A problem-solver with a keen eye for detail, An innovator who continuously seeks to improve processes, The Team Youll Be A Part Of: As part of the System Solutions Group (SSG), you will lead a team of experts in various Synopsys technologies to deliver architecture, design, verification, implementation, tools, and methodology to enable our customers to complete their most challenging SoC Design projects Our work spans from sub-blocks to full turnkey end-to-end SoCs Our customers range from start-ups to industry leaders, commercial companies, and government agencies, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

Alternate Job Titles: Digital IP Verification Engineer IP Methodology Engineer ASIC Methodology Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: You are a seasoned professional with a strong background in electronics or electrical engineering, holding a Bachelor's or Master's degree from a reputed university With 6-10 years of experience in ASIC/SoC/IP Methodology, you possess a deep understanding of Synopsys implementation and infrastructure tools such as coreConsultant, coreAssembler, SpyGlass/VC-SpyGlass, Fusion Compiler/Design Compiler, Prime Time, Formality, TestMax Manager, TCM, Verdi, and VCS Your proficiency in scripting languages like TCL, Perl, or Python complements your technical expertise You excel in multi-clock designs and understand Clock-Domain-Crossing principles You are an effective communicator, a collaborative team player, and a problem-solver who thrives in dynamic environments, What Youll Be Doing: Create and support innovative Design Methodologies by leveraging feedback from our EDA and Digital IP teams, Integrate Methodologies into the development infrastructures of the Digital IP teams and demonstrate successful results, Support and maintain our regression infrastructure to manage changes and revise methodologies regularly, Test a range of Digital IPs through our Methodologies centered around Synopsys EDA tools, Collaborate with various teams to improve methodologies, enhancing both team and customer experiences, Develop and manage infrastructures, processes, methodologies, and checklists for the SG Digital IP Controllers, The Impact You Will Have: Enhance the efficiency and effectiveness of Digital IP development processes, Ensure high-quality and robust Digital IP products through rigorous methodology testing, Improve customer satisfaction by delivering superior Digital IP solutions, Drive innovation in design methodologies, contributing to Synopsys' leadership in the industry, Facilitate seamless integration of methodologies into development infrastructures, optimizing workflows, Support the continuous improvement of regression infrastructures, ensuring up-to-date methodologies, What Youll Need: Bachelors or Masters degree in electronics or electrical engineering or equivalent from reputed universities, 6-10 years of relevant experience in ASIC/SoC/IP Methodology, Proficiency in Synopsys implementation and infrastructure tools (coreConsultant, coreAssembler, SpyGlass/VC-SpyGlass, Fusion Compiler/Design Compiler, Prime Time, Formality, TestMax Manager, TCM, Verdi, VCS), Familiarity with multi-clock designs and understanding of Clock-Domain-Crossing principles, Proficiency in scripting languages (TCL, Perl, Python), Who You Are: You are an effective communicator with strong collaboration skills You have a knack for problem-solving and possess a systems-level thinking approach Your ability to write code in various scripting languages enables you to develop and manage complex infrastructures and methodologies efficiently, The Team Youll Be A Part Of: You will be joining the Synopsys IP Group Digital Methodology team, a dynamic and innovative group focused on designing, developing, and managing infrastructures, processes, and methodologies for Digital IP Controllers This team thrives on collaboration, continuous improvement, and delivering high-quality solutions to meet the evolving needs of our customers, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

We Are: At Synopsys, we drive the innovations that shape the way we live and connect Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content Join us to transform the future through continuous technological innovation, You Are: An experienced and passionate Analog Design Engineer with 1-3 years of experience in the field You have a strong background in CMOS processes and deep submicron process technologies You understand the intricacies of CMOS circuit design and layout methodology, and you have a basic understanding of analog/mixed signal circuitry Familiarity with ESD concepts is a plus You are knowledgeable about ASIC design flow and JEDEC requirements for DDR interfaces and standards You excel at executing circuit design tasks with a focus on quality and efficiency Your communication skills are excellent, enabling you to interact effectively with internal development teams, What Youll Be Doing: Designing DDR/HBM Memory Interface I/O circuits and layouts, including GPIO and special I/Os, Collaborating with the DDR/HBM PHY team, package engineers, and system engineers to meet design specifications, Ensuring adherence to best practices in circuit design and layout methodology, Conducting thorough design reviews and contributing to the continuous improvement of design processes, Staying updated with the latest advancements in analog design technologies and methodologies, Documenting design processes and providing support for design validation and testing, The Impact You Will Have: Enhancing the performance and reliability of our analog and mixed-signal circuits, Contributing to the development of high-performance DDR/HBM Memory Interfaces, Supporting the overall success of our chip design and IP integration projects, Driving innovation in analog design methodologies and processes, Ensuring our products meet the highest standards of quality and efficiency, Helping Synopsys maintain its leadership position in the semiconductor industry, What Youll Need: Bachelor's or Master's degree in Electronics or Electrical Engineering, 1-3 years of experience in CMOS processes and deep submicron technologies, Proficiency in CMOS circuit design and layout methodology, Basic understanding of analog/mixed signal circuitry, Familiarity with ASIC design flow and JEDEC requirements for DDR interfaces, Who You Are: A detail-oriented engineer with a passion for analog design, An effective communicator who collaborates well with cross-functional teams, A problem-solver who can analyze and address design challenges efficiently, A continuous learner who stays updated with industry trends and advancements, A team player who contributes to the overall success of the project, The Team Youll Be A Part Of: You'll join a dynamic and innovative team of engineers focused on advancing our analog design capabilities Our team is dedicated to pushing the boundaries of technology and delivering cutting-edge solutions for the semiconductor industry We value collaboration, creativity, and a commitment to excellence in everything we do, Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs Our total rewards include both monetary and non-monetary offerings Your recruiter will provide more details about the salary range and benefits during the hiring process,

The role is responsible for managing all electronic design and delivery activities for assigned automotive projects, ensuring high-quality standards, cost optimization, and compliance with industry regulations. This position requires a proactive professional who excels in a collaborative, fast-paced environment and is committed to delivering innovative and reliable automotive electronic designs. Responsibilities Leading a small team of electronics engineers Design and development of electronic sensors for automotive applications (e.g., speed sensors, pedal modules, position sensors, ABS sensors) Evaluate customer requirements and align designs with electrical functionality standards Understand and compile overseas designs, comparing customer requirements with design specifications Review and optimize electronic schematics and PCB designs for cost and time efficiency Create and validate product specifications, including electrical requirements and EMC/EMI test plans based on CISPR, ISO IEC, and OEM standards Interface with process engineering teams to resolve PCB panel design issues and ensure manufacturability Resolve technical issues related to PCB design and support both design and manufacturing teams with solutions Oversee DFMEA, prototype build documentation (BOM, process flow, testing parameters, etc.), and ensure compliance with quality standards Conduct calculations, analysis, and evaluations to ensure a high-quality and robust circuit design Provide primary technical component/module information to support cost estimation and quotation processes Support standardization efforts by referencing engineering specifications and improving the quality of existing standards Collaborate with cross-functional teams (mechanical, electrical, and process engineering) to meet design and packaging requirements Coordinate with test labs for EMC/EMI testing and documentation Lead task tracking, planning, and delegation within the project team Requirements Education: Bachelor s or higher degree in Electronics Engineering or a related field (Masters preferred) Experience: 8+ years of relevant experience in automotive process and product development Experience in leading a team Experience in the field of circuit design, sensor technology Hands-on experience in PCB population, testing, debugging, and fabrication processes Knowledge: Expertise in hardware PCB design for automotive sensors, including design flows from library creation to Gerber release Comprehensive understanding of EMI/EMC standards (CISPR, ISO IEC, IPC, MIL) and optimization techniques for automotive applications Strong knowledge of automotive sensing technologies (e.g. Hall, inductive sensing) and switches (especially two wheeler) Knowledge of FTA analysis and FIT rate Skills: Proficiency in ASIC programming, analog/digital circuit design, and tools like Altium Designer, LTSpice, and CST Studio Suite Experience in multi-layer PCB design for automotive environment and signal integrity optimization Strong skills in documentation and BOM creation Advanced computer skills in MS Office and SAP Strong English communication skills, knowledge of German or Japanese is a plus Attributes: Outgoing, adaptable, and collaborative Proactive and detail-oriented, with a commitment to delivering high-quality solutions Willingness to travel domestically and internationally Are you interested Please send us your detailed application, including your salary expectations and earliest possible starting date. We are looking forward to meeting you.

Job Description SoC Verification Engineer The SoC Development team at Sandisk is seeking highly motivated SoC Verification Engineers to join our talented team, working on cutting-edge controller development for high-performance SoCs used in industry-leading products. Role & Responsibilities: As a SoC Verification Engineer , you will play a key role in ensuring the quality and reliability of our SoC designs. You will be responsible for: Developing verification test plans based on design specifications. Creating and executing test cases across multiple platforms , including RTL simulation, FPGA prototyping, and Palladium emulation . Performing Gate-Level Simulations (GLS) and debugging complex SoC designs. Collaborating with design, architecture, and firmware teams to define verification strategies and drive coverage-driven verification methodologies . Contributing to the development of advanced verification environments , including UVM, PSS testbenches. Analyzing functional coverage and simulation results to enhance verification efficiency and effectiveness. Why Join Us? At Sandisk , you ll be part of a team of highly skilled engineers solving complex verification challenges and driving innovations in data storage solutions . Your work will directly impact the performance and reliability of high-volume new age data solutions, consumer and enterprise products. Together, we ll push the boundaries of technology, unlock the full potential of data, and shape the future of storage solutions. Qualifications Required : BE or MS degree in Electrical/Electronics Engineering or Computer Engineering, with 4-8 years of experience Deep understanding of C, SystemVerilog UVM and coverage driven verification methodology History of building and improving UVM based verification methodology Knowledge on Chiplet Protocols - UCIe Skills : Develop and execute verification plans Proficiency with C, Verilog, System Verilog and UVM based verification Experience in implementing advanced test benches, verification models, scoreboards/checkers. Knowledge in bus protocols - AXI, AHB, APB and bus interconnects Experience with test plan creation and test-bench development Experience with test development and test coverage assessment Excellent debugging and problem-solving skill Knowledge in various interfaces - PCIe, DP, UART, I2C, I2S, SPI, USB, SD Experience working on processor-based SoC -- ARC/ARM/RISC.. Create and modify SoC-level, and sub-system level test benches. Experience in setting up and running gate-level simulations Gate Level / Power-Aware simulations Great written and verbal communication skills Good Programming/Scripting skills with languages such as Python, Perl, TCL, and BASH Interest in ASICs, SoCs, flash memory, semiconductor components Strong team player who can collaborate with colleagues

Apply to this job Meta is hiring ASIC Verification Engineer with in-depth understanding of PCIe Express within the Infrastructure organization. We are looking for individuals with experience in verification of PCIe Switch, Root Complex and Endpoint to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook s data center applications. You will be responsible for the verification closure of a sub-system or SoC from test-planning, Hybrid test bench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC DV Engineer, PCIe Verification Responsibilities Develop and execute verification plans, test cases, and scripts to ensure PCIe interface functionality, performance, and compliance with industry standards. Collaborate with design teams to understand the PCIe interface architecture and identify potential issues. Create and maintain testbenches, including simulation models and tests Perform simulation-based testing, including functional, performance, and compliance testing Analyze test results, identify defects, and work with design teams to resolve issues. Stay up-to-date with industry trends, standards, and best practices related to PCIe verification Debug, root-cause and resolve functional failures in the design, partnering with the Design team Mentor engineers to drive and deliver high confidence verification for highly complex ASIC projects. Minimum Qualifications Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience At least 8+ years of relevant experience Track record of first-pass success in ASIC development Good knowledge of PCIe specifications, protocols, and standards covering Root Complex, End Point and Switch Good hands-on verification experience in PCIe Transaction, Link and Physical layer. Hands-on experience in Verilog, SystemVerilog, UVM , C/C++, Python based verification Experience in IP, Cluster and SoC level verification in both RTL and Gate Level Setup Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments Experience in architecting and implementing DV setup for complex Subsystem and ASICs. Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Preferred Qualifications Experience in development of PCIe Gen6/Gen7 DV testbench and infrastructure from scratch Hands-on experience with integration and usage of varied PCIe vendor VIP Experience in performance verification of PCIe Sub-System for AI/ML Applications etc Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with simulators and waveform debugging tools Experience working across and building relationships with cross-functional design, model and emulation teams About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Apply to this job Meta is hiring ASIC Verification Engineer with background in Simulation Acceleration using Emulation and Hybrid Platforms within the Infrastructure organization. We are looking for individuals with experience in Simulation Acceleration and Emulation to build IP and System On Chip (SoC) for data center applications.As a Design Verification Engineer, you will be part of a dynamic team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook s data center applications. You will be responsible for the verification closure of a sub-system or SoC from test-planning, Hybrid test bench development to verification closure. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success. ASIC DV Engineer, Simulation Acceleration and Hybrid Verification Responsibilities Propose, implement and promote the Simulation Acceleration and Hybrid Verification Methodology to be used across the group, both at the Cluster and at the SoC level Work with Architecture and Design teams to come up with functional, use case and performance test plan for the DUT Define Verification scope, create environment, testplans and close use case scenarios and performance using targeted tests at Cluster and SoC level Debug, root-cause and resolve functional failures in the design, partnering with the Design team Develop and drive continuous Hybrid Verification improvements using the latest methodologies, tools and technologies from the industry Build reusable/scalable environments for Hybrid Verification. Evaluate and recommend solutions for Hybrid Verification and Simulation Acceleration Provide training for internal teams and mentoring engineers related to Hybrid Verification Methodology Minimum Qualifications Bachelors degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience At least 8+ years of relevant experience Track record of first-pass success in ASIC development Hands-on experience in Verilog, SystemVerilog, UVM, C/C++, Python based verification Experience of working with Zebu, Palladium, Veloce HW platforms Experience in Cluster and SoC level verification using Hybrid Simulation and Emulation based methodologies Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments Experience in architecting and implementing Hybrid Verification infrastructure and executing verification cycle Experience using analytical skills to craft novel solutions to tackle industry-level complex designs Demonstrated experience with effective collaboration with cross functional teams Preferred Qualifications Experience in development of Simulation Acceleration and Hybrid verification environments from scratch Experience in performance verification of complex compute blocks like CPU, GPU or HW Accelerators, Ethernet, PCIe, DDR, HBM etc Experience in verification of Data-center applications like Video, AI/ML and Networking designs or integration verification of high-speed interfaces like Ethernet PCIe, DDR, HBM Experience with development of fully automated flows and scripts for data exploration, analysis and performance verification Experience with verification of ARM/RISC-V based sub-systems or SoCs Experience with revision control systems like Mercurial(Hg), Git or SVN Experience with simulators and waveform debugging tools Experience working across and building relationships with cross-functional design, model and emulation teams About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Job Description We are seeking a highly skilled and experienced DFT Engineer to join our dynamic team of engineers to develop the next-generation Flash Controllers. As an SoC DFT Engineer, you will be responsible for defining and implementing industry leading DFT solutions, with emphasis on SCAN, MBIST, BSDL etc. The ideal candidate will have a deep understanding of DFT Architecture, Implementation flow, MBIST, SCAN ATPG & Simulation expertise. ESSENTIAL DUTIES AND RESPONSIBILITIES: DFT Architecture definitions for SoC development Leading complex activities and providing solutions for complex DFT problems. Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs. Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies. Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs. Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology. Qualifications B.Tech / M,Tech / Phd in Electronics, Computer science or Electrical Engineering Minimum 15+ years of experience in DFT Strong understanding of DFT Architecture SKILLS : Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology. Proven track record of driving DFT architecture in complex ASIC designs. Work independently on multiple complex DFT problems across different projects. Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs). Proficiency in SCAN, MBIST implementation. Solid understanding of JTAG & BSDL standards. Good understanding on Test clocking requirements, Test mode timing closure. Proficiency in complex silicon debugs and yield analysis. Solid understanding of SoC architecture and low-power design principles. Understanding of High-Speed interfaces (PCIe or UFS protocols) and experience with SSD/Flash is advantage. Excellent analytical and problem-solving skills. Strong communication skills and the ability to work effectively in cross-functional teams.

Business Information: Our Indian Operations Centre (INOPC) is a competence center with around 2600+ skilled engineers who focus on tendering, engineering, planning, procurement, functional system testing, installation supervision, and commissioning. Over the last decade, INOPC has evolved to become the largest engineering hub serving more than 40 countries across different energy sectors. The team caters to the four business units Transformers, Grid Integration, Grid Automation, High Voltage and has successfully executed engineering and commissioning for projects in more than 80 countries. Mission Statement: We seek a Control Design Engineer for power quality solutions mainly synchronous condenser with medium to high complexity. This function will include complete assignments on medium to large projects requiring engineering that is cost-effective and in accordance with contract specifications, quality standards and safety requirements. Based on technical specification from end customers and inputs from Operating Unit Engineering teams, it is required to prepare system Communication Block Diagram, Network topology, IP list, I/O signal list and Internal validation of RTU, PLCC based system. Furthermore, this function includes work on standard technical specifications for major equipment, providing input to RD activities for plant base solutions. Cost awareness and carrying out comparisons between different solutions, bill of materials, RFQs, vetting of vendor offers, engineering hours estimation, technical risk assessment and opportunity evaluation is also required. The job will include both individual work as well as coordination of engineering resources and interaction with other engineering leads and tendering teams. Effective interaction with project managers, SCM, primary, secondary designers will also be required Roles and responsibilities: Design of Communication Block Diagram along with network topology based on specifications. Design and verify the HMI application for various PQ Control and Protection System. Configuration of SCADA Gateways, Engineering workstation, Network switches, GPS, KVM, GOOSE. Configuration of SCL, CID, ICD files. Creation of I/O signal list, SCADA Signal list. Control logic design and internal validation. Undertake PSCAD and RTDS simulation studies individually or as part of a team to verify control dynamic performance of FACTS solution. Support tenders, delivery projects, and RD activities during control system dynamic performance studies. Lead, supervise and coordinate engineering project teams and towards other departments related to scope, schedule progress, approvals, budget, targets, resource load cost-to-complete. Ensure Engineering processes and base solutions are applied. Conduct engineering project reviews and report progress and cost-to-complete engineering- and project manager. Establish contacts with suppliers for technical support to improve material quality and/or to optimize on costs. Prepare base design and detailed designs and focus on continuous improvements both technically and functionally. Track and handle technical issues and follow up. Handle clarification where more than one domain/function/party is concerned plus topics that cannot be allocated to an engineering domain. Initiate mitigation of possible responsibility gaps in the project team. Collect and consolidate project risks and opportunities from engineering team, technical, but as well related to engineering work, information/data availability and assumptions taken. Define, coordinate take proactive actions to mitigate risks. Living Hitachi Energy s core values of safety and integrity, which means taking responsibility for your own actions while caring for your colleagues and the business. Your background: Minimum bachelor s degree (B. E/B. Tech) in electrical engineering. Minimum 6-7 years of work experience. Prior experience in SAS most preferred and Cyber Security exposure for SAS and PQS systems will be added advantage. Knowledge on communication protocols like Mod Bus, DNP3, IEC 101/104, TCP/IP, PRP, HSR, etc. Knowledge on RTU til 500 and Multiprog PLC (Preferred) and Strong knowledge on IEC 61850 (MMS and GOOSE) . Configuration of IEC61850 in different vendor relays (SEL, HITACHI, GE). System Integration of different product IED, meters and other substation devices into RTU/Gateway. Knowledge on closed loop control system Basic power system knowledge to understand the Sync Con operation and b asic Protection knowledge on IED s. Configuration of GPS, Ethernet switches and network components configurations. Hands on experience on System network preparation/topology for validation and testing along with test procedure. Exposure in commissioning support for HMI / SCADA. Knowledge of TD equipment, such as AC / DC switchgear circuit breakers, disconnectors, earthing switches, instrument transformers, power transformers, cables. HV MV substation engineering understanding and experience preferred. Technical risk and opportunity assessment and validation and take ownership for the project KPIs such as OTD, COPQ etc. Estimation of engineering effort for each project for costing at tender stage. Innovative ideas to reduce engineering effort and Proficiency in Auto CAD and Microsoft Vision. Knowledge of relevant international standards e. g. IEEE, IEC (preferably both). Knowledge and experience in international TD substation and power generation tendering and project engineering activities (technical commercial). Highly structured individual with strong technical and coordination skills and ability to think out-of-the-box and challenge traditional solutions. Comprehensive knowledge of- and ability to interact actively with interfacing disciplines in the organization (SCM, sales, project management). Works independently, applying established standards and dynamic and Proactive, willing to grow in the organization. Team player, ready to play the role in an international environment. High level of ownership and able to lead, guide and plan work individually and for the team. Strong communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams. Attention to detail and a commitment to delivering high-quality digital solutions. Preferentially have experience in Generators/Motors/Synchronous condenser Qualified individuals with a disability may request a reasonable accommodation if you are unable or limited in your ability to use or access the Hitachi Energy career site as a result of your disability. You may request reasonable accommodations by completing a general inquiry form on our website. Please include your contact information and specific details about your required accommodation to support you during the job application process. .

Position Overview The Tessent division seeks a highly motivated, creative, and energetic individual as Product Engineer, specializing in design-for-test (DFT) and test delivery at chip and system level. Tessent is the market and technology leader of automated tools for insertion of semiconductor design-for-test (DFT) structures, automatic test pattern generation (ATPG), embedded deterministic compression (EDT), memory built-in self-test (MBIST), logic built-in self-test (LBIST), diagnosis-driven yield analysis (DDYA), hierarchical DFT solutions such as Streaming Scan Network (SSN), and analog fault injection and test. This position presents a great opportunity to stay involved technically while getting exposure to marketing and interacting with sales. Responsibilities include but are not limited to: Define and characterize new product capabilities needed to meet customer requirements Work collaboratively with Tessent R&D to prototype, evaluate, and test new products and features within complex IC design flows Lead beta programs and support beta partners Drive product adoption and growth Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes Develop and review tool documentation such as user and reference manuals Work with customers as well as Siemens EDA stakeholders such as regional application engineers, global support engineers, and marketing Work through complex technical issues and independently create solutions and new methodologies Present complex principles in simple terms to broad audiences Collaborate and share information across team boundaries in written and spoken forms Some travel, domestic and international Job Qualifications The successful candidate will possess the following combination of education and work experience: BS degree (or equivalent) in Electrical Engineering, Computer Science, Computer Engineering, or related field is required Must have 5-8 years of experience, including 2+ years of experience in DFT for complex ASICs / SOCs, including some of the following areas: Automatic test pattern generation (ATPG), internal scan, embedded scan compression (EDT), packetized test delivery (SSN), memory built-in self-test (MBIST), logic built-in self-test (LBIST), IEEE 1687 IJTAG, analog design and simulation, hierarchical DFT implementation Must have industry experience with DFT tools, preferably Tessent tool suite Industry experience with inserting scan, running ATPG and debugging fault coverage Exposure to one or more adjacent IC disciplines such as the following a plus: o RTL coding and verification using Verilog/ SystemVerilog/VHDL o Synthesis and timing analysis o Place and route o Advanced IC packaging o DFT and test for embedded IP cores o Failure diagnosis o ATE use / test program development Candidate should be high energy, curious individual, self-motivated to learn new DFT methodologies and technologies Able to work as individual contributor and lead technical activities of junior engineers Strong problem-solving, reasoning and deduction skills and the ability to analyze and debug complex design and simulation issues Proficiency in LINUX and Windows environments Proficiency in a scripting language like TCL (preferred) or Python Excellent written and spoken English language communication skills Excellent organizational skills Location can be remote or hybrid in North America, or in-office at one the following Tessent locations: o Ottawa (Canada), Saskatoon (Canada), Wilsonville (Oregon), Fremont (California).

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. About the role: We are seeking a highly motivated and detail-oriented Application Support Engineer to join our dynamic, fast paced and growth-mindset team. In this role, you will be focused on supporting the Questa verification products, specifically in Verification IP line of products. In this position, you will be working closely with the product engineering team, field application engineers and customers. As an ASE, you will be solving some of our customers complex design, testbench and environment issues in the domain of functional verification. You will also be working closely on creating knowledge-based content and providing expertise on the Questa platform. You will work with multiple customers to understand their challenges and flow and be involved in technical presentations, training, evaluation and competitive benchmarking. You will part of the larger application support engineering organization and will be interfacing regularly with the North American and PACRIM teams. Minimum Qualifications: BS Electronic/Computer Engineering from an accredited institution Minimum of 2+ years of Digital Design/Verification experience Knowledge of VHDL or Verilog, or SystemVerilog RTL languages for ASIC or FPGA design Experience with ASIC or FPGA hardware design and implementation using RTL tool flows and methodologies Knowledge of Windows and Linux OS Self-motivated, flexible, self-disciplined, and comfortable in a dynamic, quick-moving environment. Strong interpersonal and communications skills with the ability to quickly establish rapport and credibility with our customers, sales, and product teams. Strong oral, and written communication, and presentation skills Excellent organizational and time management skills Preferred qualifications MS Electronic/Computer Engineering Knowledge of UVM and System Verilog for Verification Clock Domain Crossing (CDC), Static and Formal Verification Formal Applications Working knowledge of Working knowledge of Questa-Modelsim, VCS (Synopsys), NCSim (Cadence) or Aldec simulators. Knowledge of C/C++ programming languages Demonstrated proficiency with Object-Oriented Programming experience in test bench architecture and design Knowledge of scripting languages (e.g., Shell, Tcl, Perl, Python) Knowledge of CDC, low power and formal methodologies. Location Noida/ Bangalore Why us? Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Transform the Everyday #Li-EDA #LI-HYBRID

Looking for Siemens EDA ambassadors Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the Increasingly complex world of chip, board, and system design. Real trendsetters in every language. Before our software developers write even a single line of code, they have to understand what drives our customers. What is the environment and the user story based on? Implementation means trying, testing, and improving outcomes until a final solution emerges. Knowledge means exchange discussions with colleagues from all over the world. Join the team and enjoy the freedom to think in completely new categories. Be an integral part of a team that is developing comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400Gigabit Ethernet, DDR5, LPDDR5 and leading coherency protocols like CXL for use with Questa RTL simulation! We make real what matters. This is your role. Questa verification IP"™s help design teams find more bugs in less time than conventional simulation techniques. You will specify, implement, test and enhance these verification components for a wide range of end user applications. You will work on technologies involving SV, UVM, Assertions, Coverage, Test plan, BFM design, debug, and logger. You will work well with TMEs and Field AEs or directly with customers to deploy or resolve customer issues. We don"™t need superheroes, just super minds. We are seeking Electronics Engineers (B.Tech/M.Tech) or professionals from related fields, graduated from reputed institutes, who possess strong expertise in verification engineering and bring 1-4 years of hands-on experience to the table. You've sound knowledge of System Verilog for test bench with exposure to verification methodologies like UVM, VMM etc. You've intimate knowledge of one or more standard bus protocols, like PCIe, USB, SATA, NVMe, Flash, DIMM etc. We are phenomenal teammates, resilient and sincere, with a passion for learning new things and building our knowledge base in new areas! We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We are Siemens A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow! We offer a comprehensive reward package which includes a competitive basic salary, bonus scheme, generous holiday allowance, pension, and private healthcare. Transform the everyday! #LI-EDA #LI-Hybrid #DVT

Meta is looking for ASIC Engineer, Infra Silicon Enablement to join our dynamic team and embark on a rewarding career journey. you will be a key contributor to our engineering team, responsible for verifying the functionality and performance of ASIC designs. You will work on complex projects, ensuring that ASICs meet quality standards and specifications. Key Responsibilities : Verification Planning : Collaborate with design and architecture teams to create verification plans that outline the scope, goals, and strategies for ASIC verification. Testbench Development : Develop and maintain verification environments, including testbenches, models, and test sequences, using verification languages such as SystemVerilog and UVM. Test Case Design : Create and execute test cases to verify the functionality, performance, and compliance of ASIC designs with project specifications. Functional and Code Coverage : Ensure comprehensive functional coverage and code coverage metrics are met, identifying verification gaps and proposing solutions. Simulation and Emulation : Utilize simulation and emulation tools to run test scenarios, debug issues, and track the behavior of the ASIC design under different conditions. Debugging and Issue Resolution : Investigate and resolve issues identified during verification, working closely with design and software engineers to analyze and rectify problems. Performance Testing : Verify the performance of ASICs under various scenarios, such as speed, power, and reliability, and optimize performance parameters. Documentation : Maintain clear and organized documentation of verification plans, testbenches, test results, and issues identified. Verification Tools and Methodologies : Stay current with verification tools, methodologies, and industry best practices to enhance the verification process. Collaboration : Work collaboratively with cross-functional teams, including design, architecture, and software development, to ensure the success of ASIC projects.

About this opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Leadership Opportunity: Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Engage in an environment that champions innovation and critical thinking. Youll have the autonomy to explore advanced verification technologies alongside skilled experts. Global Influence: Contribute to projects that transform industries, advance digital economies, and enhance global communication, bridging gaps between people, systems, and information worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you perform at your best without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Driving Execution Be responsible for IP (Intellectual Property) development section, including design and verification at the subsystem, block, and/or sub-block levels. Act as an interface towards stakeholders and vendors. Ensure good collaboration with other teams both on-site and cross-site Team Recruiting and Development Recruit and develop team designers and verifiers Manage individual and team performance Develop a motivating, customer oriented and exciting work environment Broader Responsibilities Be an active contributor to the leadership teams of that global functional department that you collaborate with as well as the local IP development department Act as the chair and participate in steering groups inside organization or towards external suppliers Drive internal efficiency, cost effectiveness via new or alignment of existing ways of working, across all other design sections continuous improvements and automation Set goals, follow-up and strategically evolving section towards vison Required Qualifications: Bachelor s degree in electrical or computer engineering Proven leadership experience in all the following areas IP development team management (at least 3 years) building a motivated, innovative, empowered team coaching and mentoring written and verbal communications and presentations ability to build on cultural diversity and collaborate across teams, organizations and sites working with external suppliers agile ways of working and project management 8+ years experience as an individual contributor designer or verifier Additional Requirements: Experience with Cadence and Synopsys design and verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, thats why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 766880

MTS SILICON DESIGN ENGINEER THE ROLE: The focus of this role is to plan, build, and execute the Design of new and existing features for AMD s IPs, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ timezones . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Collaborate with architects, hardware engineers, and firmware engineers to understand the IP and/or new features to be designed Build design documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Estimate the time required to design the new features and QA checks Documentation of the Micro Architecture Specification Work with the verification team to review the test plan and make sure all features are covered Debug test failures to determine the root cause; work with Verification and firmware engineers to resolve design defects PREFERRED EXPERIENCE: Proficient in IP level ASIC RTL Design Proficient in debugging firmware and RTL code using simulation tools Proficient in working with Linux and Windows environment s Experienced with Verilog, System Verilog, C, and C++ Graphics pipeline knowledge Automating workflows in a distributed compute environment . Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process Strong background in the C++ language, preferably on Linux with exposure to Windows platform Good understanding and hands-on experience in the SystemVerilog language and UVM based verification Scripting language experience: Perl, Ruby, Makefile , shell preferred. Exposure to leadership or mentorship is an asset Desirable assets with prior exposure to DDR, SERDES or other multimedia solutions . ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Role & responsibilities Job Title: Mix Signal ASIC/IC Functional safety engineer/manager Job location: Bangalore Work mode: Hybrid Mode of employment: Permanent / Direct Company Payroll OVERVIEW: Seeks a dynamic and experienced Mix Signal ASIC/IC Functional Safety Engineer & Manager to join the Sensor Global Quality Engineering Center within its TE Sensors Quality Organization. This role focuses on ensuring the compliance to Functional Safety requirements of sensor products from project definition to production release for Automotive and Industrial & Transportation (ICT) markets. This role will engage with various Engineering Centers of Expertise and manufacturing plant globally. It is a strategic role to support TE Sensor Technology roadmap based in our growing Global Design Center Bangalore India. KEY RESPONSIBILITIES: Functional Safety for New Technology Development: Ensure that functional safety requirements are met from project definition to production launch according to TE stage gate procedure. Provide guidance to project stakeholders to adhere to ISO26262 standards Negotiate and mutually agree on required safety goals with customers (DAI) Contribute to the development of technical safety Concepts per ISO26262. Deliver Functional safety Work Products as per ISO26262 such as Safety Plan, HARA, FSR/C, TSR/C, FMEDA at hardware level (IP block/Gate). Review gate exits and release Functional Safety documentation (Safety Case) to enable production launch. YOU MUST HAVE Functional Safety Certification Experience: Minimum of 10 Years’ Experience in functional safety at hardware level SoC, ASIC, IC Successful release in production of project of at least ASIL C level . Proficiency with all Functional Safety tools from safety plan to safety case, including SPFM, LFM metrics Master FDMEA and FIT calculation Knowledge of Quality Standards: Familiarity with ISO 9001, AS 9100, IATF 16949 Strong English communication skills Customer & Leadership Engagement: Ensure efficient communication with customers and leadership team on functional safety related topics Anticipate and manage escalations effectively. Process & Continuous Improvement Management: Inspire a Zero-Defect mindset by ensuring data-driven problem-solving and improvement initiatives. Evaluate project outcomes, identify areas for improvement, and suggest enhancements to processes. WE VALUE Six Sigma Green Belt or Black Belt certification Experience in Cybersecurity ISO 27001 or ISO/SAE 21434 Experience participating to VDA audits, IATF audits EDUCATION Bachelor or Master in Engineering or related discipline Interested candidate please apply here. Also share your profile to chidananda@manpower.co.in; Best Regards, HR Team, Manpower Group Preferred candidate profile

We are seeking an exceptional Senior ASIC Verification Engineer to join our innovative semiconductor team. You will lead verification initiatives for complex ASIC designs and drive technical excellence across projects. About the Role : You will be responsible for developing advanced verification environments, leading cross-functional technical initiatives, and mentoring team members while ensuring the highest quality standards in our ASIC designs. What You'll Do : - Design and implement advanced System Verilog/UVM verification infrastructures - Lead verification planning and execution for complex ASIC projects - Develop comprehensive test strategies ensuring thorough design validation - Drive debug resolution through collaboration with cross-functional teams - Mentor and provide technical guidance to verification team members - Enhance and optimize verification methodologies - Own end-to-end SOC verification environments Required Skills & Experience : - BS/MS in Electrical/Computer Engineering - 2+ years of hands-on ASIC verification experience - Expert-level SystemVerilog, UVM, and object-oriented programming skills - Strong proficiency with industry tools like VCS, Xcelium, QuestaSim - Advanced debugging and problem-solving capabilities - Excellent communication and collaboration abilities - CLP and GLS - Python/Perl scripting expertise Nice to Have : - Experience with PCIe, DDR, USB, C2C - Knowledge of on-chip interconnects and processor subsystems - Background in formal verification methods - Prior experience on Emulators

About this opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Immerse yourself in an environment that champions innovation and critical thinking. Youll have the opportunity to explore advanced verification technologies alongside skilled experts. Global Impact: Contribute to projects with far-reaching impacts, transforming industries, advancing digital economies, and enhancing communication worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you excel professionally without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of verification engineers, providing mentorship and guidance to ensure efficient and reusable verification practices. Collect and address, team status and metrics. Take full responsibility for the verification strategies that the team has responsibility for. Define and implement UVM-based test environments. Break down requirements to create a Verification Strategy and develop and execute a Verification Plan. Develop, run, and debug test cases to ensure design quality. Continuously improve and optimize verification methodologies. Generate comprehensive documentation throughout the verification lifecycle. Collaborate closely with other verifiers, designers, and architects. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor s degree in electrical or computer engineering. 8+ years of industry experience in verification using SystemVerilog and UVM. Proven track record of leading verification test plan development in cross-site environments. Proficiency in/with: architecting and creating new grounds-up random and directed test environments and testcase strategies. formal verification for connectivity checks and using assertion-based VIPs. architecting and leading implementation of scoreboards, checkers, bus functional models SystemVerilog Assertions. Strong experience in low-power design verification. Additional Requirements: Experience with Cadence or Synopsys verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience in verification in one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson What happens once you apply Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, thats why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 766878

About this Opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Engage in an environment that champions innovation and critical thinking. Youll have the autonomy to explore advanced verification technologies alongside skilled experts. Global Influence: Contribute to projects that transform industries, advance digital economies, and enhance global communication, bridging gaps between people, systems, and information worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you perform at your best without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Lead a team of designer engineers, providing mentorship and guidance to ensure efficient and reusable design practices and IP. Collect and address, team status and metrics. Own and oversee the breakdown of requirements into actionable tasks for IPs and subsystems, ensuring alignment with project objectives. Review work done by the team, ensuring quality and adherence to design specifications. Take responsibility for deliverables, prioritizing work to ensuring successful completion in time. Continuously enhance and optimize design methodologies and processes, facilitating innovation and efficiency. Collaborate closely with IP System Architects and cross-functional teams to ensure requirements are effectively met. Work closely with the verification lead to support review and refinement of verification plans. Develop competence in the technical domain. Foster cross-team collaboration to ensure seamless project delivery and integration. Required Qualifications: Bachelor s degree in electrical or computer engineering. 8+ years of industry experience in ASIC design. Proven track record leading IP development and of successful cross-team and cross-site collaboration. Proficiency in/with: Understanding of ASIC technology, design environments, and methodologies. SystemVerilog RTL static sign-off tools such as SpyGlass. Scripting languages like TCL, Python, or similar. SystemVerilog Assertions. Strong Experience with in low-power design, including specifying power intent using UPF or similar standards. Knowledge of Design for Test methodologies. Additional Requirements: Experience with Cadence and Synopsys front-end and middle-end design suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson What happens once you apply Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, thats why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 766876

About this opportunity We are starting a new Silicon R&D center in Bangalore. Join our team as we pioneer the IPs that power the digital ASICs of tomorrows mobile standards. Ericsson System on a Chip (SoC) devices are custom-made for mobile networks and spans across the Ericsson Radio System - RAN Compute, Radio and Transport - to enable communication service providers to surpass the expectations of their end-customers. At our state-of-the-art design centers, we dont just follow industry trends we set them. By leveraging cutting-edge tools and methodologies, we lead innovation in the telecommunications sector. As a valued team member, youll play a pivotal role in shaping the future of global connectivity, contributing to the advancement of 5G and 6G technologies. As part of our global R&D organization, youll collaborate with talented teams across Sweden, the US, and beyond. We are committed to fostering a collaborative and innovative work environment that encourages creativity and teamwork. What you will do Leadership Opportunity: Take charge of delivering high-impact ASIC IP solutions, ensuring alignment with broader project goals and requirements. Creative Freedom: Engage in an environment that champions innovation and critical thinking. Youll have the autonomy to explore advanced verification technologies alongside skilled experts. Global Influence: Contribute to projects that transform industries, advance digital economies, and enhance global communication, bridging gaps between people, systems, and information worldwide. Work-Life Balance: We prioritize the well-being of our team members, offering a balanced work-life environment to help you perform at your best without compromising your personal life. Professional Growth: Engage in continuous learning opportunities, tackle exciting challenges, and collaborate with brilliant minds in a supportive and forward-thinking atmosphere. An international work environment with opportunities for professional growth and development. A collaborative and inclusive culture that values diversity and innovation. A competitive compensation and benefits package. You will bring Key Responsibilities: Driving Execution Be responsible for IP (Intellectual Property) development section, including design and verification at the subsystem, block, and/or sub-block levels. Act as an interface towards stakeholders and vendors. Ensure good collaboration with other teams both on-site and cross-site Team Recruiting and Development Recruit and develop team designers and verifiers Manage individual and team performance Develop a motivating, customer oriented and exciting work environment Broader Responsibilities Be an active contributor to the leadership teams of that global functional department that you collaborate with as well as the local IP development department Act as the chair and participate in steering groups inside organization or towards external suppliers Drive internal efficiency, cost effectiveness via new or alignment of existing ways of working, across all other design sections continuous improvements and automation Set goals, follow-up and strategically evolving section towards vison Required Qualifications: Bachelor s degree in electrical or computer engineering Proven leadership experience in all the following areas IP development team management (at least 3 years) building a motivated, innovative, empowered team coaching and mentoring written and verbal communications and presentations ability to build on cultural diversity and collaborate across teams, organizations and sites working with external suppliers agile ways of working and project management 8+ years experience as an individual contributor designer or verifier Additional Requirements: Experience with Cadence and Synopsys design and verification suites. Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results. Specifically, experienced at communicating and meeting expectations within and across teams in an agile environment. High attention to detail and commitment to quality. Strong focus on meeting project deadlines and deliverables. Proficient in English, with strong communication skills. Preferred Skills: Understanding of radio access systems and their components. Working knowledge of systems for continuous integration (e.g., Jenkins), simulation and analysis environments (e.g., Simscope), issue-tracking (e.g., Jira). Experience designing one or more of the following hardware domains: AMBA-based designs especially AXI and CHI. ARM-based real-time microcontroller systems including their control and interface peripherals. Wireless infrastructure specific protocols and interfaces and protocols. Implementation of hardware-based digital signal processing systems (filters, adaptation, etc.) Why join Ericsson What happens once you apply Click Here to find all you need to know about what our typical hiring process looks like. Encouraging a diverse and inclusive organization is core to our values at Ericsson, thats why we champion it in everything we do. We truly believe that by collaborating with people with different experiences we drive innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team. Ericsson is proud to be an Equal Opportunity Employer. learn more. Primary country and city: India (IN) || Bangalore Req ID: 766880

You are responsible for ensuring that you have properly trained people and that their needs are addressed so they can focus on their jobs. You will ensure Amazon policies - including attendance tracking - are implemented and administered fairly and consistently. This includes motivating, coaching, reporting, and providing feedback of associates performance - including productivity, quality, and safety - as a means for achieving or exceeding Amazon expectations. The Team lead will address discipline and/or performance issues for LM Associates including up to termination. In addition, you will work in partnership with third party delivery providers to ensure Amazon standards are being met in accordance to service contracts. Amazon is seeking Team leads for our GSF FC operations team. Amazon is one of the most recognizable brand names in the world and we distribute millions of products each year to our loyal customers. Key job responsibilities Were seeking a Team lead for our LM operations. In this role, you will be responsible for: - Managing, on a daily basis, end to end operations for either one large site or a combination of small sites. Executing inbound and outbound operations - Meeting customer facing metrics, while maintaining cost targets and upholding safety and morale of the team reporting to you. - Driving performance management of your team members. Preparing and implementing training and development plans for associates. - Continuously improve the delivery process and attain a sustained level of delivery performance improvement. - Conducting 4M and 5S audits for the delivery station on a daily basis. - Stand-in for Area Manager. Ability to manage day and night shifts. asic qualifications 1+ years of customer-facing environment, warehousing, logistics or manufacturing experience Bachelors degree Speak, write, and read fluently in English Experience with Microsoft Office products and applications Experience with Excel Experience in customer-facing environment, warehousing, logistics or manufacturing

Are you looking for a unique opportunity to be a part of something greatWant to join a 20,000-member team that works on the technology that powers the world around usLooking for an atmosphere of trust, empowerment, respect, diversity, and communicationHow about an opportunity to own a piece of a multi-billion dollar (with a B!) global organizationWe offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: You will be working with our Design team from Hyderabad to develop STA tests. These tests are intended to catch timing violations at block level /SoC. In this role you will have an opportunity to understand in depth FPGA/SoC silicon architectures at block level as well as full chip level, to develop constraints and, debug the setup, perform static timing analysis and debug Timing violations. Interact with Physical design Teams and propose fixes for the timing violations. You will work closely with design engineers, custom engineers and layout engineers to ensure FPGA division deploys new products with the highest quality and shortest time to market. Skills will be developed to work on multiple projects supporting key functions within the organization. Good communication and presentation skills are required. Requirements/Qualifications: Perform Static Timing Analysis ASIC blocks and full chip with industry lead EDA tools like prime-time / Tempus, understand different interfaces, ASIC blocks and work on constraints and develop different STA modes at full chip level. Track post layout netlist releases spef extractions and integrate the new releases into full chip STA environment. Perform verification processes with modelling and simulation using industry standard simulators Maintain technical expertise and provide training to juniors Contribute to cross group communication to work towards standardization and group success Proactively solicit input from Standards, CAD, modelling and layout to ensure the design quality Drive innovation into the future generation with dynamic work environment Previous strong experience in STA and making timing constrains Experience in taking an industrial specification and implementing the respective IP Good understanding on timing/area/power/complexity trade-offs on complex interface design Familiar with IP level verification and strong RTL debugging capabilities Experience in frontend implementation tasks such as synthesis and logic equivalence Experience in large scale mix signal circuitry design including logic implementation/verification, timing analysis/optimization an advantage Excellent problem-solving and analytical skills A self-motivated, enthusiastic team player who enjoys working with others Good communication skills with the ability to convey complex technical concepts to other design peers in verbal and written form. Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

At Broadridge, weve built a culture where the highest goal is to empower others to accomplish more. If you re passionate about developing your career, while helping others along the way, come join the Broadridge team. Requirements / Qualifications: 7 to 10 years of experience in the OTC derivatives regulatory reporting domain. Proven working experience with one or more regulatory regimes, including EMIR, MiFID, ASIC, MAS, HKMA, CFTC, CSA, and/or SEC regulatory regimes. Strong proficiency in JavaScript, XML, and XPath. Excellent communication skills, with the ability to articulate complex technical concepts to non-technical stakeholders. Exceptional stakeholder management skills, with a track record of building and maintaining strong relationships with diverse groups. Experience working in an agile development model, with the ability to adapt to a fast-paced and dynamic environment. Strong problem-solving skills and attention to detail. Working knowledge of various tools (Git, Maven/Gradle, Grunt, Jenkins, Docker) Qualification: Bachelor s degree in engineering (BE/B. Tech) or equivalent, preferably in Computer Science. Key Responsibilities: Oversee and manage the end-to-end regulatory reporting process for OTC derivatives across various global jurisdictions. Ensure compliance with one or more regulatory regimes, including EMIR, MiFID, ASIC, MAS, HKMA, CFTC, CSA, and SEC. Develop, maintain, and optimize JavaScript, XML, and XPath code to support regulatory reporting requirements. Communicate effectively with internal and external stakeholders to ensure alignment on regulatory requirements and project deliverables. Manage stakeholder expectations and foster strong relationships to facilitate smooth regulatory operations. Collaborate with cross-functional teams in an agile environment to drive efficient project delivery and continuous improvement. Stay informed of changes and updates in global regulatory frameworks to ensure ongoing compliance and risk mitigation. Nice to have: . Knowledge of AWS basics. Shift Timings: 1 PM to 10 PM IST We are dedicated to fostering a collaborative, engaging, and inclusive environment and are committed to providing a workplace that empowers associates to be authentic and bring their best to work. We believe that associates do their best when they feel safe, understood, and valued, and we work diligently and collaboratively to ensure Broadridge is a company and ultimately a community that recognizes and celebrates everyone s unique perspective.

External job description Amazon Lab126 is an inventive research and development company that designs and engineer s high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced ground-breaking devices like Fire tablets, Fire TV and Amazon Echo. Work hard. Have fun. Make history. We are looking for an Embedded Software Development Engineer- to help design, develop, integrate our next generation devices. In this role you will work with customers, system architects, program managers and hardware engineers to design, implement, troubleshoot, fix kernel drivers, Audio SW, BSP for our next generation devices. You will be responsible for the development of real-time embedded firmware and embedded Linux software that implements audio features. If you have one or more of the below skills, then this job is for you: - Expertise in ALSA / Pulse Audio - Exposure to Audio software stack on Android/QNX/proprietary OS including Audio Flinger, Audio HAL - Exposure to ARM, DSP architectures - Exposure to Dolby MS12 / DTS/ MPEG-TS - Exposure to Audio/Video Sync - Exposure to STB / DTV audio systems - Working knowledge of Oscilloscope, Logic Analyzer, and Audio Tools including Audio Precision In this role, you will: - Design audio features that work across various embedded products - Develop audio software that runs on ARM/DSP using Bare metal, Linux and other high level OSes - Optimization and porting audio and speech processing algorithms - Integration of vendor hardware and software stacks - Tune hardware for highest audio performance and lowest noise - Be passionate, responsive, flexible and able to succeed within an open collaborative peer environment - Be able and willing to multi-task and learn new technologies quickly About the team Amazon Lab126 is an inventive research and development company that designs and engineer s high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced ground-breaking devices like Fire tablets, Fire TV and Amazon Echo. - 3+ years of non-internship professional software development experience - 2+ years of non-internship design or architecture (design patterns, reliability and scaling) of new and existing systems experience - Experience programming with at least one software programming language - Basic qualifications - Bachelor s degree in Computer Science or related fields - 3+ years as Application Engineering experience - 2+ years in embedded development preferably ARM systems - 5+ years programming experience in C/C++ - Linux kernel and application development, and focus on stability, efficiency, and performance. - Knowledge of Android platform and development environment. - System scripting and building environment - Experience with embedded system concepts and hardware interfaces, such as, JTAG, UART, SPI, I2C, ROM, Microcode, Custom ASIC/FPGAs x86 and ARM chipset and firmware security (TPM, UEFI, TrustZone, Secure/Measured Boot, JTAG, PCIe) - 3+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience - Bachelors degree in computer science or equivalent - Preferred qualifications - Masters or PhD - Experience supporting shipping Android and Linux based IOT devices