776 Asic Jobs - Page 11

Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 8 years of experience in high-performance design, multi-power domains with clocking. Experience in multiple SoCs with silicon success. Experience with Verilog or System Verilog language. Preferred qualifications: Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation. Experience with chip design flow and an understanding of cross-domain involving DV/DFT/Physical Design/Software. Knowledge of one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead a team of ASIC RTL engineers on sub-system and chip-level Integration activities including plan tasks, hold code and design reviews, code development of complex features. Interact closely with architecture team and develop implementation (e.g., microarchitecture and coding) strategies to meet quality, schedule and performance, power, and area (PPA) for sub-system/chip-level integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Minimum qualifications: Bachelor's degree or equivalent practical experience. 7 years of experience in business development, partnerships, management consulting, or investment banking, in the Consumer Electronics, Auto, OEMs, Telecom, E-Commerce/Retail, Apps, Ads, Gaming, or Technology industries. Experience working with C-level executives and cross-functionally across all levels of management. Experience managing agreements or partnerships. Preferred qualifications: 8 years or more of semiconductor experience in the EDA/3PIP/ASIC partner management. Experience in driving EDA/3PIP/ASIC partnership with cross-functional deliverables, with the ability to engage and deliver results. Knowledge of EDA design flows and 3PIP ecosystem. Knowledge of product and technology development processes and strategies, and EDA and IP platforms. Excellent collaboration skills across multiple business units to align and execute deliverables. About the job Google's line of products and services to our clients never stops growing. The Partnerships Development team is responsible for seeking and exploring new opportunities with Google's partners. Equipped with your business acumen and extensive product knowledge, you are right on the front line of interacting with our partners, and helping them find ways to grow using Google's newest product offerings. Your knowledge of relevant verticals and relationships with key industry players will help shape our great applications and content for products such as YouTube, Google TV and Commerce. The Custom Silicon Sourcing team plays a crucial role in the development of Pixel products. The team is responsible for sourcing third-party IP and EDA tools and managing relationships with the suppliers. The goal is to ensure the delivery of committed SoC and chip components. The Global Partnerships organization is responsible for exploring new opportunities with Google's partners. Google s Global Partnerships team works with a wide range of partners to bring the best of Google to power their business. The Global Partnerships team supports Google s own Product teams with essential partnerships to help Google s user experiences in advertising, Search, Assistant, Maps, Travel, Shopping, Payments and more. Teams create product-enabling partnerships, go-to-market strategies and incubate business growth for a variety of products. Responsibilities Drive EDA and 3PIP partner engagements. Manage contract process from start to finish including negotiating agreements, financial terms, timelines, amendments and SoWs. Manage suppliers on an ongoing basis with agreed upon KPIs. Evaluate new supplier engagement opportunities and provide recommendations to the management team, communicate and collaborate with a broad range of cross-functional constituents (e.g., product, engineering, marketing, finance, sales, legal). Build, maintain and evolve relationships with a variety of internal and external stakeholders, partner with key stakeholders and provide insights on product plans and roadmap availability to engineers and program managers.

Minimum qualifications: Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience. 5 years of experience in DFT specification definition architecture and insertion. 3 years of experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent). Experience with ASIC DFT synthesis, STA, simulation, and verification flow. Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, and debug of silicon issues, etc.). Preferred qualifications: Master's degree in Electrical Engineering, or a related field. Experience in IP integration (e.g., memories, test controllers, TAP, and MBIST). Experience in SoC cycles, including silicon bring-up and silicon debug activities. Experience in fault modeling. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design, insert, and verify the DFT logic. You will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO. Demonstrate ownership from DFT logic, pre-silicon verification, to co-work with test engineers post silicon. Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks. Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces. Document DFT architecture and test sequences, including boot-up sequence associated with test pins. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support post-silicon test team.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 10 years of work experience in RTL design. Experience with ASIC design methodologies for clock domain checks and reset checks. Experience in RTL coding using System Verilog/Verilog. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science. Experience in area, power and performance design optimization. Experience implementing Machine Learning Accelerators, Camera ISP image processing IP, or other multimedia IPs such as Display or Video Codec. Experience in scripting languages, C/C++ programming and software design skills. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Provide microarchitecture definition for Core IP hardware designs and subsystem/ASIC top-level integration. Define and develop Register-Transfer Level (RTL) implementations that meet engaged power, performance and area goals. Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the sub-system and chip-level verification. Create tools/scripts to automate tasks and track progress. Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 5 years of experience in DFT/DFD flows and methodologies. Experience working with fault modeling, test standards and industry DFT/DFD/ATPG tools and with Application-Specific Integrated Circuits (ASIC) DFT, synthesis, simulation and verification flow. Experience developing DFT specifications and driving DFT architecture. Preferred qualifications: Experience using EDA tools like Design Compiler, DFT Max, FastScan, TetraMax, Tessent, SpyGlass, Modus, Tessent, and TestKompress, VCS, NC-Verilog, and waveform debugging. Experience with User Defined Fault Models (UDFM) generation like Cell-Aware and other fault models like GDD, SDD. Experience with STA constraints development and analysis for DFT modes and SDF simulations. Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST and JTAG related issues Knowledge of various Test standards (such as IEEE 1149.10, 1149.6, 1500, 1687) and test formats (such as BSDL, ICL, PDL, STIL, CTL). About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define Design for Excellence (DFX) specifications and develop flows and methodologies for new technology node implementation. Implement/Integrate and verify Design for Testing (DFT) logic, for example, memory built-in self test (MBIST), scan chains, DFT compression, Test Access Port (TAP) controller, BSCN, iJTAG instrumentation, functional BIST, logic BIST and eFuse logic on test chips. Work with silicon engineering team to create test plans and generate test patterns. Participate in post-silicon activity like bring up, diagnostics and characterization. Work with EDA and IP vendors to incorporate state-of-the-art DFT/DFD/DFY flows and methodologies. Provide support to internal teams.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience. 3 years of experience with Formal Verification (e.g., sequential equivalence checking, Security Path verification, connectivity, low power and Formal property verification). Experience with programming languages (e.g., Python/Perl and TCL). Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or a related field. Experience with regression setup and management. Experience with formal sign-offs of industry Application-specific integrated circuit (ASIC) designs. Knowledge of formal verification applications such as sequential equivalence checking, and connectivity checking and data-path verification. Knowledge of formal methodology and formal abstraction techniques. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Plan the formal verification strategy, create the properties and constraints for digital design blocks. Use different formal verification applications to resolve multiple tests like clock-gating verification, low power, connectivity and security path verification. Utilize formal property verification tools combined with formal verification closure techniques to verify properties. Contribute improvements to methodologies and scripting to enhance formal verification results.

Minimum qualifications: Bachelor's degree in Mechanical Engineering, Electrical Engineering, Industrial Engineering or equivalent practical experience. 3 years of experience with standard GPU workloads like Manhattan/3DMark. Experience with GPU architecture and AMBA Bus protocols like AHB/AXI/ACE. Preferred qualifications: Master's degree or PhD in Electrical Engineering or Computer Science, or a related field. Experience with performance verification of ASICs and ASIC components. Experience with verification of low power techniques. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Be part of a team to verify complex digital design blocks (e.g., CPU, Graphics Processing Unit (GPU), Image processor) by understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience in ASIC Chip Design. 5 years of experience with hardware electronic design automation tools. Experience in Python/C++ programming. Experience in writing code and design practices. Preferred qualifications: Experience planning and deploying new tools and flows to users. Experience in AI/ML methods for ASIC development. Knowledge of chip design processes such as verification, design, and implementation. Ability to present and explain novel methods to users. Strong programming/software skills like C/C++/Python. About the job In this role, you ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will help deliver products that have a substantive impact on the technical infrastructure. You will provide leadership in an innovative and fast-paced environment with a focus on infrastructure for chip design. You'll also lead complex technical projects from the concept/planning stage through execution and closure. You will enable the wider team to deliver designs of different application areas, including ML/AI acceleration by developing tools relying on AI/ML techniques. You will lead end-to-end chip design process improvement projects. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Responsibilities Partner with the Google Deepmind team to incorporate AI/ML techniques in chip design methodology and integrate into development flow. Partner with Chip Project teams to influence and standardize methodology across projects and functional areas (e.g., Design, Verification, Emulation, and other front end domain). Propose, design, and implement software automation addressing bottlenecks in today's ASIC and SoC EDA flow. Perform or guide technical evaluations of tools and their AI capabilities, and drive planning for possible deployment. Lead the development of internal software tools and automation efforts, participate in design reviews, and engage in influencing and scheduling trade-off discussions. Collaborate to identify and create strategic opportunities for improved chip design across Google. Work directly with a hardware team on projects-prototype and deploy tools to make a positive impact on Google's chip hardware development process.

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience 4 years of experience with digital design in ASIC. Experience in RTL design utilizing Verilog/System Verilog with ARM-based SoCs, interconnects, and ASIC methodology. Experience in a scripting language, such as Python or Perl. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Science, or equivalent practical experience. Experience with AMBA (Advanced Microcontroller Bus Architecture) protocols. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Experience with methodologies for low power estimation, timing closure, synthesis. Experience with a scripting language like Python. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details including interface protocols, block diagrams and data flow. Perform RTL quality checks such as Lint, CDC, and Synthesis checks. Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up. Collaborate within a team to develop and deliver optimized interconnect blocks and subsystems. Coordinate with architecture, design verification, and implementation teams to ensure specification adherence and Communicate and work with multi-disciplinary and multi-site teams.

Minimum qualifications: Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design integration. Experience in Verilog or Systemverilog coding. Experience in High performance design, Multi power domains with clocking of multiple SoCs with silicon. Preferred qualifications: Master s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. Experience with ASIC design methodologies for front quality checks including Lint, CDC/RDC, Synthesis, DFT ATPG/Memory BIST, UPF and Low Power Optimization/Estimation. Experience with chip design flow and understanding of cross domain involving DV DFT/Physical Design/software. Knowledge in one or more of these areas: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, Pin-muxing. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Lead a team of ASIC RTL engineers on Sub-system and chip-level Integration activities including planning tasks, hold code and design reviews, code development of features. Interact closely with architecture team and develop implementation (microarchitecture and coding) strategies to meet quality, schedule and PPA for Sub-system/chip-level integration. Work closely with the cross-functional team of Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process.

Minimum qualifications: Bachelor s degree in Electrical/Computer Engineering or equivalent practical experience. 2 years of experience with RTL design using Verilog/System Verilog and microarchitecture. Experience in ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master s degree in Electrical/Computer Engineering. Experience with methodologies for RTL quality checks (e.g., Lint, CDC, RDC). Experience with methodologies for low power estimation, timing closure, synthesis. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of our platform IP team, you will be a part of a team that designs foundation and chassis IPs (NoC, Clock, Debug, IPC, MMU and other peripherals) for Pixel SoCs. You will collaborate with members of architecture, software, verification, power, timing, synthesis, etc. to specify and deliver quality RTL. You will solve technical problems with innovative micro-architecture, low power design methodology and evaluate design options with complexity, performance and power. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Define microarchitecture details such as interface protocol, block diagram, data flow, pipelines, etc. Perform RTL development (SystemVerilog), debug functional/performance simulations. Perform RTL quality checks including Lint, CDC, Synthesis, UPF checks. Participate in synthesis, timing/power estimation, and FPGA/silicon bring-up. Communicate and work with multi-disciplined and multi-site teams.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: GPU Design and micro-Architect who will work across functions like GPU architecture and Systems in design and micro-architecture of the next generation GPU features. Work very closely with Architecture teams to come up with micro-architecture and hardware specification for features Design and RTL ownership Work very closely with Design Verification teams to review test plans and sign off the validation of all design features across products Work closely with physical design teams to achieve the right power, performance and area metrics for the GPU blocks Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

We are now looking for a SOC Verification Engineer. NVIDIA is pioneer in building the worlds fastest highly-parallel processing systems for deep-learning, high-performance computing, and automotive applications. We are seeking a passionate, innovative, and highly motivated verification engineer to work on the complex CPU-GPU memory systems. What You ll Be Doing: Responsible for defining test plans & architecting testbenches for verification of the CPU/GPU memory subsystem. Verify micro-architecture/architecture features at subsystem or full chip testbenches. Work with architects, designers, and pre-silicon verification teams to accomplish your tasks. Build reusable bus functional models, traffic generators, monitors, checkers and scoreboards following coverage driven verification methodology. Developing innovative tools/automation to stress the design under test and cover the verification space. What We Need To See: BS or MS in electrical engineering or computer engineering 3+ years of experience working on ASIC development Exposure to micro-architecture of high-performance CPU or GPU memory subsystems Experience with industry standard verification methodologies Ways To Stand Out From The Crowd: Exposure to coherency protocols, cache verification and network-on-chip (NOC) Exposure to CPU memory subsystem and knowledge of AMBA/CHI protocols. Innovative mindset, ability to use automation/tools to cover vast verification spaces. Good communication skills and ability collaborate across multiple teams. With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world s most desirable employers. We have some of the most brilliant and talented people in the world working for us and, due to unprecedented growth, our elite engineering teams are rapidly growing. If youre a creative and self-reliant engineer with a real passion for technology, we want to hear from you. #LI-Hybrid

Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe , CXL , and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com . Title : Lead Software QA Engineer, A stera Labs, Bengaluru, India. Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. For more information about Astera Labs, see www.AsteraLabs.com . Key Responsibilities Lead and scale high-performing Firmware QA teams in India. Own the full software development lifecycle, from architecture and design to testing and deployment. Develop and implement software development and QA best practices, including test automation, process monitoring, and quality metrics. Collaborate cross-functionally with hardware, product, and customer-facing teams to define and deliver robust software solutions. Communicate regularly with global customers including Hyperscalers and Tier 1 OEMs to provide updates, support audits, and resolve escalations. Help build large-scale test farms and automation frameworks. Mentor, coach, and grow engineering talent through effective performance management and career development. Drive continuous improvement in team efficiency, quality, and delivery. Basic Qualifications : Bachelor s degree in Electrical Engineering or Computer Science (Master s or PhD preferred). 8+ years of experience in firmware software QA. Proven ability to build and manage complete software development teams in India. Expertise in Agile software development methodologies. Deep understanding of software test methodologies, automation, and management tools. Excellent communication and interpersonal skills, especially in customer-facing roles. Strong planning, prioritization, and project management skills in fast-paced environments. Entrepreneurial, proactive mindset with a passion for innovation and customer success. Required Experience : Proficiency and demonstrated experience with ASIC based hardware systems and SQA mechanisms. Knowledge of PCIE is required. Building and scaling technical teams with a focus on collaboration and innovation. Proficient in C and Python programming. Expert-level user of Git, Jira, and Confluence. Experience defining and tracking software KPIs and quality metrics. Development and implementation of firmware design and test plans. Knowledge of hardware/software architecture and its impact on system performance. Preferred Experience : Experience with Security Development Lifecycle and FIPS certification. Familiarity with cryptographic protocols and implementation. Knowledge of memory (DDR4/DDR5/HB) technologies. Deployment of AI based SQA and FW development We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the Silicon Design team at AMD you will help create leading edge IP s used in a wide variety of applications. The focus of this role is to lead, design, plan and execute RTL design for NoC (Network on Chip). THE PERSON: Successful candidate will have an SOC/ASIC Design background, would have participated in several silicon design projects with increasing level of scope/responsibilities and has a history of achieving results through effective execution . KEY RESPONSIBILITIES: Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements. Collaborate with architecture and hardware teams to understand the requirements. Help lead and mentor other engineers to achieve project goals and organizational growth. Work with verification and physical design teams to achieve high quality design and successful tape outs. Design and implement logic functions that enable efficient test and debug. Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features. Implement automation to increase design team efficiency. PREFERRED EXPERIENCE: Must have proven track record of ASIC design on several production tape-outs. Experience in Designing RTL block for an SOC. Experience in integrating ASIC IP into an SOC. Experience with Arm architecture and APB, AXI, CHI protocols. Experience with synthesis, static timing analysis & optimizations. Experience writing timing constraints and exceptions. Experience with automation using scripting techniques such as PERL, Python or Tcl Ability to develop clear and concise engineering documentation. Ability to organize and present complex technical information. Strong verbal and written communication skills. Exhibit strong ownership of tasks and responsibilities. ACADEMIC CREDENTIALS: Bachelor s or master s degree in computer engineering/Electrical Engineering #LI-PS1

Amazon Lab126 is an inventive research and development company that designs and engineers high-profile devices like the Kindle family of products. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc. Since then, we have worked to produce best-selling e-readers and tablets, as well as new inventions like Echo line of products, Fire TV and Fire phone. What will you help us create? As a Senior Validation engineer in Amazon Lab126, you will have a leadership role in defining and delivering validation methodology for pre-silicon; emulation and hardware prototyping platforms, as well as post silicon efforts for custom multi-media SoCs targeted for next-generation Amazon consumer devices. You will engage with the Silicon and System Architecture, Product Planning, and Technology Platform teams to validate hardware and software for these custom SoCs. You will be responsible for understanding the architecture of the SoCs and its software stacks, writing detailed testplans for each of its subsystems, and initially implementing those testplans on emulation and prototyping platforms. You will extend these test suites to validate silicon. In this role you will: Contribute to building and developing a world-class emulation and validation team Deliver best in class work flows to develop and implement validation strategies for SoC emulation prototyping and post silicon. Attend and run cross-functional engineering meetings Dive into and take ownership of crucial execution issues Build design processes to continuously improve performance and quality Drive analysis to determine performance targets Bachelors in Electrical or Computer Engineering/Computer Science 10+ years in working on emulation/prototyping and validation of ASIC/SoC products Excellent analytical and problem solving skills Expertise in protocols/interfaces such as USB, PCI, I2C, SPI, CSI, DSI, I2S, DDR, Flash etc. Expertise in building robust testplans that ratify system features. Expertise in silicon bring up involving complex SoC products Expertise in Firmware/Linux Understanding of emulation platforms like Zebu/Palladium/Veloce Understanding of prototyping platforms like HAPs/Proteum etc. Masters in Electrical or Computer Engineering/Computer Science Experience with multi-media SoCs in any of the following domains: audio, speech, computer vision, machine learning, multi-media. Experience developing methodology for emulation, prototyping, and silicon validations Demonstrated success delivering high quality, innovative products based on rapidly evolving technologies

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Brief description about the Job. Job Location : Electronic -City, Phase II,Bangalore. Who you are Leading the design, development, andimplementation of high speed boards for servers, including processors, memory,storage, and network interfaces. Experience in full HDLC like schematic design, PCB layout, SI-PI, mechanicaland software integration. Experience in High Speed board design with interfaces like PCIe 5.0, LPDDR4/5,SSD s,M.2,U.2 NVMe, SATA, CXL, USB, Ethernet. Etc Understanding customer requirements, translating them into technicalspecifications, and working with other departments to ensure a robust andscalable solution. Who you are 6-8 years of experience Hands on experience in server class ofboard design with AMD or Intel GPU s, with high speed interfaces like PCIe5.0,LPDDR4/5, SSD s,M.2,U.2 NVMe, SATA, CXL, USB, Ethernet. etc. Hands on experience in HardwareDevelopment Life Cycle like design, bringup, testing and validation of boards,functional testing, trouble shooting, debugging and Failure analysis. Experience in at least one completeproject starting from the high-level design to the final validation. Should be able to independently handleschematic design, design analysis and review coordination with peer designers. Mentoring and guiding a team of hardwareengineers, providing technical expertise and support, and ensuring team membersadhere to industry standards. Collaboratingwith cross function team in managing PCB layout, SI-PI simulations, Softwaredevelopment, mechanical, thermal, silicon IP Validation, BIOS and DriverDevelopment/QA etc. and other stakeholders to ensure a cohesive and efficientsystem design. Experience with relevant design tools like Altium and orcad. Hand on experience in using instruments like high speed Oscilloscopes, DMM,electronic loads etc. Should be able to develop the board bring-up plan, beable to identify the test equipment required and execute independently. Experience in preparing and reviewing hardware design documentation and issueinvestigation reports. Good Communication and interpersonalskills Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. . Tessolve is not responsible for any lossesincurred due to such fraudulent activities

: 2025-06-18 Country: India Location: North Gate Business Park Sy.No 2/1, and Sy.No 2/2, KIAL Road, Venkatala Village, Chowdeshwari Layout, Yelahanka, Bangalore, Karnataka 560064 Overview: Hardware Product Design activities for Power and Controls SBU (EPS and EACS Businesses) needs a proficient Analog and Digital Designer who has expertise designing for DO-160 and testing and corelating the same and also has strong understanding of EMI/EMC, signal integrity, and hardware design principles who can support in GETC- EDTC qualification activities In this role the Principal Engineer independently own different phase of Hardware Development cycle of Airborne Electronic Hardware development. Mentoring the team and owning HW development cycle as per RTCA DO-254 / EUROCAE ED-80, Design Assurance Guidance for Airborne Electronic Hardware. Position: Principal Engineer (P4) Primary Responsibilities: Expert in Design, Analysis, Testing and Qualification of mixed signal Hardware Systems. Expert in reviewing the deliverables and provide technical guidance to the team. Understanding of DO-254 (Design Assurance Guidance for Airborne Electronic Hardware) process for hardware life cycle. Strong technical capability to lead Hardware Life Cycle Activities (Requirements development, Detailed Design and Specification, Test Plan and Procedure, Verification and Certification documents). Perform board level thermal, signal/power integrity, EMI/EMC simulation, to refine design before the prototype phase, ensuring the highest quality of output. Strong capability to work on technologically complex system with risk taking abilities, championing of new ideas and lead the product development from concepts to reality. In depth understanding of FPGA hardware design and verification for Aerospace Products Proficient in usage of DOORS for requirement management. Knowledge of PCB Layout guidelines to meet EMI/EMC tests, provides board layout guidelines to PCB designers. Board level and system level testing Experience. Designs innovative solutions to complex problems Ability to break-down activities in sub-tasks and milestones to adhere to timelines and to respect budget constraints. Work closely with cross-functional teams to ensure seamless integration of hardware components with other system parts, facilitating a cohesive and functional product. Should have excellent troubleshooting skills on electrical/electronic systems to find root cause and resolve the issues. Lead the evaluation, troubleshooting, and debugging of hardware prototypes. Identify the root causes of failures and implement corrective actions. Oversee the creation and maintenance of technical documentation. Release and sustain system board designs in TeamCenter. Experience in Electrical CAD tools (Pspice, Allegro, LTspice, Mathcad, Matlab-Simulink) Ability to Create and review the test reports from conducted test data of DO-160 Tests. Basic Qualifications: BE/BTech or Masters degree in Electrical or Electronics and Communications Engineering. 12 - 17 years of relevant industry experience with at least 6 years as an Electrical Engineer performing ED Analysis and Testing for DO160 certification (Static Timing Analysis, Stress, Power Summary, Signal Integrity and Power Integrity along with HW requirements management, HW verification and validation). Ability to interpret customer s requirement and estimate the work for the technical solution. Capability to lead the critical design reviews with global stakeholders and customer audits. Hands on experience with Lab tools and debugging (CRO, Signal generators, logic analyzer and environmental testing equipment s, code optimization, timing analysis, CPU loading, digital circuits, hardware software integration etc) Preferred Qualifications: Experience in DO254 and DO160 Certification process by supporting SOI 1 to SOI 4. Experience in FPGA/ASIC and Hardware design development. Able to create the Test Plans and Procedures for HW. Competencies Shall possess strong written and verbal communication skills in English Shall be able to coach/mentor the junior level professionals Shall be a very good listener & a very good team player Shall be curious to learn always, result oriented & forward looking Shall be able to work with a sense of urgency & under ambiguous conditions Shall possess high degree of ownership & accountability Shall be very good at analytical thinking and problem solving . The high-quality products we design, test and produce in our Advanced Structures business help millions of passengers reach their destinations safely - every day! From nacelles, landing systems, flight controls and actuation to propellers- the products we manufacture work together behind the scenes to enhance the overall flight experience. We delight our customers with superior products and best-in-class service. Our global team is committed to continuous improvement - we work hard to make our solutions lighter-weight, stronger and more technically advanced, so that plane travel can be safer, more affordable, and more sustainable in the years to come. We are looking for the best and brightest to fly and land with us! WE ARE REDEFINING AEROSPACE. Some of our competitive benefits package includes: Transportation facility. Meal coupons Group Term Life Insurance. Group Health Insurance. Group Personal Accident Insurance. Entitled for 18 days of vacation and 12 days of sick leave annually. Employee scholar program Work life balance Car lease program National Pension Scheme LTA Fuel & Maintenance /Driver wages Meal vouchers And more! Nothing matters more to Collins Aerospace than our strong ethical and safety commitments. As such, all India positions require a background check, which may include a drug screen. At Collins, the paths we pave together lead to limitless possibility. And the bonds we form - with our customers and with each other -- propel us all higher, again and again. Apply now and be part of the team that s redefining aerospace, every day .

Lead the core level pre-silicon functional & performance verification for our next -generation IBM POWER processor core systems offering. Understand the IBM Power ISA and micro-architecture of the processor core, understand and enhance the existing unit and core level verification environment. Develop deep understanding of the processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units of the high performance processor CPU. Hands on debug for core level fails, propose and implement stimulus enhancements and drive improving the debug capabilities for core testbench environments. Develop verification test plan for both functional and performance verification including the estimation for coverage closure. Support higher level core/system simulation environment. Participate in post silicon lab bring-up and validation of the Hardware. Lead , guide ,mentor a team of engineers and represent them at global forums. Thoroughly document verification environment details, providing comprehensive insights for future reference and continuous improvement. Effectively Communicate progress ,potential challenges encountered and milestones achieved to stake holders and team members. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 12 years or more experience in functional verification of processors, demonstrating a deep understanding of complete processor pipeline stages. Good understanding of computer architecture, including Processor core design specifications,processor pipeline including Instruction Fetch, Branch Prediction, Dispatch, Load Store and execution units Experience with high frequency, instruction pipeline designs. At least 1 generation of Processor Core silicon bring up experience. In depth understanding of industry microprocessor designs (e.g., x86, ARM, or RISC-V processor designs) Exposure to system-level verification methodologies and techniques, ensuring holistic verification coverage across multiple levels of design Proficiency in C++, Python scripting or similar object oriented programming languages. Preferred technical and professional experience Nice to haves - Knowledge of verification principles and coverage. - Knowledge of test generation tools and working with ISA reference model. - Experience with translating ISA specifications to testplan. - Understanding of Agile development processes. - Experience with DevOps design methodologies and tools.

When visionary companies need to know how their world-changing ideas will perform, they close the gap between design and reality with Ansys simulation. For more than 50 years, Ansys software has enabled innovators across industries to push boundaries by using the predictive power of simulation. From sustainable transportation to advanced semiconductors, from satellite systems to life-saving medical devices, the next great leaps in human advancement will be powered by Ansys. Innovate With Ansys, Power Your Career. Summary / Role Purpose As Senior Application Engineer, you will be part of the team deploying Ansys EDA products across all top Semiconductor companies. This involves working with Software developers, Architects, & Product Specialists to get the product developed, and deploy it on leading edge SoCs across Semiconductor companies. Key focus areas will include all areas related to IP/SoC/3DIC Power Integrity, Signal Integrity, Reliability aspects like EM/ESD/Thermal, Advanced timing/jitter, Packaging the top challenges for any chip design on advanced nodes like 7/5/3 nm. Key Duties and Responsibilities Be a senior member of Application Engineering Team that: Works with Global-Customers / IP-providers / Foundries to understand design challenges of cutting-edge SoCs & 3DICs on 7/5/3 nm and creates EDA product specifications. Works with Product development team to get state-of-the-art EDA products developed. Works on Ansys-Seascape platform - Semiconductor Industrys First and Only True Big-Data design Platform! Works with top Semiconductor companies around the globe to deploy EDA products for solving Power/Signal/Reliability challenges across Chip-Package-System at 7/5/3 nm. Works on RedHawk and RedHawk-SC to help users and to perform EMIR/power-integrity sign-off analysis. Provides expert guidance / consultation to Customers around the globe for solving design challenges. Minimum Education/Certification Requirements and Experience BS in Engineering, Electrical/Electronics Engineering, Computer Science, or related field with 5 years’ experience, MS with 3 years’ experience, or PhD 3+ years of prior experience in either of a) ASIC Physical design, b) Power-Integrity/Signal-Integrity/Reliability Closure c) Custom circuit design and simulation Bachelor’s/Master’s degree in Electronics Engineering/VLSI from Top Institutions Strong problem-solving skills Good programming skills Excellent verbal and written communication skills Preferred Qualifications and Skills Passion to learn and deploy new technologies. Ability for minimal travel At Ansys, we know that changing the world takes vision, skill, and each other. We fuel new ideas, build relationships, and help each other realize our greatest potential in the knowledge that every day is an opportunity to observe, teach, inspire, and be inspired. Together as One Ansys, we are powering innovation that drives human advancement. Our Commitments: Amaze with innovative products and solutions Make our customers incredibly successful Act with integrity Ensure employees thrive and shareholders prosper Our Values: Adaptability: Be open, welcome whats next Courage: Be courageous, move forward passionately Generosity: Be generous, share, listen, serve Authenticity: Be you, make us stronger Our Actions: We commit to audacious goals We work seamlessly as a team We demonstrate mastery We deliver outstanding results OUR ONE ANSYS CULTURE HAS INCLUSION AT ITS CORE We believe diverse thinking leads to better outcomes. We are committed to creating and nurturing a workplace that fuels this by welcoming people, no matter their background, identity, or experience, to a workplace where they are valued and where diversity, inclusion, equity, and belonging thrive. At Ansys, you will find yourself among the sharpest minds and most visionary leaders across the globe. Collectively we strive to change the world with innovative technology and transformational solutions. With a prestigious reputation in working with well-known, world-class companies, standards at Ansys are high met by those willing to rise to the occasion and meet those challenges head on. Our team is passionate about pushing the limits of world-class simulation technology, empowering our customers to turn their design concepts into successful, innovative products faster and at a lower cost. At Ansys, it's about the learning, the discovery, and the collaboration. It's about the what's next as much as the mission accomplished. And it's about the melding of disciplined intellect with strategic direction and results that have, can, and do impact real people in real ways. All this is forged within a working environment built on respect, autonomy, and ethics. CREATING A PLACE WE'RE PROUD TO BE Ansys is an S&P 500 company and a member of the NASDAQ-100. We are proud to have been recognized for the following more recent awards, although our list goes on: Americas Most Loved Workplaces, Gold Stevie Award Winner, Americas Most Responsible Companies, Fast Company World Changing Ideas, Great Place to Work Certified (China, Greece, France, India, Japan, Korea, Spain, Sweden, Taiwan, U.K.). For more information, please visit us at www.ansys.com Ansys is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, and other protected characteristics. Ansys does not accept unsolicited referrals for vacancies, and any unsolicited referral will become the property of Ansys. Upon hire, no fee will be owed to the agency, person, or entity.

Key Responsibilities: Drive sales strategy and revenue growth in VLSI and IC design services Identify and win new business opportunities (new logos & expanded accounts) Engage with R&D and engineering leadership at Tier-1 semiconductor firms Build and maintain strong client relationships through consultative selling Collaborate with presales, delivery, and hiring teams to fulfill project needs Create strong sales pipeline through proactive networking and outreach Mentor and lead a small, high-performing sales team Provide input on solution strategy, proposals, SoW, and MSA reviews Must-Have Skills: Proven experience in IC/VLSI Design Services sales Strong connects with top semiconductor firms (e.g., AMD, Qualcomm, Micron) Understanding of Silicon Engineering value chain (Frontend, Backend, Post-Silicon) Familiarity with RTL to GDSII, STA, DFT, Verilog, UVM Excellent communication, negotiation, and client handling skills Good-to-Have Skills: Hands-on background in VLSI design, verification, or validation Experience building VLSI service offerings, partnerships, and go-to-market plans Awareness of market trends and competitor strategies in semiconductors Ability to guide and grow business development or sales teams

Key Responsibilities: Define and lead the strategy for VLSI front-end design services Build and scale high-performing VLSI engineering teams (from 50 to 500+) Engage with customer design managers and secure design wins through deep technical collaboration Mentor and upskill engineering teams in line with evolving industry needs Ensure successful delivery of ASIC design and verification projects Develop innovative proposals and drive new project wins Collaborate with internal resourcing teams and external partners to fulfill staffing needs Represent VLSI practice in industry forums and events Must-Have Skills: Strong leadership experience in VLSI/ASIC front-end engineering Expertise in RTL design, UVM-based verification, UPF/SDC, formal verification, emulation Hands-on with commercial EDA tools (Synopsys, Cadence, Siemens) Familiarity with Verilog and standard formats (LEF/DEF/SPEF) Client engagement, delivery management, and proposal leadership Good-to-Have Skills: Industry connects with EDA vendors, foundries, and Tier-1 semiconductor companies Knowledge of ASIC-package co-design Experience in defining VLSI roadmaps, SoW/MSA processes Automation exposure (Python/Perl) Awareness of semiconductor industry trends and competitor insights

Key Responsibilities: Define and lead VLSI back-end services strategy and offerings Build and scale high-performing VLSI engineering teams (300+ roadmap) Engage with semiconductor clients for technical discussions and project wins Oversee delivery of back-end services including physical design, STA, DFT, timing/power analysis Collaborate with sales, presales, and partner ecosystem to drive business growth Mentor engineers and ensure alignment to latest tech trends and client needs Lead proposal creation, solution demos, and client engagement at senior levels Must-Have Skills: Strong experience in VLSI/ASIC back-end engineering Physical design, timing closure, DFT, power/performance optimization Expertise in EDA tools (Synopsys, Cadence, Siemens) Verilog, LEF/DEF/SPEF formats Excellent leadership, communication & stakeholder management Good-to-Have Skills: Proficiency in scripting (Python, Perl, Tcl) Experience with advanced node technologies (7nm, 5nm, etc.) Exposure to ASIC-package co-design Strong industry connects (EDA vendors, foundries, Tier-1 chipmakers) Strategy planning, SoW/MSA reviews, innovation initiatives

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced Debug IP Design Engineer/Microarchitect to focus on the development of Debug IPs. The ideal candidate will have a strong background in IP design, verification, and delivery, with specific expertise in CoreSight IP design. Key Responsibilities: Debug IP Design: Focus on the design and development of CoreSight based Debug IPs, ensuring they meet the required specifications and performance standards. RTL Design: Utilize your experience in RTL design for complex SoC development using Verilog and/or SystemVerilog to create efficient and reliable IPs. Arm-Based Designs: Apply your knowledge of Arm-based designs and/or Arm System Architectures to develop and optimize IPs. Collaboration: Work closely with cross-functional teams, SoC integration & Architecture teams to ensure successful IP delivery within the specified timelines. Quality Assurance: Implement rigorous verification processes to ensure the IPs meet all functional and performance requirements. Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Experience: Proven experience in RTL design for complex SoC development using Verilog and/or SystemVerilog. Arm Expertise: Strong understanding of Arm-based designs and/or Arm System Architectures. Technical Skills: Proficiency in IP design, verification, and delivery, with a focus on Debug IPs. Communication: Excellent communication and collaboration skills to work effectively with cross-functional teams. Preferred Skills: Experience with CoreSight based Debug IP design. Strong problem-solving and analytical skills Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Systems Engineering General Summary: We are seeking a highly skilled and experienced IP Design Engineer to join our dynamic team. The ideal candidate will have a strong background in microarchitecture design, RTL design for complex IPs, and a deep understanding of AMBA or PCIe protocols. This role requires a hands-on approach and a commitment to delivering high-quality, reliable designs. Key Responsibilities: Lead the design and development of ground-up IP solutions, focusing on microarchitecture and RTL design. Collaborate with cross-functional teams to define and implement design specifications and requirements. Ensure the quality and performance of designs through rigorous PLDRC and synthesis processes. Develop and maintain detailed documentation for design processes and methodologies. Troubleshoot and resolve complex design issues, ensuring timely and effective solutions. Stay current with industry trends and best practices in IP design and related technologies. Qualifications: 7-10 years of experience in IP design, with a strong focus on microarchitecture and RTL design for complex IPs. Extensive hands-on experience with AMBA protocol or PCIe protocol. Proficiency in PLDRC and synthesis tools to ensure high-quality design outputs. Strong understanding of digital design principles and methodologies. Experience with design verification and validation processes. Excellent problem-solving skills and the ability to work independently and in a team environment. Strong communication and interpersonal skills. Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Preferred Skills: Experience with industry standard design flow tools. Knowledge of ASIC design flows. Familiarity with scripting languages such as Python for automation. Experience with version control systems like Git, clearcase. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience.