776 Asic Jobs - Page 13

" Key Responsibilities Feature Ownership : Take end-to-end ownership of medium-complexity switching features including VLAN management, link aggregation, and QoS implementations Broadcom SDK Integration : Develop and maintain software components using Broadcom switching SDK and APIs Protocol Development : Implement network protocols such as RSTP, MSTP, IGMP snooping, and basic routing protocols Performance Optimization : Optimize switching software for packet processing performance and latency requirements Hardware Abstraction : Develop hardware abstraction layers for different Broadcom chipset families and switch platforms System Integration : Integrate switching features with management plane software and CLI interfaces Cross-Platform Support : Ensure software compatibility across different switching platforms (10GB, 25GB, 100GB, 400GB) Debugging Complex Issues : Analyze and resolve complex switching software issues using hardware debugging tools Code Reviews : Conduct thorough code reviews and mentor Engineer II team members Technical Requirements Advanced C Programming : Proficient in C programming with deep understanding of memory management, data structures, and embedded optimization techniques Broadcom SDK : Hands-on experience with Broadcom switching SDK, BCM APIs, and ASIC programming concepts Network Protocols : Solid understanding of L2/L3 protocols, switching algorithms, and packet processing pipelines Embedded Linux : Experience with embedded Linux development, kernel modules, and device drivers Real-time Systems : Understanding of real-time constraints, interrupt handling, and system performance optimization Hardware Debugging : Proficiency with hardware debugging tools, oscilloscopes, and protocol analyzers Switching Domain Expertise Understanding of switching architectures, forwarding tables, and ASIC pipeline programming Knowledge of SME-focused switching features: simplified VLAN management, automated network segmentation, guest network isolation, and branch office connectivity Understanding of SME network management requirements including centralized configuration, automated policy deployment, and simplified troubleshooting Basic understanding of network management protocols (SNMP) and switch management architectures optimized for SME environments Familiarity with switching performance metrics and optimization techniques for cost-sensitive SME deployments Qualifications Bachelors degree in Computer Science, Electrical Engineering, or Computer Engineering 2-5 years of embedded software development experience 1+ years of experience with network switching software or similar embedded networking systems Experience with Broadcom or similar networking ASIC SDKs preferred Strong debugging skills and experience with embedded development tools

We are hiring a CAD Automation Software Engineer (Frontend & Backend) with 10+ years of experience to deploy and support front-end tools, develop scripts for regression and debug flows, and collaborate with design, implementation, and verification teams. The candidate must be proficient in scripting (Python, Bash, C), Linux administration, and version control (Git/Mercurial). Experience in ASIC flows, CAD tools, and CI/CD setup is essential.

About Marvell . Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. Conduct reviews in all the SOC/Subsys verification phases, to achieve desired quality + on-schedule deliverables and drive SOC/Subsys verification process improvement. Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. Work effectively with a global team and be self-motivated to manage deliverables Communicate clearly both verbally and in writing. What Were Looking For Technical Requirement s: Bachelor s degree in CS/EE with 14 18 years of relevant experience, or Master degree in CS/EE with 12 16 years of relevant experience Must Lead a team of 4-6 engineers Experience in SOC/Subsys level/Block verification of ARM-based SOCs; experience in ARM based boot environment preferred. Knowledgeable of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. Experience with industry standard interfaces such as DDR, eMMC, PCIE, Ethernet and USB. Experience in coding UVM SOC/Subsys level testbenches, BFM, scoreboards, monitors, etc. Proficient in writing and debugging tests in UVM as well as C. Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. Experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Familiarity with TLMs in SystemC. Experience in Version tools like CVS, SVN, GIT etc. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

About Marvell . Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys/Block Specification to Silicon. Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. Work effectively with a global team and be self-motivated to manage deliverables Communicate clearly both verbally and in writing. What Were Looking For Technical Experience: Bachelor s degree in CS/EE with 8 12 years of relevant experience, or Master degree in CS/EE with 8 10 years of relevant experience Strong background in IP, Subsystem and SoC verification, including methodology and testbench development Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus Strong analytical and problem-solving skills Ability to manage multiple tasks in a fast-paced environment Excellent communication, interpersonal, and teamwork skills Capable of interfacing effectively at all levels within and outside the organization Proactive in participating in problem-solving and quality improvement initiatives Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Description Our mission at Enphase Energy is to advance a sustainable future for all. Today, our intelligent microinverters, which turn sunlight into an affordable, safe, reliable, and scalable source of energy, work with virtually every solar panel made, and when paired with our award-winning smart battery technology, we engineer one of the industrys best-performing clean energy systems. To date, we have installed more than 48 million microinverters on more than 2.5 million systems across 140 countries and well over 50 thousand homes use our energy storage products. Like our customers, our innovative teams are also worldwide, making Enphase Energy a truly global company. We are one of the fastest growing and most dynamic energy companies in the world. Nimble and acutely focused on developing ground-breaking solar energy management technology, each of our teams has a shared goal of creating a carbon-free future. Do you want to help change the worldLearn more about the role: Our custom designed ASICs enable our industry-leading IQ microinverters, batteries and other energy management products. We are looking for an engineer to characterize and qualify our ASICs before we produce millions in support of our energy services platform What you will be doing: Drive new ASIC s through NPI process for all things related to characterization, qualification, and manufacturing test (Yields, Costs, Test time, etc) Work with the ASIC design engineers to establish testability against Requirements Coordinate with our foundry partners to develop manufacturing test plans Design a set of PCBs for characterization and burn-in new ASIC s Write code to control the char equipment Characterization of new ASIC s vs datasheet requirements Reproduce and debug ASIC issues as they arise Support Failure Analysis for any RMA units Drive difficult cross functional problem solving across ASIC design (digital and/or analog), foundry partners, system level engineering and manufacturing test engineers What We Are Looking For You will need to be an independent self-starter but also a natural team player. Strong oral and written communication abilities are required. Your attention to details and desire to learn new things will make you stand out in our pool of candidates. Your background should include: Bachelor s degree + 5-12+ years of demonstrable professional experience in electrical engineering Familiarity with the operation of ADCs, op amps, comparators, FET drivers. etc Experience in Semiconductor Fabrication Process and Skew corners. Experience in analysing Wafer Acceptance Test to drive performance and yield results. Knowledge of Statistical Processes , Design of Experiments for ASIC debug and Software for analysis (i.e. JMP or Minitab) Experienced in driving device qualification and in Failure Analysis process. Experience with Python or similar scripting languages. Strong understanding of tests and test equipment including SMUs, AWG, logic analysers, oscilloscopes, DMMs, etc. Experience with ATE platforms (Verigy 93K preferred), Wafer Probers and Handlers. Experience in bring up, debug and analysing a board or system for failures Experience with of Cadence PCB tools (OrCAD CIS and Allegro) and knowledge of the full-design flow of a PCBA Being comfortable using a solder station for rework and basic assembly Any experience with National Instruments LabView and TestStand is considered a big plus.

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

Responsible for all aspects of physical design and implementation.Responsibilities include chip floor plan, power/clock distribution, chip assembly and P&R, timing closure, power and noise analysis and back-end verification across multiple projects. High level of expertise in complete physical implementation tool chain; Good working knowledge and experience of netlist to GDSII flows Hands-on technical experience with deep sub-micron technology ASIC design, STA and physical implementation;Expertise in Synthesis, Static Timing Analysis and Timing Closure of High Performance Hard-Macros and/or Full Chip Physical DesignsShould be independent, self-driven and a strong team player. Thorough understanding and knowledge of the entire Back end flow Netlist to gdsii Must be familiar with Industry standard tools like ICC/Encounter/Talus/Olympus Should have expertise in Timing analysis and closure Should have Tcl and perl scripting skills Should have work experience in the latest technology nodes like 16nm/14nm/10nm Should be familiar with low-power design and their impact on Back end flow (power switches/Level shifter/Isolation cell/retention cells/Back biasing/Forward biasing)

Experience with OVM/UVM/VMM/Test Harness, developing assertions, checkers, coverage, and scenario creation.,min 2 to 3 SoC Verification projects.developing test and coverage plans, verification environments, and validation plans,

S ENIOR SOFTWARE DEVELOPMENT ENGINEER THE ROLE: AMD is looking for a specialized software engineer to join our growing team. You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technologies. As a key contributor you will be part of a leading team to drive and enhance AMD s abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: The ideal candidate should be passionate about software engineering, have good understanding of the underlying hardware and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Design, develop and maintain Bootloaders and/or Security libraries and drivers Stay informed of software and hardware trends and innovations Design and develop new groundbreaking AMD technologies Participating in new SoC/ASIC and hardware bring ups Debugging/fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: Proficiency in C, Python Good understanding of ARM architecture and knowledge of ARM based SoCs Ability to write high quality code with a keen attention to detail Experience with Windows, Linux and/or any RTOS Experience developing bootloaders and drivers for hardware cyrpto accelerators is a plus Experience in developing software, that is certified for Safety and Security, is a plus Effective communication and problem-solving skills ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Electronics and Communication Engineering or Computer Science and Engineering, or equivalent #LI-SG

. Job Title: Software Engineer 3_ Platform Software Experience: 3+ Years Location: Bangalore About ACX Platform Software Team Our team in Juniper is responsible for driving technology leadership in the Juniper routing, access, and aggregation router developments for next-generation Metro and 5G networks, deployed in some of the world s largest service providers, data centers, enterprise, and metro ethernet networks. We are driving Juniper s growth in revenue and market share in service provider, data center, enterprise, access, and aggregation space, by delivering market-leading products with continuous innovation and relentless execution. These products (either modular or chassis-based) are based on either Juniper homegrown switching ASIC or based on merchant silicon. Who are we looking for? Upbeat and hardworking engineers with a can-do demeanor to become part of Junipers success story. Responsibilities You will be part of this platform team, responsible for developing platform software in the areas of: Board bring-up related experience. 10G, 40G, 100G, 400G, 800G interface related platform software like interface drivers, etc. Platform infrastructure-related software like Routing Engine Redundancy/High Availability, Chassis/line card, fabric, Optics, etc. Timing software in PTP, SYNCE & Grand Master You will be responsible for these product developments in the platform area in either JunOS or Junos evolved software architecture. In addition to the development activity, you are required to work closely with system and solution test teams to ensure products/solutions delivered are of the highest quality. You will be required to work closely with Juniper Technical Assistance Team for providing engineering assistance in supporting critical customer escalations for customer deployments. Requirements BTech / MTech in CS/CE or related field with proven experience. Good understanding of hardware-level details for Optics, PCIe, SPI, I2C, Retimers, FPGA, CPLD, MDIO, Flash Driver Proficiency with device drivers, system bring-up, FreeBSD/Linux internals. Understanding of Ethernet, OTN, SONET, etc. technologies. Strong technical, analytical, and problem-solving skills. Strong in C, C++ programming, OO analysis & design, data structures, and system debugging skills. Prior software development experience on networking products.

. Job Title: Software Engineer 4 - Platform Software, Device drivers, System bring-up Experience: 7+ Years Location: Bangalore About ACX Platform Software Team Our team in Juniper is responsible for driving technology leadership in the Juniper routing, access, and aggregation router developments for next-generation Metro and 5G networks, deployed in some of the world s largest service providers, data centers, enterprise, and metro ethernet networks. We are driving Juniper s growth in revenue and market share in service provider, data center, enterprise, access, and aggregation space, by delivering market-leading products with continuous innovation and relentless execution. These products (either modular or chassis-based) are based on either Juniper homegrown switching ASIC or based on merchant silicon. Who are we looking for? Upbeat and hardworking engineers with a can-do demeanor to become part of Junipers success story. Responsibilities You will be part of this platform team, responsible for developing platform software in the areas of: Board bring-up related experience. 10G, 40G, 100G, 400G, 800G interface related platform software like interface drivers, etc. Platform infrastructure-related software like Routing Engine Redundancy/High Availability, Chassis/line card, fabric, Optics, etc. Timing software in PTP, SYNCE & Grand Master You will be responsible for these product developments in the platform area in either JunOS or Junos evolved software architecture. In addition to the development activity, you are required to work closely with system and solution test teams to ensure products/solutions delivered are of the highest quality. You will be required to work closely with Juniper Technical Assistance Team for providing engineering assistance in supporting critical customer escalations for customer deployments. Requirements BTech / MTech in CS/CE or related field with proven experience. Good understanding of hardware-level details for Optics, PCIe, SPI, I2C, Retimers, FPGA, CPLD, MDIO, Flash Driver Proficiency with device drivers, system bring-up, FreeBSD/Linux internals. Understanding of Ethernet, OTN, SONET, etc. technologies. Strong technical, analytical, and problem-solving skills. Strong in C, C++ programming, OO analysis & design, data structures, and system debugging skills. Prior software development experience on networking products.

. Job title: Software Engineer Staff - Platform Software, Device drivers, System bring-up Experience: 10+ Years Location: Bangalore About ACX Platform Software Team Our team in Juniper is responsible for driving technology leadership in the Juniper routing, access, and aggregation router developments for next-generation Metro and 5G networks, deployed in some of the world s largest service providers, data centers, enterprise, and metro ethernet networks. We are driving Juniper s growth in revenue and market share in service provider, data center, enterprise, access, and aggregation space, by delivering market-leading products with continuous innovation and relentless execution. These products (either modular or chassis-based) are based on either Juniper homegrown switching ASIC or based on merchant silicon. Who are we looking for? Upbeat and hardworking engineers with a can-do demeanor to become part of Junipers success story. Responsibilities You will be part of this platform team, responsible for developing platform software in the areas of: Board bring-up related experience. 10G, 40G, 100G, 400G, 800G interface related platform software like interface drivers, etc. Platform infrastructure-related software like Routing Engine Redundancy/High Availability, Chassis/line card, fabric, Optics, etc. Timing software in PTP, SYNCE & Grand Master You will be responsible for these product developments in the platform area in either JunOS or Junos evolved software architecture. In addition to the development activity, you are required to work closely with system and solution test teams to ensure products/solutions delivered are of the highest quality. You will be required to work closely with Juniper Technical Assistance Team for providing engineering assistance in supporting critical customer escalations for customer deployments. Requirements BTech / MTech in CS/CE or related field with proven experience. Good understanding of hardware-level details for Optics, PCIe, SPI, I2C, Retimers, FPGA, CPLD, MDIO, Flash Driver Proficiency with device drivers, system bring-up, FreeBSD/Linux internals. Understanding of Ethernet, OTN, SONET, etc. technologies. Strong technical, analytical, and problem-solving skills. Strong in C, C++ programming, OO analysis & design, data structures, and system debugging skills. Prior software development experience on networking products.

About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect In this role based in Hyderabad - India, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process. You will be responsible for maintaining, enhancing, and supporting Marvells Place and Route Flow, leveraging industry-standard EDA tools. Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks. You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues. Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell. What Were Looking For Completed a Bachelor s Degree in Electronics/Electrical Engineering or related fields and have 4-8 years of related professional experience OR a Master s degree and/or PhD in Electronics/Electrical Engineering or related fields. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis. Good understanding of standard Synthesis to GDS flows and methodology. Good scripting skills in languages such as Perl, tcl, and Python. Good understanding of digital logic and computer architecture. Hands-on experience in advanced technology nodes upto 2nm. Strong hands-on experience in blocks/subsystem P&R implementation using Cadence Innovus and Synopsys FC. Strong experience in block level signoff power, timing, PV closure & debugging skills. Good top level and full-chip experience is an added advantage Knowledge of Verilog/VHDL. Good communication skills and self-discipline contributing in a team environment. Ability to independently drive subsystems/IPs P&R and signoff closure working with global teams. Ability to mentor juniors and be involved in team development activities. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

NVIDIA needs a Senior Custom SOC/IP Verification Engineer for next-gen solutions. Seeking hard-working individuals to build life-changing custom SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of exceptional people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. What youll be doing: Lead ASIC design verification for various processing blocks in a SOC, including planning, execution, Coverage and methodology development. Collaborate with multiple teams (Architecture, SW/FW, Design, Modeling, Emulation, Post-Silicon Validation) to ensure comprehensive verification plans. Support engineering teams in delivering solutions for purpose-built ASICs and collaborate with IP development teams for IP identification, selection, and licensing. Analyze SOC and IP architecture, develop verification plans, and establish performance metrics. Work with partners in a co-development environment during development, debug, and bringup. Plan tests, achieve coverage closure, and enable customer TB infrastructure. Validate use cases for power-on and boot requirements. What We Need To See: Proficient in design verification tools like Synopsys VCS, Cadence Xcelium Simulator, Verdi, JasperGold, and VC Formal. Consistent track record of first-pass success in ASIC Development. Holds a B. S. or M. S. degree in Computer Engineering or Electrical Engineering, with 7+ years of experience in ASIC, IP, or SoC design verification. Skilled in handling mixed language UVM and C++ testbenches, interpreting functional specs, and building comprehensive test plans. Experienced in developing tools and infrastructure using Perl or Python, with a strong background in AMBA protocols (AXI, ACE, CHI, ATB). Hands-on experience with subsystems in new technologies like ARM CPU, LPDDR, HBM, GPUs, DLA, PCIe, and Network on chip, including performance verification. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

NVIDIA is seeking Silicon Solutions Engineer for system level bringup, debug and validation of GPU and SoC. The sophisticated nature of various chip features poses many exciting debugging situations. Someone with solid understanding and innovative thinking is required for on time release of the products. As part of the Silicon Solutions Team, we are responsible for productizing NVIDIAs chips into groundbreaking consumer, professional, server, mobile, and automotive solutions. What you will be doing: Silicon and board bring up, validation, and debug from prototype to production. Responsible for the GPU and SoC system qualification including feature checks, system stress at PVT conditions, testing of large number of systems and debug of issues affecting any unit of the chip or software. Debug complex ASIC and board issues related to logic design, signal integrity and power delivery in a high energy work environment, with a team that is the best in the business! Understand architecture of next generation chips, develop test plans, scripts and implement. Understand various HW features related to power, performance and safety. Drive the debug of Silicon, Board or Software issues involving many multi-functional teams. Develop new methodologies to improve the silicon validation process and take it to the next level! What we need to see: BTech/BE or MTech/ME degree in Electronics with 2+ years of work experience. Good knowledge in board and system design considerations, experience in silicon design/bring up. Hardware design experience related to high speed subsystem design, High-speed IO protocols, on-chip interconnect would be much appreciated. An understanding of PC architecture and various commonly used buses. Familiarity with scripting languages like perl and/or python. Very good problem solving and debugging skills. Strong data analysis and logical reasoning skills. Must be a standout colleague and ready to work with global teams from diverse cultural backgrounds. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation. #LI-Hybrid

Role Business Analyst Location Mumbai Contract 12 months f2f interview Summary: The Business Analyst is a member of the IT Regulatory team whose focus is supporting project-based reporting solutions for internal customers and external regulators. Primary Responsibilities : Partner with key stakeholders to translate business needs into technology requirements Elicit and document the client's business requirements, processes and workflows Develop both written and visual depictions of requirements and process flows Analyze data, identify best data sources for requirements, perform gap analysis Recommend appropriate solutions and write functional specifications, map data, and write ad hoc queries Perform QA testing of developed deliverables and assist business with User Acceptance Testing Prioritize, log, and track tasks, user issues, defects, enhancements and work requests Collaborate with other teams within Investment Technology to deliver innovative technology solutions Adhere to policies Job Requirements: Strong understanding of Investment Data and Asset Management industry 5+ years of experience in the financial services industry, preferably buy-side 5+ years of experience as a business analyst working in collaboration with software development Experience with OTC Derivatives, ETD, Equity, and Fixed Income instruments Experience with compliance systems or regulatory reporting systems is a plus Experience with EMIR, MAS, ASIC, MiFID or CFTC reporting is a plus Ability to work in a team environment Capable of managing multiple tasks with tight time deadlines Strong problem solving and practical decision-making skills Ability to communicate appropriately and effectively with stakeholders, colleagues, and vendors in both formal and informal contexts in a fashion tailored for the audience Strong SQL skills Strong Excel skills Strong analytical skills and attention to detail Tools used: Microsoft Office, Microsoft Visio, SQL

. Our team in Juniper is responsible for driving technology leadership in the Juniper routing, access, and aggregation router developments for next-generation Metro and 5G networks, deployed in some of the world s largest service providers, data centers, enterprise, and metro ethernet networks. We are driving Juniper s growth in revenue and market share in service provider, data center, enterprise, access, and aggregation space, by delivering market-leading products with continuous innovation and relentless execution. These products (either modular or chassis-based) are based on either Juniper homegrown switching ASIC or based on merchant silicon. Who are we looking for? Upbeat and hardworking engineers with a can-do demeanor to become part of Junipers success story. Responsibilities You will be part of this platform team, responsible for developing platform software in the areas of: Board bring-up related experience. 10G, 40G, 100G, 400G, 800G interface related platform software like interface drivers, etc. Platform infrastructure-related software like Routing Engine Redundancy/High Availability, Chassis/line card, fabric, Optics, etc. Timing software in PTP, SYNCE & Grand Master You will be responsible for these product developments in the platform area in either JunOS or Junos evolved software architecture. In addition to the development activity, you are required to work closely with system and solution test teams to ensure products/solutions delivered are of the highest quality. You will be required to work closely with Juniper Technical Assistance Team for providing engineering assistance in supporting critical customer escalations for customer deployments. Requirements BTech / MTech in CS/CE or related field with proven experience. Good understanding of hardware-level details for Optics, PCIe, SPI, I2C, Retimers, FPGA, CPLD, MDIO, Flash Driver Proficiency with device drivers, system bring-up, FreeBSD/Linux internals. Understanding of Ethernet, OTN, SONET, etc. technologies. Strong technical, analytical, and problem-solving skills. Strong in C, C++ programming, OO analysis & design, data structures, and system debugging skills. Prior software development experience on networking products.

At Micron, we transform how the world uses information to enrich life for all. The pace is fast, collaboration occurs on a regular basis, and innovation is expected. As a test platform development Engineer within the Non-Volatile Engineering (NVEG) Product Engineer team, you will develop and qualify low-cost in-house engineering test platforms and solve complex problems. This role requires deep understanding of test hardware and software along with NAND, UFS and PCIe protocol knowledge. You will be responsible to enable the PE test infrastructure and test platforms to test, debug and characterizing the NAND component and System products by closely working with the cross functional teams such as Test Engineering and System Integration, ASIC and FW teams and assist Qualification and Ramping of cutting-edge NAND and System Micron products. The candidates responsibility is to design, develop, debug and optimize the firmware for the test platform. Key Responsibilities: Design, develop, and qualify product engineering test hardware, platforms, test firmware and software for non-volatile memory product bring up and debug. Design, develop, debug, validate and optimize firmware code for products. Collaborate with cross-functional teams, including Test Engineering & System Integration, ASIC, FW, Product Engineering and operations, to integrate FPGA designs with other system components. Provide engineering test solutions (HW & SW) for Product Development for NAND/System characterization and Silicon debug capabilities Drive and support new protocol enablement (SCA- Separate Command Address, ONFI, UFS, PCIe) and capability bring up Routinely communicate overall project status to leadership and cross functional product team Provide guidance through debug and resolution of product related issues Qualifications: Successful candidates for this exciting opportunity will have: 8+ years of strong hands-on experience working on firmware development using C/C++ and good understanding of scripting languages including TCL, Perl/Python. Proficiency with GNU toolchain to compile, debug and build software applications. Experience in embedded systems, and good understanding of low-level firmware architecture. Knowledge of the entire firmware development lifecycle from requirements analysis, design, testing and maintenance. Knowledge of storage interface such as High Speed ONFI, UFS, PCIe, etc. Memory and Storage System behavior, architecture and design Working experience on NAND and non-volatile System products Experience with non-volatile memory, logic analyzers, oscilloscopes, and/or Automated Test Equipment (ATE) is preferred Familiar working on Unix/Linux terminal. Hands-on experience with hardware bring-up and debugging and understanding of hardware schematic and layout. Excellent data analysis, problem solving, and decision-making skills Ability to work independently in a very fast paced environment and adapt to change Drive to determine root-cause and provide corrective action for product issues Proficiency in using version control systems like Git for managing code repositories and collaboration. Self-motivated and enthusiastic in a challenging, dynamic environment Demonstrated ability to partner successfully with other groups to build strong peer relationships and achieve the best outcomes for Micron Education: Position requires a minimum of a Bachelors degree in Electrical, Electronics or Computer Engineering Course work in VLSI, semiconductor process is desirable, but not required To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidates true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

MTS SILICON DESIGN ENGINEER THE ROLE: The verification team at AMD is looking for a Member of Technical Staff to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs. THE PERSON: You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Lead and Plan verification of complex digital design blocks by fully understanding the architecture and design specifications Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics PREFERRED EXPERIENCE: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs. Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification. Strong understanding of different phases of ASIC and/or full custom chip development is required. Experience in block level NOC (Net work on Chip) verification is a plus. Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus. Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus. Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus. Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus. Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

SE NIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) THE ROLE : The position will involve working with a very experienced physical design team and is responsible for delivering the physical design of blocks/tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation chips in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5-7 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

At Micron, we transform how the world uses information to enrich life for all. The pace is fast, collaboration occurs on a regular basis, and innovation is expected. As a test platform development Engineer within the Non-Volatile Engineering (NVEG) Product Engineer team, you will develop and qualify low-cost in-house engineering test platforms and solve complex problems. This role requires deep understanding of test hardware and software along with NAND, UFS and PCIe protocol knowledge. You will be responsible to enable the PE test infrastructure and test platforms to test, debug and characterizing the NAND component and System products by closely working with the cross functional teams such as Test Engineering and System Integration, ASIC and FW teams and assist Qualification and Ramping of cutting-edge NAND and System Micron products. The candidates responsibility is to design, develop and debug the VHDL or Verilog based application and have good knowledge of FPGA platform development lifecycle. Key Responsibilities: Design, develop, and qualify product engineering test hardware, platforms, test firmware and software for non-volatile memory product bring up and debug. Develop efficient RTL design using Verilog or VHDL for FPGA implementation, ensuring optimal resource utilization. Drive complete FPGA design flow including synthesis, place and route, timing analysis and verification. Implement FPGA designs on hardware platforms using tools like Xilinx Vivado and optimize for performance, area and power and to create test bench and verification scripts. Debug and validate FPGA designs in hardware using tools such as oscilloscopes , logic analyzers , and signal tap . Optimize designs for speed, power, and resource usage based on the specific FPGA platform used. Collaborate with cross-functional teams, including Test Engineering & System Integration, ASIC, FW, Product Engineering and operations, to integrate FPGA designs with other system components. Provide engineering test solutions (HW & SW) for Product Development for NAND/System characterization and Silicon debug capabilities Drive and support new protocol enablement (SCA- Separate Command Address, ONFI, UFS, PCIe) and capability bring up Routinely communicate overall project status to leadership and cross functional product team Provide guidance through debug and resolution of product related issues Qualifications: Successful candidates for this exciting opportunity will have: 6+ years of experience in RTL design, synthesis, timing closure, and verification methodologies. Knowledge of storage interface such as High Speed ONFI, UFS, PCIe, etc. Memory and Storage System behavior, architecture and design Working experience on NAND and non-volatile System products Experience with non-volatile memory, logic analyzers, oscilloscopes, and/or Automated Test Equipment (ATE) is preferred Experience working on firmware development using C/C++ and good understanding of scripting languages including TCL, Perl/Python. Familiar working on Unix/Linux terminal. Hands-on experience with hardware bring-up and debugging and Understanding of hardware schematic and layout. Excellent data analysis, problem solving, and decision-making skills Ability to work independently in a very fast paced environment and adapt to change Drive to determine root-cause and provide corrective action for product issues Self-motivated and enthusiastic in a challenging, dynamic environment Demonstrated ability to partner successfully with other groups to build strong peer relationships and achieve the best outcomes for Micron Education: Position requires a minimum of a Bachelors degree in Electrical, Electronics or Computer Engineering Course work in VLSI, semiconductor process is desirable, but not required To request assistance with the application process and/or for reasonable accommodations, please contact hrsupport_india@micron.com Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards. Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron. AI alert : Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidates true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification. Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

SMTS SILICON DESIGN ENGINEER (AECG ASIC TFM Lead) T HE ROLE : As a Silicon Design Engineer in the AMD AECG ASIC TFM (Tools Flows Methodology) team, you will work with design experts to come up with the best implementation methodologies/flows and work on development and support of the BE flows. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. K EY RESPONSIBLITIES : Define and drive key Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Provide technical support to other teams P REFERRED EXPERIENCE : 12+ years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4

MTS SOFTWARE DEVELOPMENT ENG INEER THE ROLE: AMD is looking for a specialized software engineer to join our growing team. You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technologies. As a key contributor you will be part of a leading team to drive and enhance AMD s abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: The ideal candidate should be passionate about software engineering, have good understanding of the underlying hardware and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Design, develop and maintain Bootloaders and/or Security libraries and drivers Stay informed of software and hardware trends and innovations Design and develop new groundbreaking AMD technologies Participating in new SoC/ASIC and hardware bring ups Debugging/fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: 8-12 years of experience, Proficiency in C, Python. Good understanding of ARM architecture and knowledge of ARM based SoCs Ability to write high quality code with a keen attention to detail Experience with Windows, Linux and/or any RTOS Experience developing bootloaders and drivers for hardware cyrpto accelerators is a plus Experience in developing software, that is certified for Safety and Security, is a plus Effective communication and problem-solving skills ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Electronics and Communication Engineering or Computer Science and Engineering, or equivalent #LI-SK4

MTS SOFTWARE DEVELOPMENT ENG INEER THE ROLE: AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. Key Responsibilities Develop test cases to validate functionality and performance. Monitor and maintain end-to-end ML test cases for the compiler in production, addressing issues as they arise. Contribute to open-source projects, sharing your developments with the community. Influence the direction of the AMD AI platform. Collaborate across teams with various groups and stakeholders. Preferred Experience A minimum of 7+ years of experience in relevant fields. Proficiency with AI/DL frameworks such as PyTorch, ONNX, or TensorFlow. Exceptional programming skills in Python, including debugging, profiling, and performance analysis. Experience with machine learning pipelines and CI/CD pipelines. Knowledge of MLIR is a significant advantage. Strong communication and problem-solving abilities. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners #LI-NR1