331 Asic Jobs - Page 13

The candidate would be required to work on various phases of SoC DFT related activities for Broadcom APD (ASIC Product Division) s designs - DFT Architecture, Test insertion and verification, Pattern generation, Coverage improvement, Post silicon debug and yield improvement to meet the product test metrics It involves working with the Physical Design & STA team for DFT mode timing closure The role could also involve direct interaction with external customers The candidate should have in-depth knowledge of DFT concepts and should be well experienced in various aspects of DFT -ATPG, MBIST & JTAG The candidate should have worked on DFT insertion & verification, pattern generation, coverage improvement, vector simulation, post-silicon debug Strong problem solving & debugging skills are a must Expertise in scripting languages such as perl, shell, etc is an added advantage Experience with either Mentor Graphics DFT tools (TestKompress, Fastscan) or Synopsys DFT tools (DFTMax, Tetramax) is highly desirable The candidate should have worked with team across multiple geographies The candidate should be able to handle his/her work independently and also supervise the work of other team members as required The candidate should possess excellent communication skills Educational qualification & Experience Level : Bachelor s degree with 8+ years of relevant experience or Master s degree with 6+ years of relevant experience

You are responsible for ensuring that you have properly trained people and that their needs are addressed so they can focus on their jobs. You will ensure Amazon policies - including attendance tracking - are implemented and administered fairly and consistently. This includes motivating, coaching, reporting, and providing feedback of associates performance - including productivity, quality, and safety - as a means for achieving or exceeding Amazon expectations. The Team lead will address discipline and/or performance issues for LM Associates including up to termination. In addition, you will work in partnership with third party delivery providers to ensure Amazon standards are being met in accordance to service contracts. Amazon is seeking Team leads for our GSF FC operations team. Amazon is one of the most recognizable brand names in the world and we distribute millions of products each year to our loyal customers. Key job responsibilities Were seeking a Team lead for our LM operations. In this role, you will be responsible for: - Managing, on a daily basis, end to end operations for either one large site or a combination of small sites. Executing inbound and outbound operations - Meeting customer facing metrics, while maintaining cost targets and upholding safety and morale of the team reporting to you. - Driving performance management of your team members. Preparing and implementing training and development plans for associates. - Continuously improve the delivery process and attain a sustained level of delivery performance improvement. - Conducting 4M and 5S audits for the delivery station on a daily basis. - Stand-in for Area Manager. Ability to manage day and night shifts. asic qualifications 1+ years of customer-facing environment, warehousing, logistics or manufacturing experience Bachelors degree Speak, write, and read fluently in English Experience with Microsoft Office products and applications Experience with Excel Experience in customer-facing environment, warehousing, logistics or manufacturing

"> Search Jobs Find Jobs For Where Search Jobs SOC Engineering, Staff Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10321 Remote Eligible No Date Posted 26/03/2025 Alternate Job Titles: SoC Verification Engineer Staff SoC Verification Specialist Senior SoC Verification Engineer We Are: At Synopsys, we are at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we are powering it all with the world s most advanced technologies for chip design and software security. If you share our passion for innovation and SoC Design, we want to meet you. You Are: You are a highly skilled and experienced SoC Verification Engineer with a strong background in electronics and a passion for innovation. You possess a deep understanding of processor-based SoC level verification, including experience with Verilog, System Verilog, and UVM mix environment. Your hands-on experience with verification tools such as VCS, waveform analyzers, and third-party VIP integration (such as Synopsys VIPs) sets you apart as a leader in your field. With strong problem-solving, analytical, and debugging skills, you thrive in dynamic and challenging environments. You are an excellent communicator and collaborator, capable of mentoring junior engineers and working effectively with cross-functional teams. What You ll Be Doing: Understanding design specifications, defining verification scopes, developing test plans, tests, and verification infrastructure. Implementing and analyzing System Verilog assertions and coverage (code, toggle, functional). Collaborating with other verification team members to develop and execute verification test cases. Leading and mentoring junior engineers, helping them debug complex problems. Working with architects, designers, and pre- and post-silicon verification teams to accomplish tasks. Adhering to quality standards and best verification practices. Ramping up on new verification tools and methodologies using Synopsys products to enable customers. Developing innovative solutions to problems independently. Setting task-level goals and consistently meeting schedules. Collaborating with other Synopsys teams, including BU AEs and Sales, to develop and deploy tool and IP solutions. The Impact You Will Have: Ensuring the correctness and reliability of complex SoC designs. Enhancing the efficiency and effectiveness of verification processes. Mentoring and developing the skills of junior engineers. Contributing to the successful delivery of high-quality SoC products to market. Driving innovation in verification methodologies and tools. Strengthening Synopsys position as a leader in the semiconductor industry through your technical expertise. What You ll Need: B.E/B. Tech/M. E/M. Tech in electronics with 4-8 years of experience in the verification domain. Experience in IP level or SoC level verification. Proficiency in processor-based SoC level verification, including Verilog, System Verilog, and UVM. Hands-on experience with verification tools such as VCS and waveform analyzers. Experience with third-party VIP integration (e.g., Synopsys VIPs). Proficiency in UVM, C/C++, and System Verilog verification languages. Understanding of AXI-AMBA protocol variants. Experience with scripting languages (shell, Makefile, Perl). Strong understanding of design concepts and ASIC flow. Strong problem-solving, analytical, and debugging skills. Experience with ARM core verification and ARM-based technologies. Experience with USB, PCIe, and MIPI protocols. Excellent communication skills. Who You Are: An innovative thinker with a passion for technology and verification. A collaborative team player who excels in dynamic environments. An excellent communicator who can articulate complex ideas clearly. A problem solver with a keen eye for detail and quality. A mentor and leader committed to developing the skills of junior engineers. A lifelong learner dedicated to staying at the forefront of technological advancements. The Team You ll Be A Part Of: The Systems Solutions Group (SSG) delivers tool, methodology, architecture, design creation, design verification, and physical implementation expertise to enable leading-edge customers to complete their most challenging SoC design projects. Our work spans from sub-blocks to full turnkey end-to-end SoCs. Our customers range from start-ups to industry leaders, commercial companies, and government agencies. Our customers develop SoCs for high-performance computing, automotive, aerospace & defense, and more. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

"> Search Jobs Find Jobs For Where Search Jobs ASIC Digital Design, Sr Engineer Hyderabad, Telangana, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10299 Date Posted 17/04/2025 You Are: You are a seasoned digital verification engineer with a passion for innovation and problem-solving. With a BE/B.Tech degree in electronics or a related engineering field, you bring 3-5 years of hands-on experience in digital verification. Your proficiency in system verilog, UVM, coupled with a strong understanding of formal verification techniques, sets you apart. You thrive in UNIX/Linux OS environment and have a keen interest in exploring new technologies. Your ability to build UVM based testbenches , along with your prior knowledge of EDA tools and simulators, makes you an ideal candidate. Excellent English communication skills and the ability to compile verification plans and strategies are essential for this role. What You ll Be Doing: Creation of test plans Development of testbenches Creation of tests - both directed and random Functional coverage modelling and review, Code coverage review Debugging and resolving mismatches between design and C-model Integration of third party and internal verification IP Review and improvement of verification test suites and testbench Mentor junior team members Creation of Test plan, test strategy Coverage databases (Fully traceable from test plan and specification) The Impact You Will Have: Driving innovation in processor verification techniques Enhancing the efficiency and effectiveness of our verification mechanisms Contributing to the development of cutting-edge technology that sets Synopsys apart in the industry Ensuring high-quality IP delivery through rigorous verification Supporting the continuous improvement of our hardware verification processes What You ll Need: Bachelor s degree in engineering from a reputed college Minimum 3+ years of relevant experience Microprocessor verification experience is an advantage Hands-on experience with SystemVerilog and Verilog Proficiency with Verification methodologies: UVM/OVM Programming skills: C, assembly, Perl, makefile generation Experience with latest verification techniques like formal, low-power, safety etc. is an added advantage Who You Are: Innovative thinker with a passion for technology Excellent communicator and collaborator Detail-oriented and highly organized Adept at problem-solving and critical thinking Proactive and self-motivated The Team You ll Be A Part Of: You will be part of a dynamic and innovative team focused on developing and verifying ARC processor IPs. Our team values collaboration, creativity, and continuous improvement, and we are dedicated to pushing the boundaries of technology to deliver exceptional products. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

"> Search Jobs Find Jobs For Where Search Jobs ASIC Digital Verification, Sr. Engineer Noida, Uttar Pradesh, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 6031 Remote Eligible No Date Posted 19/03/2025 We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As a Digital Verification Senior Engineer, you are passionate about technology and eager to drive pre-silicon functional verification of High-Speed PHY IPs. You have a dynamic personality and a strong desire to learn and excel in pre-silicon verification activities. With a solid understanding of digital design and HDL implementation, you are ready to take on complex challenges and contribute significantly to our innovative projects. You thrive in a diverse team environment and possess excellent debug and diagnostic skills, along with proficiency in scripting and automation using TCL, PERL, or Python. What You ll Be Doing: Working on Functional Verification of High-Speed PHY IPs for DDRxx, LPDDRxx, PCIex, Display, and HDMI protocol standards. Studying IP/design blocks/Firmware Specifications and building/updating verification plans and test cases. Building/updating functional verification environments to execute test plans. Developing DV/Firmware test benches, test plans, and test cases. Implementing checkers, assertions, random test generators, high-level transactional models, and bus functional models (BFMs). Performing simulation, random and focused stimulus generation, and coverage analysis. Collaborating closely with digital designers for debugging and achieving desired coverage. Developing architecture and micro-architecture knowledge of complex digital design blocks under test. The Impact You Will Have: Ensuring the high quality and reliability of our High-Speed PHY IPs. Contributing to the successful delivery of cutting-edge technology solutions. Enhancing the performance and functionality of our products through rigorous verification. Driving innovation and excellence in our verification processes. Supporting the rapid integration of capabilities into SoC designs. Enabling our customers to bring differentiated products to market quickly with reduced risk. What You ll Need: B. Tech/M. Tech in EC/CS with 3-6 years of relevant experience in pre-silicon verification of complex PHY IPs, ASIC, or SoC designs. Understanding of functional verification flow with experience on industry-standard development and verification tools and methodologies such as VMM, OVM/UVM, and System Verilog. Proficiency in System Verilog Assertions, code and functional coverage implementation, and review. Excellent debug and diagnostic skills. Experience with scripting and automation using TCL, PERL, or Python. Who You Are: You are a detail-oriented, analytical thinker with a strong problem-solving mindset. You possess excellent communication and collaboration skills, enabling you to work effectively within a diverse team. Your passion for technology drives you to stay updated with the latest advancements and continuously improve your skills. You are proactive, adaptable, and committed to delivering high-quality results in a fast-paced environment. The Team You ll Be A Part Of: You will join a dedicated team of engineers focused on the verification of High-Speed PHY IPs. Our team is committed to innovation and excellence, working collaboratively to ensure the highest standards of quality and performance. We value diversity and inclusivity, fostering an environment where every team member can thrive and contribute to our collective success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Noida View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

* Assisting internal stakeholders (marketing, sales team) with technical presentations and evaluating potential applications of Synopsys products to meet customer needs. * Collaborating with internal and external stakeholders on technology and solution development, validation, customer engagement, and deployment. * Providing technical assistance to customers, helping them solve their technical problems, and conducting tool training sessions. * Working closely with the PrimeTime R&D team to support the adoption and continuous usage of PrimeTime. * Engaging with field teams and customers on advanced technology engagements. * Driving innovation and success in chip design through continuous technological advancements. The Impact You Will Have: * Enhancing customer satisfaction by providing expert technical support and solutions. * Driving the successful adoption and usage of PrimeTime, contributing to its market leadership. * Collaborating with R&D and field teams to innovate and improve Synopsys products and solutions. * Facilitating customer engagement and ensuring their technological needs are met effectively. * Contributing to the development and validation of cutting-edge technologies and solutions. * Playing a pivotal role in driving the success of Synopsys chip design initiatives. What You ll Need: * BSEE/MS with minimum 15 years+ of relevant experience * Proficiency in static timing analysis (STA) and advanced STA methodologies. * Strong understanding of the full flow for chip design and EDA tools/flows. * In-depth knowledge of 3DIC stacking, packaging, and their impact on timing analysis and closure. * Experience with standard cells, MEM, IO IPs, and their library modeling and usage in flow. * Proficiency in STA constraints, ECO, and power optimization flow. * Hands-on experience with SPICE simulation and STA vs SPICE correlation. * Knowledge of advanced CMOS technologies and FinFET technology at 5nm/3nm/2nm and beyond. * Coding skills in TCL and Python; familiarity with C++ is a plus. * Familiarity with industry-stand ard ASIC tools such as PT, ICC, Redhawk, and Tempus. Who You Are: * Strong communicator and collaborator. * Technically adept and detail-oriente d. * Innovative thinker with a passion for technology. * Customer-focus ed with excellent problem-solvin g skills. * Team player who thrives in a dynamic environment.

You are a seasoned ASIC Digital Design Engineer with a strong background in the design of IP Cores or SoC Designs. You have a passion for innovation and a desire to work on cutting-edge technology that powers the Era of Smart Everything. With a degree in Electrical Engineering and substantial experience in the field, you are well-versed in various protocols such as VESA-DSC, AMBA, SD/eMMC, DDR, PCIe, Ethernet, USB, and MIPI. You excel in creating micro-architecture and detailed design documents from functional specifications and have hands-on experience with Verilog/System Verilog coding and simulation tools. Your expertise in synthesis flow, static timing flows, and formal checking makes you a valuable asset to any team. You possess excellent communication skills, are a team player, and have a knack for problem-solving. Inclusion and diversity are important to you, and you thrive in a collaborative, multi-site environment. What You ll Be Doing: Understand standard specifications and functional specifications to create architecture, micro-architecture, and detailed design documents for medium to high complexity components. Contribute individually to the design tasks, including RTL coding, debugging, and verification coverage improvement. Utilize Low Power Design Methodology and automotive safety standards in your designs. Create and review designs for the DesignWare family of synthesizable cores in various protocol areas. Perform technical reviews of functional specifications, micro-architecture, and RTL code. Analyze coverage metrics and improve them by defining additional test cases in a directed environment. Collaborate with teams across multiple sites worldwide in a project and team-oriented environment. The Impact You Will Have: Drive innovation in chip design and verification, contributing to the development of advanced technologies. Enhance the performance, power efficiency, and size optimization of SoC designs. Reduce risk and speed up time-to-market for differentiated products. Ensure the reliability and robustness of IP cores through rigorous design and verification processes. Contribute to the development of industry-leading silicon IP solutions. Collaborate with a global team to achieve common goals and deliver high-quality results. What You ll Need: BSEE in Electrical Engineering with 8+ years of relevant experience or MSEE with 7+ years of relevant experience. Experience in designing IP Cores or SoC Designs. Knowledge of protocols such as VESA-DSC, AMBA, SD/eMMC, DDR, PCIe, Ethernet, USB, and MIPI. Ethernet protocol knowledge is highly preferred. Hands-on experience with creating micro-architecture and detailed designs from functional specifications. Proficiency in Verilog/System Verilog coding and simulation tools. Experience with synthesis flow, static timing flows, Lint, CDC, and formal checking. Knowledge of revision control environments like Perforce and scripting languages like Perl/Shell. Who You Are: Excellent communication skills and a team player. Strong problem-solving abilities. Detail-oriented with a focus on quality and precision. Adaptable and able to work in a fast-paced, multi-site environment. Committed to fostering an inclusive and diverse workplace

An experienced and passionate ASIC Digital Verification Engineer with a deep understanding of RTL-based IP cores and complex protocols. You have over 12 years of experience in functional verification and are adept at making architectural decisions for test bench designs. You are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM), and you have a proven track record of implementing coverage-driven methodologies. You bring a wealth of knowledge in protocols such as DDR, PCIe, AMBA, and more. Your technical expertise is matched by your strong communication skills, ability to work independently, and your innovative problem-solving capabilities. Your experience may also include familiarity with functional safety standards such as ISO26262 and FMEDA. What You ll Be Doing: Making architectural decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Implementing a coverage-driven methodology. Leading technical aspects of verification projects. Collaborating with international teams of architects, designers, and verification engineers. The Impact You Will Have: Enhancing the robustness and reliability of IP cores used in critical applications. Driving innovation in verification methodologies and tools. Ensuring high-quality deliverables through rigorous verification processes. Improving productivity, performance, and throughput of verification solutions. Contributing to the success of Synopsys customers in industries such as AI, automotive, and server farms. Mentoring and guiding junior engineers in the verification domain. What You ll Need: Knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience with UVM/VMM/OVM, test planning, and coverage closure. Proficiency in SystemVerilog and UVM, object-oriented coding, and verification. Experience with scripting languages like C/C++, TCL, Perl, Python. Experience with functional safety standards such as ISO26262 and FMEDA (preferred). Who You Are: Independent and precise in your work. Innovative and proactive in problem-solving. Excellent communicator and team player. Detail-oriented with a strong analytical mindset. Eager to learn and grow within a technical role

Designing and verifying digital and mixed-signal circuits for NRZ and PAM-based SerDes products. Collaborating with a team of experienced engineers to deliver high-performance mixed-signal designs. Developing and executing structured firmware development, verification, and documentation processes. Performing functional and performance tests on prototype test-chips. Communicating effectively with different design groups and customer support teams. Balancing good design quality while meeting tight deadlines. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that drive the innovations of tomorrow. Ensuring high-performance and reliable mixed-signal designs that meet unique performance, power, and size requirements. Accelerating the integration of more capabilities into an SoC, helping customers bring differentiated products to market quickly with reduced risk. Enhancing Synopsys reputation as a leader in chip design and software security. Driving the success of our Silicon IP business by delivering high-quality mixed-signal designs. Playing a key role in the continuous technological innovation at Synopsys. What You ll Need: BSEE or MSEE plus a minimum of 5 years industry experience in Silicon Bring up and Functional Validation. Experience with structured firmware development, verification, and documentation processes. Proficiency in digital logic design, simulation, and debug using Verilog and VCS. Demonstrated experience executing projects from start to completion. Good communication skills for interacting between different design groups and customer support teams

Owning the complete physical implementation process at both block and chip levels. Delivering timing clean blocks and chip-level designs that meet design targets. Ensuring DRC, LVS, and IR closure for all designs. Setting up and evaluating all aspects of the physical design flow, including place and route, timing, PV, and IR. Collaborating closely with the frontend design team to resolve design issues. Executing project responsibilities from start to completion, contributing to moderately complex aspects of the project. The Impact You Will Have: Ensuring the delivery of high-quality, timing-clean designs that meet industry standards. Driving innovation in physical design methodologies and processes. Contributing to the development of cutting-edge technologies that shape the future. Enhancing the overall efficiency and effectiveness of the design team. Providing mentorship and guidance to junior engineers, fostering a culture of continuous learning and improvement. Strengthening Synopsys position as a leader in the semiconductor industry through your expertise and contributions. What You ll Need: MSEE/BSEE with 6+ years of related experience in ASIC physical design. In-depth understanding of physical design specialization, with working knowledge of one other related area. Strong problem-solving skills and creativity in resolving design issues. Experience in scripting using Tcl and Perl. Ability to execute project responsibilities independently and contribute to team-driven projects. Who You Are: Detail-oriented and committed to delivering high-quality work. Collaborative and able to work effectively in a team environment. Proactive and able to take ownership of tasks and projects. Excellent communicator, capable of networking with senior personnel. Mentor and guide to junior peers, sharing knowledge and expertise.

Assisting internal stakeholders (marketing, sales team) with technical presentations and evaluating potential applications of Synopsys products to meet customer needs. Collaborating with internal and external stakeholders on technology and solution development, validation, customer engagement, and deployment. Providing technical assistance to customers, helping them solve their technical problems, and conducting tool training sessions. Working closely with the PrimeTime R&D team to support the adoption and continuous usage of PrimeTime. Engaging with field teams and customers on advanced technology engagements. Driving innovation and success in chip design through continuous technological advancements. The Impact You Will Have: Enhancing customer satisfaction by providing expert technical support and solutions. Driving the successful adoption and usage of PrimeTime, contributing to its market leadership. Collaborating with R&D and field teams to innovate and improve Synopsys products and solutions. Facilitating customer engagement and ensuring their technological needs are met effectively. Contributing to the development and validation of cutting-edge technologies and solutions. Playing a pivotal role in driving the success of Synopsys chip design initiatives. What You ll Need: BSEE/MS with minimum 12 years of relevant experience Proficiency in static timing analysis (STA) and advanced STA methodologies. Strong understanding of the full flow for chip design and EDA tools/flows. In-depth knowledge of 3DIC stacking, packaging, and their impact on timing analysis and closure. Experience with standard cells, MEM, IO IPs, and their library modeling and usage in flow. Proficiency in STA constraints, ECO, and power optimization flow. Hands-on experience with SPICE simulation and STA vs SPICE correlation. Knowledge of advanced CMOS technologies and FinFET technology at 5nm/3nm/2nm and beyond. Coding skills in TCL and Python; familiarity with C++ is a plus. Familiarity with industry-standard ASIC tools such as PT, ICC, Redhawk, and Tempus. Who You Are: Strong communicator and collaborator. Technically adept and detail-oriented. Innovative thinker with a passion for technology. Customer-focused with excellent problem-solving skills. Team player who thrives in a dynamic environment

An Emulation Expert with deep knowledge of IP interfaces such as PCIe and DDR, and experience with Zebu. You have a proven track record in IP product development focused on emulation and verification. You thrive in a matrixed, international, and team-oriented environment with multiple stakeholders. Your hands-on approach, collaborative mindset, and proactive attitude drive results. You are passionate about right-first-time development, ensuring traceability of all verification requirements and covering the entire ecosystem of Controller and PHY. What You ll Be Doing: Bridging and closing gaps between the available or required Emulation IP feature set and the Design IP verification of all its functions, covering both the Controller and PHY. Reporting metrics and driving improvements in Emulation IP. Using your expertise to drive requirements for the Emulation IP and ensure its correct usage and deployment in verification strategies for both Controller and PHY. Staying ahead of evolving standards, understanding future changes, ECNs, and specification errata, and driving this understanding into both the Emulation IP and Design IP teams. Reviewing test plans in both Emulation IP and Design IP to ensure they deliver the required function, feature, and quality to be best in class. The Impact You Will Have: Enhancing cross-functional collaboration to improve product quality and end customer satisfaction. Changing the mindset in the way we use Emulation IP in validating digital designs and architectures. Driving innovation in defining requirements for IP product development, in the context of Emulation. Evolving and integrating best-in-class methodologies within the organization. Standardizing and optimizing workflows to increase efficiency and compliance. What You ll Need: 8+ years of relevant experience. Results-driven mindset. Subject Matter Expert in PCIe and DDR interfaces. Experience with Zebu in the context of technology and IP verification . Proven track record in IP product development, specifically emulation . Experience in cross-functional collaborations. Excellent communication skills and a beacon for change. Adaptability and comfort in a matrixed, international environment .

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: Strong desire to learn and explore new technologies. Demonstrates good analysis and problem-solving skills. Prior knowledge and experience in tools like DC, ICC2, PT-SI,FC is a definite advantage. Should be a strong team player, excellent communicator as the role involves daily technical interaction with local, US counter parts. What You ll Be Doing: He/She will be part of SNPS DDR/HBM/Ucie IP implementation team and responsible for the implementation and integration of world class DDRs at the cutting-edge technology nodes. Timing closure above ~4GHz, mixed signal had macro IP integration, Building the efficient clock trees with very tight skew balancing are some of the challenges as part of day-to-day job. Prior working knowledge in the DDR/HBM/HBI timing closure, implementation would be an added advantage. Should be very hands-on and able to technically lead a team of 4-6 junior engineers towards successful completion of project on-time and with top quality. Who You Are: Typically requires a minimum of 6+ years of related experience after the post graduation. Possesses a full understanding of specialization area plus working knowledge of multiple related areas. A team player Independently resolves a wide range of issues in creative ways on a regular basis. Customarily exercises independent judgment in selecting methods and techniques to obtain solutions. Performs in project leadership role. Contributes to complex aspects of a project. Determines and develops approach to solutions. Work is independent and collaborative in nature. Provides regular updates to manager on project status. Represents the organization on business unit and/or company-wide projects. Guides more junior peers with aspects of their job.

Implementing and power signoff of world-class DDRs at cutting-edge technology nodes. Achieving timing closure above ~2GHz and integrating mixed signal macro IPs. Building efficient clock trees with very tight skew balancing. Providing regular updates to your manager on project status. Guiding junior peers with aspects of their job and contributing to their development. Representing the organization on business unit and/or company-wide projects. The Impact You Will Have: Driving the implementation of cutting-edge DDR technology, contributing to the advancement of high-performance computing. Ensuring the power efficiency and performance of our silicon chips, crucial for our competitive edge. Enhancing the reliability and integration of mixed signal macro IPs. Contributing to the overall success and innovation of Synopsys IP solutions. Mentoring junior engineers, fostering a culture of continuous learning and improvement. Representing Synopsys in key projects, influencing the direction and success of our initiatives. What You ll Need: Minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in tools like DC, ICC2, StarRC, and PT-SI. Strong understanding of timing closure, power signoff, and mixed signal macro IP integration. Experience with DDR power signoff and clock tree building. Excellent problem-solving and analytical skills. Who You Are: A strong team player with excellent communication skills. Independent and collaborative, capable of working with minimal supervision. Creative and innovative, able to develop unique solutions to complex problems. Detail-oriented and organized, ensuring high-quality project outcomes. Passionate about continuous learning and professional growth.

Floor planning, power planning, placement, and optimization Clock tree building and optimization Routing and optimization Timing constraints closure, synthesis, and formal verification Extraction, IR drop analysis, EM analysis, and signal integrity Physical verification and flow development for advanced technology nodes The Impact You Will Have: Enhance the best practices of the physical design flow Contribute to the successful implementation of high-performance digital designs Drive innovations in low-power design and high-speed clock distribution Ensure the integrity and reliability of complex IC designs Support the development of cutting-edge technology that shapes the future Collaborate with cross-functional teams to meet customer requirements What You ll Need: Solid engineering understanding of IC design concepts Strong knowledge of the full design cycle from RTL to GDSII Expertise in implementation flows and methodologies for deep sub-micron designs Experience in high-performance digital design, CAD, high-speed design, low-power design, and high-speed clock design and distribution Proven experience with project tape-outs and timing closure Proficiency in software and scripting skills (Perl, Tcl, Python) Knowledge of Synopsys tools, flows, and methodologies

At minimum, a Bachelor s degree in engineering is required with 12+ years of digital design experience using Verilog. Strong background in RISC architectures required. Working experience in RISC microprocessor IP design, programming at assembly and C/C++ level, DSP skills, an understanding of multi-core architectures and development techniques are a plus. Experience with multi-site development is helpful. The successful candidate is expected to: Design embedded RISC microprocessor IP at architectural and RTL level Write High-level architecture and micro-architecture specifications of the design Optimize design for performance, speed, area and power, generate hardware benchmarks and analyze results Develop standalone Verilog testbenches to verify their module Debug design issues / bugs working closely with the verification team Maintain our current processor product line and their derivative products Develop and maintain project plans. Work closely with program managers Good written, oral and problem-solving skills desired along with good communication skills and inter-person skills Work with multi-site, multi-time zone, multi-cultural teams on various aspects of the product like design, implementation, physical design, verification

As an ideal candidate, you are a passionate and highly skilled engineer with a keen interest in ASIC physical design. You possess a strong foundation in electronics engineering or computer science, ideally with a Bachelors degree and a minimum of 3 years of related experience. You have a methodical approach to problem-solving and are proficient in scripting languages like Unix, Perl, and TCL. Your exposure to Verilog/VHDL and understanding of microprocessor design make you a valuable asset to any team. You are a team player with excellent written and verbal communication skills, capable of working in a collaborative international environment. Your enthusiasm for learning and applying new technologies drives you to continuously improve and contribute to cutting-edge projects. What You ll Be Doing: Contributing to the physical design and implementation of our highly optimized hardware IP for the ARC family of configurable processors. Working on the full SOC design cycle with a focus on physical design tasks, including floorplanning, placement, routing, and timing closure. Collaborating with cross-functional teams to ensure the successful integration and verification of our microprocessor IP. Assisting in customer sales and design-ins of our IP by providing technical support and expertise. Participating in in-house test chip designs and development platforms to explore potential applications of our microprocessor IP. Engaging in benchmarking and qualification activities to ensure the highest performance and reliability of our products. The Impact You Will Have: Enhancing the performance and efficiency of our microprocessor IP through innovative physical design techniques. Contributing to the development of state-of-the-art embedded designs used in various high-tech applications. Supporting the successful deployment of our IP in customer projects, leading to high customer satisfaction and repeat business. Driving continuous improvement in our implementation flows and methodologies. Helping Synopsys maintain its leadership position in the semiconductor industry by delivering top-quality products. Fostering a collaborative and innovative work environment by sharing your expertise and learning from others. What You ll Need: Bachelor s degree in electronics engineering or computer science; a Master s degree is a plus. Minimum of 3 years of related experience in ASIC physical design. Proficiency in Unix, Perl, and TCL scripting. Exposure to Verilog/VHDL and understanding of microprocessor design. Strong written, verbal, and methodical skills. Who You Are: A collaborative team player with excellent communication skills. A methodical problem-solver with a keen attention to detail. Enthusiastic about learning and applying new technologies. Adaptable and able to work in an international, multi-disciplinary team. Dedicated to continuous improvement and innovation.

Implementing DDR and HBM PHYs for customer ASICs and SOCs in the DDR and HBM PHY Hardening service line. Performing synthesis, physical design, verification, design for test, and ATPG. Contributing as a senior member of a design team or as a project design engineer working with both internal and external design teams. Providing regular updates to the manager on project status. Representing the organization on business unit and/or company-wide projects. Guiding more junior peers with aspects of their job and frequently networking with senior internal and external personnel in your area of expertise. The Impact You Will Have: Enhancing the reliability and performance of DDR and HBM PHYs for customer ASICs and SOCs. Contributing to the success of complex projects through innovative problem-solving and technical expertise. Ensuring timely delivery of high-quality design solutions to our customers. Improving the efficiency and effectiveness of the design process through your autonomous judgment and technical knowledge. Strengthening Synopsys position as a leader in chip design and verification through your contributions. Mentoring and guiding junior team members, fostering a collaborative and innovative team environment. What You ll Need: A minimum of 5+ years of related experience in ASIC Physical Design. Proficiency in state-of-the-art CAD tools such as DC, PT, ICC2/FC, and ICV. Experience with advanced technologies like FinFet. Strong problem-solving skills and the ability to autonomously resolve a wide range of issues. Excellent verbal and written communication skills. Who You Are: An innovative thinker with a passion for technology and continuous learning. A collaborative team player who excels in a dynamic and fast-paced environment. A mentor and guide for junior team members. A strong communicator with the ability to network effectively with senior personnel. A composed and reliable professional who can handle risks and uncertainty with ease.

Hands-on experience of implementing digital block using state of the art gate to GDSII ASIC flows mainly including Design Initialization, Power planning, Floor planning/Macro placement, Scan-chain reordering, CTS, Route and chip finishing steps Perform Physical Implementation of blocks starting from gate netlist till gds out Perform signoff verifications including Layout verifications (DRC, LVS, Antenna) and Reliability verifications (EMIR, ESD) of the implemented blocks Ownership of writing MCMM and UPF for the block designs Provide handoff data to other signoff closure like STA, Formality, Layout and Reliability verification Job Requirements In-depth understanding of the ASIC Physical design flow steps of starting from Gate netlist Experience in Testchip implementation and testing exposure is a plus Exposure to Synopsys Tool set (such as FC/ICC2, Primetime, Formality, ICV) is highly desirable Exposure to FinFET designs is desirable Experience in working on IO integration with Wire-bond or Flip-chip design would be big plus Experience : Min 5 years of Relevant Physical design domain Education : B.E/B.Tech/M.Tech in ECE/EE

We are looking for a highly motivated individual, with expertise in IC design and physical implementation for a group with growth opportunities. Responsibilities include complete digital implementation from RTL to GDS including Synthesis, Floor-Planning, Power Planning and Analysis, CTS, Placement and Routing, STA, Formal Verification, EMIR Signoff and physical verification. The individual will contribute both on the implementation side as well as flow development for a variety of advanced high performance interface IPs, Test chips & Subsystems at latest techno nodes. The successful candidate: - has solid engineering understanding of the underlying concepts of IC design, implementation flows and sign-off methodologies for deep submicron design. - has intimate knowledge of the full design cycle from RTL to GDSII, including development of timing constraints - has good scripting & programming skills (Perl, Tcl, Python etc); knowledge of CAD automation methods. - Can interface with the larger product team to understand design constraints, deliverable formats, customer requirements - Independent, timely decision maker and able to cope with interrupts - Knowledge of IP Subsystem implementation & FE flows are added advantages 8+ years of hands-on experience in ASIC physical implementation and EDA tools with recent contribution to project tape-outs. Must demonstrate knowledge of the Synopsys tools, flows and methodologies including Design Compiler, IC Compiler/2, Fusion Compiler, Primetime, Formality, Star-RCXT, Hercules/ICV and other industry tools.

Driving the physical implementation of high-speed interface IPs and test-chips from RTL to GDS. Managing timing and physical sign-off to ensure successful project tape-outs. Collaborating with multiple functional groups, including front-end, analog, and CAD teams. Focusing on advanced SerDes developments, including the latest 56/112G PAM4 standards. Leading the physical design team to ensure on-time delivery of projects. Utilizing your software and scripting skills to enhance CAD automation methods. The Impact You Will Have: Contributing to the successful delivery of high-performance silicon IPs that power the Era of Smart Everything. Ensuring the integration of more capabilities into SoCs, meeting unique performance, power, and size requirements. Reducing the risk and time-to-market for differentiated products. Driving technological innovation through advanced SerDes development. Enhancing Synopsys reputation as a leader in chip design and verification. Supporting the companys mission to power the world s most advanced technologies for chip design and software security. What You ll Need: 8+ years of physical design experience with recent contributions to project tape-outs. Intimate understanding of the full design cycle from RTL to GDSII, including chip level. Experience with advanced FinFET nodes, TSMC 16 nanometer or below. Solid understanding of IC design, implementation flows, and methodologies for deep submicron design. Proven track record for technical steering of physical design teams for on-time delivery. Who You Are: Excellent communicator with the ability to engage with peer groups and customers. Autonomous and capable of making timely judgments. Proficient in software and scripting skills (Perl, Tcl, Python). Knowledgeable in CAD automation methods and industry standards in deep sub-micron designs. Able to travel internationally as required.

As a RTL Design lead, first time bug free RTL from requirement or specification gives you a dopamine rush. Finding an alien life is a complex challenge, however, millions of bug free lines of RTL gives much more satisfaction. We are looking for an expert like you, having done multiple tape-outs, driven the design effort for complex IP/Subsystem/SoC blocks. Verification Lead: As a Verification lead, it is always a fun to catch bugs and ensuring that the design intent is met. Imagine your chip on a space telescope and sending beautiful images of galaxy - verification is the key to avoid white spots mixing with stars. We are looking for an expert like you, having lead multiple tape-outs, closed the verification of complex IP/Subsystem/SoC blocks. Job role and Skill set - Design role: Senior RTL Subsystems Designer Lead role. With 8+ years of experience. Must be able to drive the Subsystem life cycle from requirement to final release(s) phase(s), crafting the functional specification, defining the micro-architecture, coding the RTL with best practices, driving RTL quality checks and working with Verification and implementation teams, and, all the way to release(s). Proficiency with standard protocols like PCIe, DDR, UFS, USB, AMBA etc., Hands-on experience with low power design. Understanding of DFT requirements and architecture. Working with cross-functional teams and driving the projects to completion. Job role and Skill set - Verification role: Senior Verification lead role. With 8+ years of experience. Must be able to drive the complete Verification cycle : crafting the test plan, architecting the verification environment, developing the test infrastructure and executing the plan, driving to closure with coverage. Proficiency with Functional Verification of standard protocols like PCIe, DDR, UFS, USB, AMBA etc., Power aware Verification with UPF. Gate Level Verification hands-on experience is a value add. Working with cross-functional teams and driving the projects to completion.

Defining and developing ASIC RTL design and verification at both chip and block levels. Writing and modifying test cases, checkers, and scoreboards in a system Verilog-based test environment. Collaborating with cross-functional teams to ensure seamless integration of analog and digital components. Conducting AMS verification, particularly for high-speed SerDes designs supporting multi-protocols. Utilizing Synopsys analog mixed-signal design tools for efficient design and verification processes. Programming and scripting using TCL, Perl, and Python to automate and streamline workflows. The Impact You Will Have: Enhancing the performance and reliability of our high-performance silicon chips. Contributing to the development of innovative technologies that drive the Era of Pervasive Intelligence. Improving the efficiency and effectiveness of our design and verification processes. Ensuring the seamless integration of analog and digital components in our products. Supporting the creation of cutting-edge solutions for self-driving cars, learning machines, and more. Driving continuous technological innovation within Synopsys and the broader industry. What You ll Need: Looking for 2+yrs experience with BTech / MTech in VLSI / Electronics/ Microelectronics Knowledge or hands-on expertise/analysis of Analog and digital CMOS circuit designs Knowledge on electrical circuit networks and analysis Knowledge or hands-on Verilog/System Verilog languages and supported methodologies like VMM, UVM Must be able write/modify testcases, checkers, scoreboards in a system Verilog based test environment AMS verification experience in high speed Serdes designs supporting multi-protocols is an advantage. Experience with the Synopsys Analog mixed-signal design tool set is an advantage. Modelling languages Verilog-a/ams can be an advantage Programming/scripting know-how e. g. tcl, perl, python Experience with Linux Good communication skills, ability to take ownership Self-organized to ensure that project timescales are met Who You Are: Excellent communicator with strong interpersonal skills. Proactive and able to take ownership of projects. Self-organized and capable of managing time effectively. Collaborative team player who thrives in a dynamic environment. Detail-oriented and committed to delivering high-quality results.

You are a highly motivated and experienced professional with a deep understanding of VLSI design and a strong background in high-speed protocols such as Ethernet, DDR, and PCIe Your technical expertise is complemented by your hands-on experience in simulation, synthesis, and static timing analysis (STA) With a Bachelors and/or Masters Degree in Electrical Engineering or a related field, you bring at least 10 years of design, verification, or application engineering experience to the table You thrive in a UNIX environment and are proficient with ASIC/SoC tape-out processes from concept to full production Your ability to work across teams, coupled with strong analytical, reasoning, and problem-solving skills, sets you apart as a creative and results-oriented professional Excellent verbal and written communication skills in English are essential, as you will be collaborating with customers and teams worldwide Occasional travel is something you are comfortable with, and you are ready to take on the challenge of integrating leading Interface IP into next-generation products What You ll Be Doing: Acting as a trusted advisor for our Interface IP customers, providing guidance throughout their SoC flow. Supporting customers in resolving technical challenges and performing integration reviews at key milestones. Assisting with silicon/system bring-up and debugging critical issues. Collaborating with internal teams to deliver tailored solutions to customers. Staying updated with the latest industry specifications and applications in various hot market segments. Participating in occasional travel to support customer engagements and silicon bring-up activities. The Impact You Will Have: Enhancing the usability and adoption of Synopsys Interface IP products by providing expert technical support. Facilitating successful integration of IP into customer designs, contributing to their product development timelines. Improving customer satisfaction by resolving technical issues efficiently and effectively. Driving innovation by working with cutting-edge technologies and industry specifications. Strengthening Synopsys market position through successful customer engagements and support. Contributing to the development of next-generation products that leverage high-speed protocols and advanced IP. What You ll Need: Bachelors and/or Masters Degree in Electrical Engineering or similar with a focus on VLSI design. At least 10 years of design, verification, or application engineering experience. Proficiency in RTL coding using Verilog/VHDL. Experience with high-speed protocols such as Ethernet, DDR, and PCIe. Hands-on experience with simulation, synthesis, and static timing analysis (STA). Familiarity with UNIX environments and ASIC/SoC tape-out processes. Knowledge of CDC, RDC, Lint, DFT, STA, and LEC is a plus. Who You Are: Creative and results-oriented, capable of managing multiple tasks concurrently. Strong verbal and written communication skills in English. Ability to work collaboratively across teams to deliver solutions to customers. Strong analytical, reasoning, and problem-solving skills. Willingness to travel occasionally to support customer engagements.

We are seeking a highly motivated and experienced Digital Design Manager to lead a team of seasoned digital design engineers. You possess a deep understanding of the ASIC digital design flow, along with hands-on experience in HDL coding, RTL2GDSII flow, and scripting languages. You excel in managing project execution from defining specifications to silicon validation and characterization. Your leadership skills foster a collaborative environment, driving your team to meet stringent project requirements and deliver superior quality designs. With a minimum of 10 years in digital design and at least 3 years in a managerial role, you bring a wealth of knowledge and a proven track record of successful project completions. What You ll Be Doing: Work closely with 3DIO Phy Architects to define specifications and micro-architecture, supporting early evaluations and feasibility studies to meet customer and system requirements. Lead the execution of digital design solutions for 3DIO Phy projects, ensuring robust and high-performance designs. Own the implementation of RTL in Verilog and sign-off using Spyglass CDC/RDC/Lint tools. Verify the RTL to test desired functionality, coverage, and corner cases using state-of-the-art verification methods. Oversee the full execution of RTL2GDSII, including timing constraints, DFT insertion, test coverage, formal verification, physical implementation, timing closure, physical verification, EMIR, and reliability sign-off. Support silicon validation and characterization through test chip implementation. Manage team members and operations, including career development and planning. The Impact You Will Have: Drive innovation in digital design solutions for 3DIO Phy projects, enhancing Synopsys product offerings. Ensure high-quality and robust designs that meet customer requirements and improve system performance. Streamline the digital design process from specification to silicon validation, reducing time-to-market. Lead a team of talented engineers, fostering a collaborative and productive work environment. Contribute to the continuous improvement of design methodologies and best practices. Support Synopsys position as a leader in the semiconductor industry through successful project deliveries. What You ll Need: Excellent understanding of ASIC digital design flow with hands-on experience in HDL coding. Proficiency in writing synthesis constraints and basics of STA. Knowledge of Lint/CDC/RDC and RTL2GDSII flow. Working knowledge of scripting languages like Perl, Shell, Python, and Tcl. Experience in leading a small team of digital design engineers to execute projects. Knowledge of high-speed/DDR PHY Layer with lane redundancy implementation is highly desirable. Exposure to FIFO, test (ATE and characterization bench), silicon validation, and debugging. Familiarity with Synopsys toolset is highly desirable. Minimum 10 years of relevant digital design experience with at least 3 years as a people manager. B.E/B.Tech/M.Tech in ECE/EE. Who You Are: Strong leadership skills with a proven track record of managing and developing teams. Excellent problem-solving abilities and attention to detail. Effective communication skills, both written and verbal. Ability to work collaboratively in a fast-paced, dynamic environment. Innovative and proactive mindset with a passion for continuous improvement