561 Asic Jobs - Page 8

About Marvell . Your Team, Your Impact Built on decades of expertise and execution, Marvell s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, data center, and networking applications. What You Can Expect As a Senior Staff Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 9+ years of experience running an industry standard EDA tool for PnR signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation . Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

About Marvell . Your Team, Your Impact As member of the physical design team at Marvell you will have the opportunity to work on digital design for ASICs, Physical Implementation, Power Supply integrity checks Low Power design Signoff. Opportunity to work for complete SoC design cycle of ASICs, starting from Architecture definition, feasibility planning/benchmarking for Power/Performance/Area/Yield to end-to-end design/Implementation/Signoff. Opportunity to work on challenging design architecture across Networking, Processor, Computing, automotive, Connectivity and Security, in the technology nodes across 3nm/5nm/7nm and more. What You Can Expect As a Principal Physical Design Engineer (PnR), you will be part of our Implementation team and responsible for running/supporting/maintaining the PnR Flow using industry standard EDA tools for designing the next generation Multi-Ghz high-performance ASIC chips in leading-edge CMOS process technology. Work with design teams across various disciplines such as Digital/RTL/Analog in helping them take their blocks (custom, PnR) through the physical design flow and making sure all the blocks meet timing requirements. Implement/Support blocks with multi-voltage designs through all aspects of RTL to GDS Implementation (Place and Route, static timing, physical verification) using industry standard EDA tools. Work with physical verification team in integrating these blocks seamlessly into full chip partitions. Have a good understanding of global integration and full chip physical verification. Provide technical direction, coaching, and mentoring to employees on the team and others when necessary to achieve successful project outcomes. Writing scripts in TCL and Perl to achieve productivity enhancements through automation is required. HandsOn experience with Bump planning and routing is required. Hands on experience and a solid understanding in all of the following physical design flows and methodologies: Synthesis/PnR, power/EM/IR analysis, power intent (UPF/CLP). What Were Looking For BSEE or MS with 12+ years of experience running industry standard EDA tools for PnR signoff. Understanding of several timing-related concepts is required: setup, hold, clocking, timing corners, timing constraints, noise, and process variation Experience in tape-outs of high performance SOC is required. Physical design knowledge, from netlist handoff to GDS tape out including floor planning, place and route, clock tree synthesis, timing closure and physical verification. Work with logic verification, and design teams to understand and implement the design requirements for clocking and power management. Knowledge of scripting languages such as Perl/TCL is required. Diligent, detail-oriented, and should be able handle delegation of assignments efficiently. Must possess effective communication skills, self-driven individual and a good team player. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-MN1

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job AreaHardware Engineering (Verification) QCT's Bangalore Wireless R&D Bluetooth HW team is looking for experienced Wireless HW design verification engineers to work on Qualcomms best in class chipsets for mobile phones, wearables and IOT. Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, emulation, GLS and Formal techniques. The role also requires deep understanding of the Bluetooth Hardware Architecture. Candidate will require close interactions with Global Design, Systems, SoC, Validation and FW teams for design convergence and required to work with minimal supervision. Candidate must be able to take ownership of IP/Block/Sub-System verification. Incumbent will be analyzing HW design spec and develop a verification test plan/strategy for it, breaking down the work for new features, perform feasibility studies, estimate effort and mitigate risk. The role also required the candidate to mentor new joiners and less experienced colleagues. The candidate will work with design team on RTL debug during Pre-silicon HW development phase. Skills/Experience 6-10 years of strong experience in design verification Strong knowledge of HDLs like Verilog, System Verilog Proven experience of writing efficient constraint random tests Proven experience of building or maintaining a medium to complex SV/UVM environments Strong debugging and analytical skills and independent problem solving ability Proficient in debugging RTL/TB issues using Verdi or similar tools Demonstrate good judgment in selecting methods and techniques for obtaining solutions Strong communication skills, both written and verbal, with ability to evaluate and create testplans detailing complex features and relationships Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communications or related field Minimum Qualifications Bachelors Degree in Engineering in Electronics, VLSI, Communications or related field 6 years of VLSI industry experience in verification Preferred Qualifications Exposure to Bluetooth/BLE Technologies Knowledge on scripting languages such as Perl and(or) Python Skills: Functional Verification, Functional/Code Coverage, SystemVerilog Assertions, Universal Verification Methodology (UVM), Verification IP (VIP) Integration, SoC Integration, Formal checks Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Analyze and evaluate GPU architecture/microarchitecture and workload for performance and power optimizations GPU power modeling and estimation for projection and correlation GPU workload analysis, profiling, and characterizations Analyze, model, and minimize GPU register, logic, memory, and clock power Develop and maintain tests for pre-silicon and post-silicon power verifications. Work closely with multiple teams such as RTL designer, architecture, design verification, compiler, driver, silicon implementation, and post-silicon teams Knowledge of Graphics architecture is a plus Minimum Qualifications: Bachelor's degree or equivalent in Computer Engineering, Computer Science, Electrical Engineering, or related field. 2+ years of experience with ASIC design and verification 2+ years of experience with low-power ASIC optimization Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 7+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 8+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 4+ years of Systems Engineering or related work experience.* Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 3+ years of Systems Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Systems Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field and 1+ year of Systems Engineering or related work experience. Preferred Qualifications: Master's or PhD degree or equivalent in Computer Engineering, Computer Science, Electrical Engineering, or related field. 3+ years of experience with advanced CPU/GPU architecture/microarchitecture design development 5+ years of experience with VLSI design and verification 5+ years of experience with low-power ASIC design techniques Experience with industry tools such as PrimeTime PX and Power Artist Experience with Vulkan, DirectX3D, OpenGL, OpenCL, or Cuda development Experience with GPU driver and compiler development Skills:C/C++ Programming Language, Scripting (Python/Perl), Assembly, Verilog/SystemVerilog, Design Verification

Creating power spec for Qualcomm DSP IPs based on the design spec Power intent development using UPF for DSP IPs based on power spec Power intent validation at RTL level , Gate level (synthesis , PD ) using CLP Fixing power intent based on PA DV feedback for any issue related to power intent Debugging issues related to MV cell insertion during synthesis and modifying UPF accordingly Dynamic and Leakage power projection of DSP IPs during starting of the project Dynamic and Leakage power no. generation using PTPX and tracking the same at different stages of implementation flow Highlighting issues related to dynamic and leakage power mismatch compared to the target and working with Synthesis and PD teams to fix the issues Working with cross function teams (SOC, Sub System etc) for smooth handoff of power intent and Dynamic & leakage power no. at different stages of project execution Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Interfacewith design team to ensure DFT design rules andcoveragesare met. Generating high quality manufacturingATPGtest patterns for stuck-at(SAF), transition fault(TDF)modelsthrough the use ofon-chip test compression techniques. MBISTverification(including repair),testpattern generation through Mentor tool. ATPG(SAF, TDF)and MBISTverification usingunit delay and min/maxtiming cornersimulations. Workwith the Product/Testengineering teams on the delivery of manufacturing test patterns for ATE. Responsible for supporting postsilicondebug effort, issue resolution. Responsible for Diagnostic Tool generation for ATPG,MBISTand bring-up on ATE. Developing,enhancingandmaintainingscripts as necessary Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.Minimum of1-6yearsexperiencein ASIC/DFT- simulation andSilicon validation Detailed knowledge on DFT concepts, pattern simulation, Silicon debugand yield enhancement In depthknowledge andhands-onexperience in ATPG-coverage analysis. In depth knowledge of Memory verification,repairand failure root-cause analysis. Experience withany of thesetoolsisrequired ATPG -TestKompress MBIST- MentorETVerify Simulation -VCS(preferred),modelsim. Expertisein scripting languages such asPerl, shell, etc is an addedadvantage Ability to work in an international team, dynamic environmentwithgood communicationskills Ability to learn and adapt to newtools,methodologies. Ability to do multi-tasking & work on several high priority designs in parallel

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. We are looking for bright ASIC design engineers with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design, flows for high performance SoCs in sub-10nm process for Mobile, Compute and IOT market space. Job Responsibilities: Participate on a project involved in the development of ASICs, with emphasis in Place and Route Implementation, Timing Closure, Low Power, Power Analysis and Physical Verification. Create design of experiments and do detailed PPA comparison analysis to improve quality of results, tuning recipes and setting course for the projects going forward Work closely with RTL design, Synthesis, low power, Thermal, Power analysis and Power estimation teams to optimize Performance, Power and Area(PPA) Tabulate metrics results for analysis comparison Develop Place & Route recipes for optimal PPA Minimum Qualifications 2+ years of High Performance core Place & Route and ASIC design Implementation work experience Preferred Qualifications Minimum 3+ years of experience in PD Extensive experience in Place & Route with FC or Innovus is an absolute must Complete ASIC flow with low power, performance and area optimization techniques Experience with STA using Primetime and/or Tempus is required Proficient in constraint generation and validation Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl, Python, C++ skills are needed Strong problem solving and ASIC development/debugging skills Experience with CPU micro-architecture and their critical path Low power implementation techniques experience High speed CPU implementation Clock Tree Implementation Techniques for High Speed Design Implementation are required Exposure to Constraint management tool and Verilog coding experience

Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience in Verilog/System-Verilog is a must. knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Understanding of constraint development and timing closure is a plus. Experience in Synthesis / Understanding of timing concepts is a plus. Experience creating padring and working with the chip level floorplan team is an added advantage. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Position: ASIC RTL Design Lead (SI90FT RM 3217) Job Description: Innovate, implement, and verify RTL code for complex PHY sub systems dealing with high speed blocks using Verilog/System Verilog knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must. Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution Previous experience with storage systems, protocols, in NAND flash /DRAM controller PHY Basic understanding of PHY system level concepts Experience in PHY architecture, power management and Registers understanding to interact with FW design. Proficient in C, C++, Lint Excellent interpersonal skills and Team Player High level of integrity and commitment to quality and timeliness. Understanding of Hardware Block Diagrams, Schematics Understanding of PHY Architecture document and programming guidelines Understanding of PHY integration guidelines implementation Strong can-do attitude Job Category: Embedded HW_SW Job Type: Full Time Job Location: Bangalore Experience: 9+ YEARS Notice period: 0-30 days

Position: SoC Modeling Engineer (SI36FT RM 3227) ESSENTIAL DUTIES AND RESPONSIBILITIES: Development of C++/SystemC models for complex ASIC IPs, SOCs and Flash Memories. Create System Level Tests and/or Standalone Unit Tests and verify the models. Keen on schedule and quality of the deliverables. Timely support to the stakeholders enabling software bring-up. QUALIFICATIONS: B.E/B.Tech or M.E/M.Tech in Electronics, Computer Science or related streams. 2 - 10 years of relevant experience. REQUIRED SKILLS: Proficient in SystemC/TLM, C++, C. Hands-on experience in development of functional/approximately timed models using SystemC/C++. Hands-on experience in embedded system test development using C. Proven ability to troubleshoot and analyze complex problems. Excellent grasp of Digital Fundamentals. Ability to multi-task and meet deadlines. Should be a Fast learner and a team player. Good written and verbal communication skills. PREFERRED SKILLS: Understanding of Computer Architecture, SoC, CPU (ARC/ARM/RISC-V/etc.,), Bus Architectures, RTOS. Exposure to scripting languages like Python. Experience with Visual Studio programming environment Working Knowledge of Interface Protocols like PCIe, AXI, USB, UFS, NVMe, SD

Location - Gurugram (On-site) Are you passionate about Global Payments Dynamic payment landscapeIn that case, we might have the right opportunity for you! We are seeking an experienced and dynamic candidate to lead our payment APAC unit of Payment Operations. The ideal candidate will be responsible for overseeing all aspects of APAC market payment processing, ensuring efficiency, accuracy, and compliance with local global payment regulatory standards. The candidate will be responsible to ensure exceptional support to our clients. You will support and coordinate with your colleagues, assessing risks controls related to payments. Responsibilities Lead and manage the APAC payment operations team to achieve operational excellence Develop and implement strategies to optimize payment processes and systems Ensure compliance with all relevant regulations and industry standards Collaborate with cross-functional teams to enhance payment solutions and services Monitor and analyze payment trends to identify opportunities for improvement Regularly assess Risks involved in the process and mitigate where possible Manage relationships with key stakeholders globally especially in APAC Your profile As a person you are known for your outmost professionalism, integrity and trustworthiness. You are a curious, collaborative and outgoing person that thrives in different environments. You are comfortable with communicating and taking the lead, and at the same time, where necessary, you are willing to challenge the status quo. While you have a great attention to detail, you can look at different perspectives, see through complexity and summarize issues clearly. What is important to us, is that you are a team player with a flexible mindset and dares to let your person show. We are looking for professionals with an experience in a range of 9-10 years, preferably in an Investment bank or a Global Shared Service Centre. Proven experience in payments domain, at least 9 years In depth knowledge of SWIFT payment types Must have working knowledge of SWIFT ISO standards Must know APAC clearing systems regulatory authorities like NPP, Fast Payments, MAS, ASIC Must be familiar with International Sanctions Embargoes Excellent leadership team management skills Educational Qualification - A post graduate, preferably a diploma/degree in Business management. The candidate must have excellent communication skills. We get curious people invested in the world When you work at Saxo, you become a Saxonian and part of a purpose-driven organisation, where good ideas are always taken seriously, and where you can make a true impact. We are invested in your development, and you can expect a robust career from day one when you join Saxo - no matter which role you take on. You will join 2,500 other ambitious colleagues across 15 countries and become part of an international organisation. Working in Saxo, you will get to meet colleagues from many different cultures and backgrounds, and you should know that we value diversity and inclusion and see it as a genuine source of strength to drive growth, foster innovation and position us for long-term success. We encourage an open feedback culture and supportive team environments enabling employees to grow and fulfil their career aspirations. When you bring passion, curiosity, drive and team spirit, your learning journey will be dynamic and your career opportunities in Saxo will be immense. At Saxo we don t just offer a job - we offer an opportunity to invest in your future! How to apply : Click here to create an account and upload your resume and a short motivation. We look forward to getting to know you better!

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . AMS Verification Lead - Magnetic Sensors The mission of the Magnetic Sensor (MAG) team within the Industrial and Multi-Markets (IMM) Business Group is to develop highly innovative, differentiated and industry leading magnetic sensing technology for industrial and automotive markets. The novel and ground-breaking sensor products are defined and developed by the MAG team, leveraging proprietary processes in the Limerick Fab, meeting the emerging needs of our strategic customers. To help us accelerate our ambitious goals in bringing these emerging technologies to commercial success, the MAG team is seeking a highly driven and dynamic engineer to take a role as AMS Verification Lead responsible for leading package level design verification. The candidate will be responsible for formulating verification strategies, defining verification architecture, flow, methodology and leading, driving and completing verification of our sensor/ASIC solution. Requirements Bachelors/Masters degree in Electronics engineering or equivalent with 8+ years of experience Proven experience in leading full-chip level design verification of mixed signal devices Must have hands on experience in top level metric driven analog mixed signal (AMS) simulations Must have experience in modelling and validation of analog blocks (RNM, Verilogams etc.) Experience in developing verification collateral Familiarity with latest digital verification methodologies like digital mixed signal verification(DMS) using UVM Strong communication skills and ability to collaborate with a global team Role Setup mixed signal verification methodology/flow by interacting with methodology and CAD groups Understand device requirements and come up with traceable AMS and DMS verification plans Lead a team of AMS and DMS verification engineers/contractors Hands on contribution to modelling and AMS top level verification effort Technical support to team members Supervision of the DMS verification effort Interface with global design teams through various phases of verification

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Sr Engineer, Digital Design Job Description Design key digital blocks such as clocks, reset paths, memory controller, NVMs etc. in Verilog/ System Verilog with built-in configurability to allow Power/ Performance/ Area tradeoffs Develop strong understanding of ARM processor cores subsystems (M series associated infrastructure such as caches, interconnect fabric, DMA, MMU, Coresight Debug Trace, TZC) and their integration requirements Design for Test skills on SCAN, MBIST boundary scan, JTAG and ARM DAP interface and general functional DFT understanding. Experience of AFE based projects is an add on. Package Digital IP for seamless integration into design flow at different stages - RTL/ constraints/ CDC waivers, timing wavers, DFT DRCs and waivers, software programming sequence etc. Consolidate curate digital IP for SPI/ I2C/ UART/ JTAG and other slow serial interfaces peripherals ATPG vectors, MBIST and BSCAN post silicon debug support. Develop User Guides for RTL Integration, Synthesis, DFT, PnR, Programming Sequence, characterization etc. Minimum Qualifications Minimum B.E. / B.Tech degree in Electrical/Electronics/Computer science 4 - 8 years of digital logic design and hands-on RTL coding experience using Verilog and SystemVerilog Strong understanding of control path and data-path digital design concepts with an eye for realizing correct by construction solutions Experience with specifying Design Verification (DV) requirements such as test plans, coverage metrics, and evaluate DV quality so as to realize robust design quality Knowledge of Lint, CDC, formal equivalence, DFT concepts, power analysis Experience with developing timing constraints and ability to carry out logic synthesis and Static timing analysis Good interpersonal, teamwork and communication skills to logically effectively drive discussions with teams spread geographically Understanding of standard on-chip interfaces such as APB/AHB/AXI/ Stream protocols is a strong plus Knowledge of Processor/SoC architecture and/or DSP fundamentals is a strong plus Experience with end-to-end ASIC/ SoC product development productization is very desirable Experience in IP integration (memories, IO s, embedded processors, hard macros, Analog IP) Knowledge of Microelectronics concepts Scripting skills in Python, Tcl, C etc Ability to collaborate and work directly with the tool vendors to resolve tools bugs, as well as implement the required improvements Great communication and teamwork skills

Location - Gurugram (On-site) Are you passionate about Global Payments Dynamic payment landscapeIn that case, we might have the right opportunity for you! We are seeking an experienced and dynamic candidate to lead our payment APAC unit of Payment Operations. The ideal candidate will be responsible for overseeing all aspects of APAC market payment processing, ensuring efficiency, accuracy, and compliance with local global payment regulatory standards. The candidate will be responsible to ensure exceptional support to our clients. You will support and coordinate with your colleagues, assessing risks controls related to payments. Responsibilities Lead and manage the APAC payment operations team to achieve operational excellence Develop and implement strategies to optimize payment processes and systems Ensure compliance with all relevant regulations and industry standards Collaborate with cross-functional teams to enhance payment solutions and services Monitor and analyze payment trends to identify opportunities for improvement Regularly assess Risks involved in the process and mitigate where possible Manage relationships with key stakeholders globally especially in APAC Your profile As a person you are known for your outmost professionalism, integrity and trustworthiness. You are a curious, collaborative and outgoing person that thrives in different environments. You are comfortable with communicating and taking the lead, and at the same time, where necessary, you are willing to challenge the status quo. While you have a great attention to detail, you can look at different perspectives, see through complexity and summarize issues clearly. What is important to us, is that you are a team player with a flexible mindset and dares to let your person show. We are looking for professionals with an experience in a range of 9-10 years, preferably in an Investment bank or a Global Shared Service Centre. Proven experience in payments domain, at least 9 years In depth knowledge of SWIFT payment types Must have working knowledge of SWIFT ISO standards Must know APAC clearing systems regulatory authorities like NPP, Fast Payments, MAS, ASIC Must be familiar with International Sanctions Embargoes Excellent leadership team management skills Educational Qualification - A post graduate, preferably a diploma/degree in Business management. The candidate must have excellent communication skills. We get curious people invested in the world When you work at Saxo, you become a Saxonian and part of a purpose-driven organisation, where good ideas are always taken seriously, and where you can make a true impact. We are invested in your development, and you can expect a robust career from day one when you join Saxo - no matter which role you take on. You will join 2,500 other ambitious colleagues across 15 countries and become part of an international organisation. Working in Saxo, you will get to meet colleagues from many different cultures and backgrounds, and you should know that we value diversity and inclusion and see it as a genuine source of strength to drive growth, foster innovation and position us for long-term success. We encourage an open feedback culture and supportive team environments enabling employees to grow and fulfil their career aspirations. When you bring passion, curiosity, drive and team spirit, your learning journey will be dynamic and your career opportunities in Saxo will be immense. At Saxo we don t just offer a job - we offer an opportunity to invest in your future!

About Analog Devices Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures todays innovators stay Ahead of Whats Possible . Learn more at www.analog.com and on LinkedIn and Twitter (X) . Job Posting Title Digitizer Systems Applications Engineer Job Profile Senior Engineer, Systems Integration Engineering Job Description If you are not afraid of a different challenge every day, if you enjoy learning about a wide variety of technologies and if you want to meet and develop relationships with customers all over the world, then a career in Analog Devices Digitizer Systems on Modules (SOMs) Applications Engineering team could be for you. ADIs Systems Applications Engineers enable the interface between the world s leading analog, mixed-signal and digital signal processing provider and its customers. Whether that involves creating content for customers (e.g. hardware, software, or documentation) or supporting customers from their architecture design right through to issues that occur in the field, Systems Applications Engineers play a vital role in every customer engagement at Analog Devices. Essential Responsibilities: Develop digital receivers and transmitters for phased-array, radar, and communication markets Transition high-speed digitizer hardware & software from concept (block diagrams) to productization Engage with customers to translate their system requirements into next generation product definitions Create software scripts to control, evaluate and improve digitizer system-on-modules, which combine ADC/DAC ICs with RF/microwave front-ends, baseband processors, power distribution networks and clock distribution circuitry Guide customers through system integration, troubleshooting and testing Act as a technical liaison between customers, marketing and development teams Analyze signal chains using RF cascade concepts like gain, noise figure, linearity, and input/output power Minimum Qualifications: The candidate should be self-motivated, capable of accepting responsibility and show initiative in identifying and solving challenging technical problems. BS Degree in Electrical/Electronic Engineering with 3+ years of professional experience or equivalent Strong knowledge of RF, analog, digital and mixed-signal fundamentals Good analytical and problem-solving skills Written and verbal communications skills is a must Strong teamwork and inter-personal skills RF cascade analysis (gain, spurious, linearity, noise figure, etc.) and/or mixed signal experience Phased-array, radar, electronic warfare, satellite communication or military communication experience a plus Hardware description language (HDL) and FPGA/ASIC experience a plus Printed circuit board design experience and exposure to PCB design tools a plus Lab diagnostic equipment (spectrum analyzer, signal generators, power supplies, oscilloscopes, etc.) is a must Proficiency in MATLAB, Python scripting and C/C++ software programming a plus

Role Overview: As our Lead, you ll be at the forefront of guiding projects involving cutting-edge mixed-signal circuits, data converters, sub-sampling phase-locked loops, Serdes, and RF circuits. Leveraging your expertise in CMOS and BiCMOS technologies, alongside your proficiency in Cadence custom IC EDA tools, you ll be pivotal in realizing successful layouts. Collaborate closely with cross-functional teams, spanning both local and international domains, to drive project execution and ensure seamless hardware and software system integration. Key Responsibilities: Spearhead the development and coordination of ASICs. Collaborate with vendors and remote teams to ensure timely delivery of ASICs within specified deadlines and budget constraints. Liaise with foundries for Multi-Project Wafer (MPW) release. Conduct thorough evaluation and characterization of ASICs to ensure compliance with the specifications. Requirements: PhD/Master s degrees from esteemed universities. Demonstrated success in leading multiple mixed-signal ICs from concept to production. Over a decade of industrial experience in analog and mixed-signal design. Proven track record of realizing more than 5 ASIC designs. Profound expertise in Cadence custom IC EDA tools. Proficiency in system and behavioralmodeling using MATLAB, System Verilog, Verilog-A/AMS. Desired familiarity with HDL languages Verilog and/or VHDL. Proficient in scripting languages such as Python, Perl, and C; additional skills are a plus. Experience with design, implementation, and development environments for reconfigurable systems, such as FPGAs, is advantageous. Knowledge of silicon manufacturers and various CMOS process technologies is beneficial. Desired Aptitudes: Proficient leadership and management skills, capable of fostering high-performance teams. Strong individual contributor with a collaborative mindset, able to work effectively within teams. Adaptability to diverse customer bases and openness to periodic local and international travel. Aptitude for quickly learning new technologies and applications. Exceptional writing, verbal, and interpersonal communication skills. Competence in developing innovative solutions and effectively identifying problems. Understanding of production processes to ensure quality and robustness.

. Over the last decade, INOPC has evolved to become the largest engineering hub serving more than 40 countries across different energy sectors. The team caters to the four business units Transformers, Grid Integration, Grid Automation, High Voltage and has successfully executed engineering and commissioning for projects in more than 80 countries. Mission Statement: The technical marketing engineer for Mission Critical telecommunication Solutions (MCS) has the global responsibility to enable the Pre-Sales Sales community of the different regional HUBs to understand technical market requirements for wired telecommunication networks and ensure customer interaction in line with global solution/product strategy. Support sales organizations in driving sales by your technical expertise . Provide relevant customer market inputs to product management and RD activities, ensuring market alignment and relevance . Your responsibilities: Design HVDC Protection Logics and Algorithms for HVDC Protects across the globe. Develop Protection Functions / Solutions for HVDC Project. Perform Power system protection coordination based on Project requirement to optimize fault detection algorithms and setting philosophies. Support projects in resolving the issues related to Control and Protection Functions. Design HVDC Protection Logics and Algorithms for HVDC Protects across the globe. Develop Protection Functions / Solutions for HVDC Project. Perform Power system protection coordination based on Project requirement to optimize fault detection algorithms and setting philosophies. Support projects in resolving the issues related to Control and Protection Functions. Coordinate with different stakeholders across the business units to get inputs to optimize the HVDC solutions. Living Hitachi Energy s core values of safety and integrity, which means taking responsibility for your own actions while caring for your colleagues and the business. Your background: Bachelor s degree in electrical and Electronics w ith a minimum work experience of 6+ years in Control and Protection system . You should have knowledge in PSCAD, MATLAB, or any other Simulation Software . You must have b asic knowledge on IEEE / IEC standards . You should have experience in substation environment and protection application. Experience in technical tender support or bidding is preferrable. Experience in substation environment and protection application is an added advantage. Self-starter caliber who could own tasks through to completion. Excellent written and verbal communication skills. .

Broadcoms Central Engineering Group (CEG) is looking for an experienced, energetic and self-driven professional to join our team as a senior modeling engineer for the development and improvement of functional, timing, power, and DFT simulation models. This role will focus on authoring, debugging, and optimizing memory IP (SRAM, RF, CAM, ROM, etc.) EDA models used in ASIC-like design flows by chip teams throughout the company. This is a senior position with the expectation that the candidate can lead projects, proactively navigate complex technical issues, be able to work autonomously, and collaboratively participate in the establishment of strategic objectives. The candidate must have abilities to prioritize well, communicate clearly and concisely, deliver high quality solutions on-time, and possess excellent problem solving skills. This person will be expected to work across multiple facets of projects, have experience with ASIC development, and juggle multiple responsibilities at the same time exhibit excellent multitasking, context switching, and time management skills. Responsibilities: Candidate will Lead memory modeling and compiler development projects working closely with design teams in an environment highly charged with technical complexities and dynamic schedule challenges. Be expected to demonstrate skills and abilities to lead and drive results improvements, multitask and deliver high quality solutions in a timely fashion. Write model templates for integration into memory compilers to generate models used in DFT/CAD tools used in ASIC development flows. Participate in forums for model development, improvement and reviews, and will serve as a knowledge resource for peers, colleagues, and subordinates in the organization. Be expected to communicate well, document well, prioritize tasks and handle the multiple facets of model development projects independently to meet the business goals and commitments. Work to improve memory models and model generation flows for better performance, user experience and quality. Work directly with IP design teams, compiler teams and tool vendors globally to help resolve model related issues, and find timely solutions. Respond to library support requests and address tickets on model issues from product teams across Broadcom. Qualifications : The minimum engineering experience required is typically a BS degree in EE/CS/CE with programming/coding experience with 8+ years of industry experience, or an MS degree with 6+ or Ph.D. degree in EE/CS with 3+ years of industry experience. Have at least 3 years experience using Linux systems; possess excellent knowledge of Linux commands, file systems, and job execution. Strong preference for 5+ years of experience in Verilog modeling skills Static Dynamic timing analysis knowledge. Experience with chip design tools and design flows, such as: DFT: Tessent, LogicVision, Modus, manufacturing test flows: at-speed scan test, Logic BIST, Memory BIST Synthesis: Design Compiler, Genus. Simulation: VCS, Questa, Verilog, waveform viewers, and simulation debug. STA: Primetime, Tempus, Celtic, Velocity. Power Analysis: Redhawk, Voltus, PowerCompiler, Power Artist. PR: ICC, Innovus, Olympus, Encounter. Conversant with Verilog / RTL / Behavioral / Timing / Power / DFT / ATPG / Synthesizable model development for SRAMs/RF/CAM/ROM, etc. memories. Experience in writing directed test bench in verilog for model verification. Knowledge and experience using simulators - NC, VCS, ModelSim, ESPCV is a must. Familiarity with memory model verification/QC flow is required. Scripting flow automation, Perl, Python, Tcl, Shell programming skills are required. Able to work in agile and dynamic development environments. Excellent written and verbal communication skills. Skilled multi-tasking abilities and context switching skills are a must. Strong analytical, problem solving and quick learning skills are required. Good team player, methodical, eye for detail, independent, well organized, and have the ability to remain calm and composed in high pressure situations. .

Apply to this job As an ASIC Firmware Engineer Manager, you will be responsible for delivering firmware for next-gen ASIC platforms. In this role, you will be responsible for driving definition of architecture and implementation designs for our firmware products. You will also play a key role in ASIC roadmap, from the initial architecture and design phase to deployment in the data center fleet. Our team is responsible for developing and delivering Boot firmware, low-level device drivers, and real time operating system (RTOS) based platform firmware for next-generation data center silicon.We seek a leader with cross-functional partnership experience and proven track record in building reliable and performant complex ASICs. They should have experience with firmware development lifecycle, CI/CD and test automation, tooling, production deployments, debugs, root-cause analysis, and vendor relationships. ASIC Engineering Manager - Infra Specialist Responsibilities Manage the Silicon Firmware team, working closely with design, design verification, validation, platform software, system and data center teams to deploy firmware in our production fleet Partner with cross-functional teams such as RTL design, verification, emulation, validation teams for building next-generation silicon, and design firmware, and support rapid deployment into Meta data centers Identify candidates, hire, schedule, support, mentor and train a team of ASIC engineers in order to scale our infra silicon to satisfy Meta application requirements Contribute to, analyze, review SOWs from vendors, supporting documentation, requirements sets that meet the needs of internal customers. Partner with technical program management and supply chain team members to manage external development partners, suppliers and vendors. Minimum Qualifications B.S. or M.S. degree in Computer Engineering or Electrical Engineering or related technical fields 15+ years of experience working in an ASIC Firmware Development, Production Support, CI/CD and complete life cycle of ASIC firmware 5+ years of experience as a People Manager Experience working across multiple projects and adjusting priorities in partnership with stakeholders Experience in C/C++ or other programming languages Preferred Qualifications Experience in Firmware development, Firmware Architecture and team management Experience in Root-causing, Debugging Silicon issues in Production Environments Experience working with vendors on Failure analysis, Root-cause analysis and Firmware releases to address issues Post-deployment Knowledge of Embedded Systems, Embedded Software, Video Applications, Networking Stack and/or AI/ML system understanding About Meta . Equal Employment Opportunity . Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form .

Exp on Firewall, Router & Switches config is must Knowledge on Firewall, Server Load Balancers & Link Load Balancer config is mand Exp in VLAN config VXLAN config on ASIC switches Exp with monitoring, network diagnostic & network analytics tools Required Candidate profile CCNP/ CCNA cert will get added advantage. 8 yrs. exp as Network Admin Exp with monitoring, network diagnostic & network analytics tools Understanding of network protocols (IPSEC, HSRP, BGP, OSPF)

SOFTWARE DEVELOPMENT ENGINEER 2 THE ROLE: AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partners PREFERRED EXPERIENCE: Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with Windows, Linux and/or Android operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent Benefits offered are described: AMD benefits at a glance .

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Function The candidate would be joining a team with deep expertise in designing IP and wireless sub-systems for market leading products. In this role, the candidate would be working on cutting edge next-generation Wireless PAN technologies (Bluetooth, UWB, Thread etc.) for connectivity solutions within mobile phones, wearables, IOT and Voice & Music chips. The candidate would be a part of Bluetooth IP Design team and will be involved in IP and sub-system development. The role requires working on IP & sub-system development, latest technology nodes and on all aspects of the VLSI development cyclearchitecture, micro architecture, RTL design and integration. Close interactions with system architecture, verification, SoC Design, Validation, Synthesis & PD teams are required for design convergence. Skills/Experience 3-6 years of experience in the design of complex ASICs Strong expertise in RTL; coding complex designs using Verilog/SV Exposure to low power design methodology and designs with multiple clock domains Strong debugging, analytical skills and strong communication skills, both verbal and written Hands-on experience in front-end design tools Minimum Qualifications Bachelors or Masters Degree in Engineering in Electronics, VLSI, Communications or related field 3 years of VLSI industry experience in Digital Design Preferred Qualifications Exposure to Bluetooth/BLE Technologies and scripting languages like Perl and/or Python Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Software Engineering General Summary: Qualcomm Cloud Business Unit is looking for an experienced software engineer in the areas of Linux User-space for Machine Learning Use cases. The development target is Qualcomm high-performance inference accelerator AI100 and related products. The candidate should be familiar with developing SW using modern C++(11,14,17), Object Oriented Design, Design Patterns Principles, Linux user-mode drivers, inter-process communication such as gRPC, protocol buffers, system profiling, code optimization and tool development. Responsibilities include Linux software architecture and design, development, software integration, functional and performance testing. Ideal candidates for this position will demonstrate the following: 3+ years experience with Linux user-space development, including IOCTL interfaces, API development and multi-threaded processing. 3+ years experience with development in Modern C++(11,14,17) including debug and testing. Proficiency across multiple languages (C, C++, Python) and experience in unit testing tooling for C and C++ development, including googletest. Experience with real-time embedded operating systems. Experience in requirement capture and traceability. Experience in UML design capture & analysis. Experience with development of peripheral drivers. Knowledge of RTOS, SoC architecture (core, cache, memory, bus architecture, IOs, etc.) and common hardware blocks Experience with Source Code and Configuration management tools, git knowledge is required Willingness to work in a structured software development environment with ability to work on low-level implementation (code & test) Good English communication (written and verbal) and positive interpersonal skills Familiar with inter-process communication architecture such as gRPC. Software development and debug tools including compilers, profilers, source control systems, emulators, JTAG and serial debuggers, and logic analyzers Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Systems, Computer Science, or related field. 2+ years of academic or work experience with Programming Language such as C, C++, Java, Python, etc. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.