776 Asic Jobs - Page 8

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Overview Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary 8-15 years of relevant ASIC design experience Solid experience in digital front end design for ASICs Expertise in RTL coding in Verilog/VHDL/SV of complex designs with multiple clock domains Expertise with various bus protocols like AHB, AXI and NOC designs Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Experience in mobile Multimedia/Camera design is a plus DSP /ISP knowledge is a plus. Working knowledge of timing closure is a plus Expertise in Perl, TCL language is a plus Expertise in post-Si debug is a plus Good documentation skills Ability to create unit level test plan General Should possess good communication skills to ensure effective interaction with Engineering Management and mentor group members. Should be self-motivated and good team working attitude and need to function with little direct guidance or supervision Responsibilities Digital design and development (RTL) working in close collaboration with Multi-site leads Developing the micro architecture and implementing the design using Verilog/SV. Integrate and deliver complex subsystem to SoC Design and implement defined tasks independently. Work in close coordination with Systems, Verification, SoC team , SW team, PD & DFT teams to get the goals completed. Analyze reports/waivers or run various tools Spyglass, 0-in, DC-Compiler, Prime time, synthesis, simulation etc Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Minimum of 7+ years experience in the area of ASIC/DFT -In depth knowledge of DFT concepts -In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis -Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations -Expertise in scripting languages such as perl, shell, etc. -Experience in simulating test vectors -Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax) -Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus -Ability to work in an international team, dynamic environment -Ability to learn and adapt to new tools and methodologies. -Ability to do multi-tasking & work on several high priority designs in parallel. -Excellent problem solving skills -Excellent communication and team work skills and good English is required Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in. You will be joining a successful engineering team whose deliveries can be found in billions of mobile, compute and IoT products worldwide. Based out of Qualcomm's Bangalore office, this role offers a position in Low Power controller IP cores and subsystem digital design targeted for variety of industry leading Snapdragon SoCs for mobile, compute, IoT and Automotive markets. Key Responsibilities Micro-architecture and RTL design for Cores / subsystems. Work in close coordination with Systems, Verification, SoC, SW, PD & DFT teams for design convergence. Enable SW teams to use HW blocks. Qualify designs using static tool checks including Lint, CDC, LEC and CLP. Synthesis, LEC and Netlist CLP Report status and communicate progress against expectations. Preferred Qualifications 5 to 10 years of strong experience in digital front end design (RTL design) for ASICs Expertise in RTL coding in Verilog/SV/VHDL of complex designs with multiple clock domains and multiple power domains Familiar with UPF and power domain crossing Experience in Synthesis, Logical Equivalence checks, RTL and Netlist CLP Familiarity with various bus protocols like AHB, AXI, SPMI, I2C, SPI Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint/CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow to interact with DFT and PD teams Expertise in Perl/TCL/Python language Experienced in database management flows with Clearcase/Clearquest. Expertise in post-Si debug is a plus Excellent oral and written communications skills to ensure effective interaction with Engineering Management and team members. Team player, self-motivated, should be able to work with minimal supervision. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

AECG ASIC DFx - SILICON DESIGN ENGINEER 2 THE ROLE: As a Silicon Design Engineer, you will work with DFT experts and designers to verify DFT logic. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem - solving skills and are willing to learn and ready to take on problems . KEY RESPONSIBILITIES: Drive DFT verification for the block and write tests and assertions to verify the design Coordinate with RTL engineers to implement logic design for better clock - reset controls and verify the various DFT aspects of the design Responsible for verification quality metrics like pass rates, code coverage and functional coverage Responsible for delivering high quality of DFT RTL through LINT, SGDFT, CDC, LEC and RDC checks Responsible for block level ATPG achieving high scan coverage, Scan GLS with and without SDF. Drive MBIST verification for the block Debug block level issues and drive the RTL fixes PREFERRED EXPERIENCE: Knowledge of DFT techniques such as JTAG/IEEE standards, Scan and ATPG, memory BIST/repair or Logic BIST Good working knowledge of UNIX/Linux and scripting languages (e.g. TCL, c-shell, Perl) Familiar with Verilog design language, Verilog simulator and waveform debugging tools Knowledge of EDA tools/methodology, such as synthesis, equivalency checking, static timing analysis is a plus. Strong problem-solving skills. Team player with strong communication skills. ACADEMIC CREDENTIALS: Bachelor s or M aster s degree in computer engineering/Electrical Engineering #LI-RP1

Staff Verification Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12151 Remote Eligible No Date Posted 15/07/2025 Description Staff Verification Engineer, Interface IP We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: An experienced and highly skilled ASIC Digital Verification Engineer with a passion for ensuring the highest quality in digital design. You have a deep understanding of verification methodologies and are proficient in using advanced verification tools and techniques. Your expertise allows you to work independently, taking on complex challenges and delivering innovative solutions. You are detail-oriented, with a strong analytical mindset, and can communicate effectively with various stakeholders. Your ability to mentor and lead junior engineers is a testament to your extensive experience in the field. You thrive in a collaborative environment and are committed to continuous learning and improvement. What You ll Be Doing: Designing and implementing verification environments to ensure the correctness of Interface IP protocols. Creating and executing detailed test plans to verify complex ASIC designs. Developing and maintaining verification IP and testbenches using SystemVerilog and UVM. Collaborating with design and architecture teams to identify and fix bugs. Performing functional coverage analysis and driving coverage closure. Staying current with the latest verification methodologies and tools to continually improve processes. Mentoring and guiding junior verification engineers in best practices and methodologies. The Impact You Will Have: Ensuring the delivery of high-quality, reliable ASIC designs that meet customer specifications. Enhancing the robustness and efficiency of our verification processes and methodologies. Contributing to the successful launch of Interface IP products, impacting various industries. Driving innovation and excellence within the verification team. Improving the overall performance and functionality of Synopsys IP offerings. Fostering a culture of continuous improvement and technical excellence. What You ll Need: Extensive experience in ASIC digital verification, specifically with Interface IP protocols. Proficiency in SystemVerilog and UVM methodologies. Strong understanding of digital design and verification concepts. Experience with simulation tools such as VCS, ModelSim, or similar. Excellent problem-solving skills and attention to detail. Who You Are: Detail-oriented with a strong analytical mindset. Excellent communicator, able to convey complex technical concepts clearly. Collaborative team player who thrives in a dynamic environment. Proactive and self-motivated, with a commitment to continuous learning. Mentor and leader, capable of guiding and developing junior engineers. The Team You ll Be A Part Of: You will join a dedicated team of engineers focused on the design and verification of high-performance digital IPs. Our team is committed to innovation, quality, and excellence, working collaboratively to push the boundaries of technology. We value continuous learning and professional growth, providing ample opportunities for development and advancement. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. *Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

SE NIOR SILICON DESIGN ENGINEER THE ROLE : We are looking for an adaptive, self-motivative design verification engineer to join our growing team. As a key contributor , you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The V erification Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/ time zone s . You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. Job Description: The verification team is looking for a Senior Design Verification Engineer to contribute on the verification of Network on Chip IPs, Subsystems having adequate knowledgeble on the boot flow. The individual will help architect, develop and use simulation and/or formal based verification environments, at block, subystem , Fulchip level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystem and SOC designs. Responsibilities: Plan verification of complex digital design blocks by fully understanding the architecture and design specification Interact with architects and design engineers to create a comprehensive verification testplan Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools Debug tests with design engineers to deliver functionally correct design blocks Identify and write coverage measures for stimulus quality improvements Perform coverage analysis to identify verification holes and achieve closure on coverage metrics General requirements: Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification Strong understanding of different phases of ASIC and/or full custom chip development is required Experience in block level NOC (Network on Chip) verification is a plus Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus Special Requirements : Architect and implement verification environment using advanced verification methodology such as UVM or SystemVerilog; Test plan development and test writing; Analyzing and debugging failures using simulation tools such as Synopsys VCS or DVE to verify hard IPs, FPGA fabric or System-on-Chip; Functional coverage writing, coverage collection and analysis, coverage closure; Writing System Verilog assertions and assertion based verification; and, Running regressions, automation using scripting languages such as PERL and verification closure Education Requirements: Masters / B.Tech / M.Tech Years of Experience : 5+ Years #LI-SG

Job Overview: As a part of Arms Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. Responsibilities: Synthesis, DFT , Floorplan , Place and Route , CTS and Optimization of CPU cores, system interconnect and other ARM Designs. RTL-GDS closure for Hard Macro Analyze design timing, area and power to help improve the quality of ARM Design. Analyze DRC/LVS/PERC/ERC using Calibre and perform Layout edit for Physical Verification closure. Analyze Timing using primetime and perform Timing ECO for design closure Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results Required Skills and Experience : Bachelors or Master s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 3+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification Strong Communication and Problem Solving Skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Experience working closely in top and block level Synthesis, DFT, Floor planning, Place and Route, CTS, logical and physical optimization, timing closure and power analysis flows. Proven programming and scripting skills eg. Tcl, Perl, Python, Make. Nice To Have Skills and Experience : Knowledge around Arm based SoCs! Experience with a wide range of programming, scripting & data presentation languages Eg. Tcl, sh, csh, make, R, C, C++, Java, JS, HTML, Perl, Python, Ruby. Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design. Experience with ATPG tools/and or production testing. In Return: At Arm, we are guided by our core beliefs that reflect our creative culture and guide our decisions, defining how we work together to surpass ordinary and shape extraordinary. Accommodations at Arm At Arm, we want our people to Do Great Things. . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm Hybrid Working at Arm #LI-BB1 Accommodations at Arm At Arm, we want to build extraordinary teams. . To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations. All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation. Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility. Please email us about anything we can do to accommodate you during the recruitment process. Equal Opportunities at Arm

Meet the Team The Cisco Distributed System Engineering (DSE) group is at the forefront of developing products that power the largest networks in the world. The networking industry is going through a massive transformation to build the next generation infrastructure to meet the needs of AI/ML workloads and continuously increasing internet users and application. We are uniquely positioned to capture that market transition. This team builds products by harnessing the potential of open-source technologies while pushing the boundaries on Systems and Silicon Architecture. They are the developers and leaders who are passionate about tackling complex technology, building large scale distributed systems and comfortable working with open-source communities and technologies. Your Impact You will be involved with a fast-paced work environment and responsible for end-to-end product development and production support. As a technical lead, you will be involved on the following activities. Software Development Integration: Lead the design, development, and deployment of software solutions leveraging SONiC to interface with hardware infrastructure and platform-level components. Develop and maintain platform adaptation layers for seamless integration between SONiC and underlying hardware (e.g., ASICs, BMC, and other platform elements). Collaborate with hardware teams to enable optimal hardware-software interactions and expose hardware capabilities through SONiC interfaces. Write, review, and optimize code for critical system modules, drivers, and APIs supporting high-performance data planes and control planes. System Architecture and Design: Define the technical architecture to integrate SONiC with platform infrastructure, ensuring scalability and high availability. Design robust interfaces between SONiC and platform-specific management/control modules (e.g., telemetry, diagnostics, and security components). Lead efforts to optimize resource utilization, power efficiency, and operational stability of the network platform. Leadership and Mentorship: Provide technical direction to the development team, mentoring junior and mid-level engineers on software engineering best practices and advanced networking concepts. Coordinate cross-functional activities between software, hardware, QA, and systems integration teams. Drive code reviews, technical discussions, and issue resolution to ensure timely and quality deliverables. Collaboration and Stakeholder Engagement: Act as a key liaison with open-source SONiC communities, contributing to upstream development and leveraging community innovations. Collaborate with product management and customers to understand use cases, gather requirements, and align deliverables with business objectives. Lead the evaluation and adoption of new tools, technologies, and methodologies to accelerate development and testing cycles. Minimum Qualifications Around 15 years of experience in software development within the networking or telecommunication industry Software development experience with Linux based platforms or other like network operating systems such as SONiC Experience with platform infrastructure such as ASIC drivers, NPU, BMC, Optics and network OS development Experience working with virtualization, containerization, and orchestration frameworks such as Docker, Kubernetes and/or similar Experience leading teams or technical projects in a complex development environment Preferred Qualifications Experience in CI/CD pipelines and automated testing frameworks Experience with platform level security requirements and compliance frameworks Understanding of telemetry systems and software-defined networking (SDN) Exposure to SONiC or experience working with the SONiC open-source community Knowledge of hardware abstraction layers and SDKs from major networking silicon providers (such as Broadcom, Marvell, Mellanox etc) #WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection we celebrate our employees diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer 80 hours each year allows us to give back to causes we are passionate about, and nearly 86% do! Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us! Message to applicants applying to work in the U.S. and/or Canada: When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidates hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

Minimum Qualifications : Around 13 years of experience in software development within the networking industry. Good experience in developing software in C, especially in the context of network protocols and systems. Experience in data-plane forwarding technologies such as L2, L3, segment Routing and/or MPLS. Experience working on data path programming on custom or merchant ASIC of any networking system. Ability to debug complex issues in router pipeline. Bachelor s degree in computer science or related field. Preferred Qualifications : Experience in CI/CD pipelines and ability to automate as we develop. Knowledge of hardware abstraction layers and SDKs from major networking silicon providers (such as Broadcom, Marvell, Mellanox etc.) Ability to debug complex issues in NPU pipeline. Experience in any Cisco OS - XR, XE or NXOS would be a plus #WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all. Our passion is connection we celebrate our employees diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer 80 hours each year allows us to give back to causes we are passionate about, and nearly 86% do! Message to applicants applying to work in the U.S. and/or Canada: When available, the salary range posted for this position reflects the projected hiring range for new hire, full-time salaries in U.S. and/or Canada locations, not including equity or benefits. For non-sales roles the hiring ranges reflect base salary only; employees are also eligible to receive annual bonuses. Hiring ranges for sales positions include base and incentive compensation target. Individual pay is determined by the candidates hiring location and additional factors, including but not limited to skillset, experience, and relevant education, certifications, or training. Applicants may not be eligible for the full salary range based on their U.S. or Canada hiring location. The recruiter can share more details about compensation for the role in your location during the hiring process. U.S. employees have access to quality medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, short and long-term disability coverage, basic life insurance and numerous wellbeing offerings. Employees receive up to twelve paid holidays per calendar year, which includes one floating holiday (for non-exempt employees), plus a day off for their birthday. Non-Exempt new hires accrue up to 16 days of vacation time off each year, at a rate of 4.92 hours per pay period. Exempt new hires participate in Cisco s flexible Vacation Time Off policy, which does not place a defined limit on how much vacation time eligible employees may use, but is subject to availability and some business limitations. All new hires are eligible for Sick Time Off subject to Cisco s Sick Time Off Policy and will have eighty (80) hours of sick time off provided on their hire date and on January 1st of each year thereafter. Up to 80 hours of unused sick time will be carried forward from one calendar year to the next such that the maximum number of sick time hours an employee may have available is 160 hours. Employees in Illinois have a unique time off program designed specifically with local requirements in mind. All employees also have access to paid time away to deal with critical or emergency issues. We offer additional paid time to volunteer and give back to the community. Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components. For quota-based incentive pay, Cisco typically pays as follows: .75% of incentive target for each 1% of revenue attainment up to 50% of quota; 1.5% of incentive target for each 1% of attainment between 50% and 75%; 1% of incentive target for each 1% of attainment between 75% and 100%; and once performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation. For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.

Primary skills: ASIC / DFT / Simulation / Validation Mandatory skills: VLSI Design For Testability - DFT & worked in at least one Full chip DFT Experience with tools: ATPG - TestKompress, MBIST - MentorETVerify, Simulation - VCS (preferred), ModelSim

We are seeking highly motivated DFT engineer to be part of Hardware team. Join a great team of engineering professionals who are involved in development, validation, and delivery of DFT patterns for IBM’s chip design team. As a member of DFT team you will be required but not restricted to pattern generation, simulation, validation, characterization, delivery to TAE, IBM’s Hardware Bring-up and Silicon Debug. You will play a key role in silicon bring-up, workload execution and validation. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Proficiency inC and Pythonfor validation and automation Hands on experiencec in Writing/ maintaining test programs and automation scripts using C and Python Experience in chip bring-up /debug Experience in chip-level throttling issuesincluding power, thermal, and frequency-related behavior Knowledge on Analyzing trace data/logs and on-chip debug outputs for failure root cause Should be able to InterpretVerilog RTLto support functional and performance debug Collaborate with RTL, firmware, validation, and DFT teams for end-to-end issue resolution Strong understanding ofchip boot flowsandbring-up sequences Familiarity withassembly-level debuggingon RISC/V, ARM, or other architectures Ability to read and debugVerilog RTL code In depth understanding of chip internals, including resets, clocking, and register programming Preferred technical and professional experience Experience inpost-silicon validation, emulation or pre-silicon environments Exposure to firmware-hardware interactions Knowledge of debug infrastructure and on-chip monitoring tools Familiarity with version control tools like Git

You will need a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. Additionally, you should have at least 4 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog. It is also essential to have experience in the design and development of Security or Audio blocks, as well as with a scripting language like Perl or Python. Familiarity with DSI2 or MIPI C/D Phy is necessary. Ideally, you should have a Master's or PhD degree in Electrical Engineering, Computer Engineering, or Computer Science. Preferred qualifications include experience with ASIC or FPGA design verification, synthesis, timing/power analysis, and DFT. Knowledge of high-performance and low-power design techniques, assertion-based formal verification, FPGA and emulation platforms, and SOC architecture is also beneficial. As a part of the team working on custom silicon solutions for Google's direct-to-consumer products, you will play a crucial role in shaping the future of hardware experiences. Your contributions will drive innovation behind products that are beloved by millions worldwide, delivering exceptional performance, efficiency, and integration. The Platforms and Devices team at Google focuses on various computing software platforms and first-party devices and services. By researching, designing, and developing new technologies, the team aims to enhance user interaction with computing, making it faster and more seamless, and creating innovative experiences for users globally. Your responsibilities will include collaborating with architects to develop microarchitecture, performing Verilog/SystemVerilog RTL coding, functional/performance simulation debugging, and conducting Lint/CDC/FV/UPF checks. You will also participate in test planning and coverage analysis, develop RTL implementations meeting power, performance, and area goals, and be involved in synthesis, timing/power closure, pre-silicon, and post-silicon bring-up. Additionally, you will create tools/scripts to automate tasks, track progress, and collaborate with multi-disciplined, multi-site teams in Architecture, RTL design, verification, DFT, and Partner Domains.,

You Are: A highly-skilled ASIC Digital Verification Engineer with a passion for developing functional verification solutions for RTL based IP Cores. You are experienced in handling complex protocols and thrive in a collaborative international environment. With over 15 years of experience, you possess a deep understanding of verification methodologies and are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM). You are adept at making architectural decisions, implementing test benches, and driving innovation in verification solutions. You are a proactive team player with excellent communication and problem-solving skills, ready to contribute to cutting-edge projects in AI/machine learning, automotive, and server farm applications. What You ll Be Doing: Making architecture decisions on test bench design. Writing verification plans and specifications. Implementing test bench infrastructure and writing test cases. Utilizing a coverage-driven methodology. Providing technical leadership and guidance to the team. Collaborating with architects, designers, and other verification team members across multiple sites worldwide. The Impact You Will Have: Ensuring the reliability and performance of IP Cores used in critical applications. Driving innovation in verification methodologies and solutions. Contributing to the development of industry-leading technologies in AI, automotive, and server farms. Enhancing productivity and throughput through effective verification strategies. Maintaining high standards of quality and functionality in IP verification. Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement. What You ll Need: Extensive knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience in creating test environments from functional specifications using UVM/VMM/OVM. Proficiency in SystemVerilog (SV), UVM, and object-oriented coding and verification. Ability to provide innovative verification solutions for enhanced productivity and performance. Experience with scripting languages like C/C++, TCL, Perl, Python is an added advantage. Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage

CPU Performance Validation Engineer THE ROLE: The person will be part of AMDs CPU Performance Validation team. This team is part of AMDs global CPU Performance teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86 CPU architecture and microarchitecture ranging from CPU pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment. We highly encourage people with a creative bent of mind and with a natural ability to dive into the details. This team is a perfect place for people who can understand the present and envision the future. If you find yourself to be a person who wants to go that extra mile to refine an existing process and also understands the opportunities to make it better, if you are the one who has innovative ideas in your brain waiting to find a proper stage to come out, we can offer you the perfect ground for that. THE PERSON: Should have excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment. Continuous learning has always been the moto in this ever changing industry. An ideal person for this role should be a self-learner and always ready to upgrade his/her skills to stay abreast with the technology. The team looks for superstars but also believes in nurturing you into one. Collaboration is the key to success. Ideal candidate should learn at a great pace, deliver what is expected and also share your learning in the team to help the overall growth. It s always We before Me in the team KEY RESPONSIBILITIES: Responsible for building infrastructure for performance verification and verify performance of X86 processor. Writing specific targeted tests to measure the performance of the processor Involves having a deep understanding of processor micro-architecture and triaging performance issues in RTL and simulator Skillset Debug triage of failures from simulation and emulation environment for CORE or sub level regressions. Writing automatized triages in Perl/Ruby and creating tools using perl/ruby or AMD verification methodology (primarily in C++) to enhance the functional debug and triage process. On a need basis, work on Post-Si bug recreation PREFERRED EXPERIENCE: Experience: 2-5 years experience in processor/ASIC performance correlation. Experience in micro-architecture testing for modern high-performance processors. Experience in writing tests and building infrastructure that tests performance of modern processors. Experience in application performance analysis Programming/Scripting Skills C, C++, Perl, Python. Solid background and understanding of Digital Design, RTL design , improving model performance and Processor Architecture Strong troubleshooting, analytical and debug skills. Prior experience in performance correlation of Processor subsystems is a plus. Excellent knowledge of computer architecture with relevant research and project work or industry experience Strong programming skills (C/C++ and assembly) Basic knowledge of Verilog ACADEMIC CREDENTIALS: Bachelors/Masters in Computer Science/Electrical/Electronics Engineering with relevant course and research work LOCATION: Bangalore #LI-RR1 #LI-Hybrid AMD does not accept unsolicited resumes from headhunters, recruitment agencies or fee based recruitment services. AMD and its subsidiaries are equal opportunity employers and will consider all applicants without regard to race, marital status, sex, age, color, religion, national origin, veteran status, disability or any other characteristic protected by law. EOE/MFDV

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll Do: Perform hands-on physical design and physical verification tasks across projects in advanced process nodes. Manage project-specific ASIC development flow setup and maintenance. Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities. Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database. Ensure correct IP and pad-ring integration in block and flat designs. Mentor junior PD/PV team members and oversee their tasks. You will be reporting to ASIC Design Director. What Youll Need: Minimum 8+ Years of experience in ASIC/ SoC Physical Design. Skills - have working experience in advanced FinFET node designs. Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must. Education - B. Tech /M. Tech in Electronics Engineering. "Hybrid work environment" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Hybrid Working Model Provisions to pursue advanced education from Premium Institute, eLearning content providers. Medical Insurance and a cohort of Wellness Benefits Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Design Verification Engineer (5 + years experience) Company: HCL Tech Job Summary: We are looking for a talented and motivated Design Verification Engineer to join our team and play a key role in ensuring the functionality and quality of our next-generation integrated circuits (ICs). This position offers the opportunity to work on challenging projects while utilizing your expertise in verification methodologies and tools. Responsibilities: Develop and implement comprehensive verification plans using industry-standard methodologies (e.g., UVM) Design and write robust verification environments (testbenches) to achieve high code coverage Utilize simulation tools (e.g., ModelSim, Cadence Incisive, Synopsys VCS) to verify RTL functionality Debug and analyze verification failures to identify the root cause of design issues Collaborate with RTL design engineers to resolve functional bugs and ensure design revisions meet verification requirements Participate in code reviews and ensure adherence to verification coding standards Stay up-to-date with the latest verification tools and methodologies Qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master's degree a plus) 5-+ years of experience in design verification for ASICs or SoCs Strong understanding of digital design principles (combinational logic, sequential logic) Proven ability to develop and debug complex verification environments Proficiency in Verilog or VHDL with experience in verification methodologies (e.g., UVM) Experience with simulation tools and scripting languages (e.g., Python, Perl) is a plus Excellent analytical and problem-solving skills Strong communication and collaboration skills to work effectively in a team environment Benefits: Competitive salary and benefits package Opportunity to work on leading-edge technologies and projects Collaborative and dynamic work environment Potential for professional development and career advancement e & responsibilities

About the Company: Founded with the vision of building a runtime reconfigurable, future-proof processor, Morphing Machines is a fabless semiconductor company working on a ground-breaking technology that will transform the chip design landscape. Morphing Machines patent protected IP, REDEFINE, can concurrently accelerate heterogenous workloads, on a homogenous fabric of processing cores. REDEFINE combines ASIC (Application Specific Integrated Circuit) like performance with the reconfigurability of FPGAs (Field Programmable Gate Arrays). Morphing Machines innovation enables dataflow compute, which is a paradigm shift in the current processor industry. Due to the nature of our architecture, we can cater across domains from Data Centers, Quantitative Finance, AI/ML acceleration, Edge Vision to High Performance Compute (HPC) applications, all with the same hardware fabric. At Morphing Machines, we are building a cutting-edge technology guided by our vision to build truly software-defined hardware. Job Overview : As the Senior Compiler Engineer, you will be responsible for leading the development of a compiler toolchain for the REDEFINE accelerator, including an MLIR-based graph compiler for AI-ML frameworks. You will work closely with cross-functional teams, including hardware engineers, software developers, and system architects, to ensure the seamless integration of the REDEFINE accelerator with the software ecosystem. Your expertise in compiler development, programming languages, and AI-ML frameworks will be essential in building a powerful and developer-friendly software toolchain. Requirements : Graph Compiler Development: Lead the development of a graph compiler for AI-ML applications, enabling efficient execution of complex neural network models on the REDEFINE accelerator. Design and implement compiler optimizations, code transformations, and scheduling techniques to maximize performance and resource utilization. Collaborate with the hardware and system architecture teams to understand accelerator capabilities and optimize the compiler for specific hardware features. Software Toolchain Development: Contribute to the overall development of the software toolchain for the REDEFINE accelerator, including compilers, runtime environments, and libraries. Collaborate with the system software and runtime teams to optimize the interaction between the compiler and runtime components. Ensure developer-friendly features like debugging support, profiling, and performance analysis tools. Performance Analysis and Optimization: Conduct performance analysis and optimization of the compiler, graph compiler, and intermediate abstraction layer. Collaborate with the hardware and system teams to identify opportunities for performance improvements and software-hardware co-optimizations. Stay updated with the latest advancements in compiler techniques, programming languages, and AI-ML frameworks to drive continuous improvement. Collaboration and Documentation: Collaborate closely with hardware, software, and system teams to ensure seamless integration and compatibility. Document design decisions, algorithms, and optimizations to facilitate knowledge sharing and future development. Provide technical guidance and mentorship to junior team members, fostering a culture of innovation and learning. Qualifications : Masters or Ph.D. degree in Computer Science, Electrical Engineering, or a related field. Proven experience (5+ years) in LLVM/MLIR-based compiler development, particularly in graph compilers for AI-ML applications. Familiarity with AI-ML frameworks like TensorFlow, PyTorch, or ONNX and their compiler integration. Experience with vectorization and parallel programming models such as OpenMP, SYCL, CUDA, or GPGPU programming. Solid understanding of hardware-software co-design principles and performance optimization techniques. Strong analytical and problem-solving abilities. Excellent communication and collaboration skills. Ability to thrive in a fast-paced startup environment. Apply Now

Sr. Staff RTL Design Engineer Bengaluru, Karnataka, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 10862 Remote Eligible No Date Posted 13/07/2025 Job Titles: Senior Staff ASIC RTL Design Engineer - Bangalore location We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and highly skilled digital design engineer with a strong background in ASIC RTL design. You thrive on technical challenges, enjoy collaborating with global teams, and are motivated by seeing your designs come to life in real-world products. With over8 years of hands-on experience in architecting, implementing, and verifying complex digital systems, you are adept at translating functional specifications into efficient, robust RTL. Your experience spans data path and control path designs, and you are comfortable working with industry-standard protocols such as Ethernet, DDR, PCIe, USB, and AMBA.You possess deep expertise in synthesizable Verilog/SystemVerilog, design flows, and EDA tools. You are equally at home mentoring junior engineers as you are diving deep into code or debugging complex issues. Your ability to balance area, latency, and throughput trade-offs sets you apart, and your attention to detail ensures high-quality, reliable IP cores. You communicate effectively with both technical and non-technical stakeholders and are comfortable engaging with customers to clarify requirements and ensure successful delivery.You value diversity, inclusion, and continuous learning, and you bring a collaborative spirit to every project. If you re ready to lead, innovate, and make a tangible impact in the world of high-performance silicon design, Synopsys is the place for you. What You ll Be Doing: Architecting, designing, and implementing state-of-the-art RTL for high-performance synthesizable IP cores within the DesignWare family. Translating complex functional and standard specifications into detailed architecture and micro-architecture documents for medium to high complexity blocks. Owning the entire digital design lifecycle, including RTL coding, synthesis, CDC analysis, debugging, and test development. Collaborating with global, multi-site teams of expert engineers to drive technical excellence and innovation. Interacting with customers to understand and refine specification requirements and providing technical guidance as needed. Mentoring and technically leading junior designers, fostering growth and sharing best practices within the team. Participating in design reviews, quality process improvements, and ensuring adherence to industry-leading verification and design methodologies. The Impact You Will Have: Delivering robust, high-quality IP cores that power next-generation commercial, enterprise, and automotive applications worldwide. Driving innovation in digital ASIC design, enabling faster, more efficient, and reliable silicon solutions for Synopsys customers. Contributing to the advancement of industry standards and protocols through technical leadership and deep domain expertise. Enhancing team performance through mentorship, knowledge sharing, and technical guidance. Strengthening Synopsys reputation as a leader in chip design by consistently delivering on complex customer requirements. Accelerating product development cycles by streamlining design processes and championing best-in-class methodologies. What You ll Need: Bachelor s or Master s degree in EE, EC, or VLSI with8+ years of relevant industry experience in digital ASIC RTL design. Expertise in data path and algorithmic block design (e.g., Reed Solomon FEC, BCH codes, MAC SEC engines) and architecture trade-offs. Proficiency in synthesizable Verilog/SystemVerilog RTL coding, simulation, and EDA tools. Hands-on experience with design flows including Lint, CDC, synthesis, static timing analysis, and formal checking. Strong knowledge of industry-standard protocols (Ethernet, DDR, PCIe, USB, MIPI-UFS/Unipro, SD-MMC, AMBA AXI/AMBA2). Experience with high-speed design (>600MHz), P&R aware synthesis, and tools like Fusion Compiler is a significant plus. Familiarity with revision control systems (e.g., Perforce) and scripting languages (Perl/Shell). Prior experience as a technical lead or mentor within a design team is highly desirable. Who You Are: A collaborative team player who thrives in a global, distributed environment. An effective communicator, adept at conveying complex technical ideas to diverse stakeholders. A proactive problem-solver with strong analytical skills and high initiative. Detail-oriented, quality-focused, and committed to delivering excellence. Passionate about mentoring and enabling the growth of others. Dedicated to diversity, inclusion, and fostering an open, respectful workplace. The Team You ll Be A Part Of: You ll be an integral member of the DesignWare IP Design R&D team at Synopsys Bangalore, collaborating with some of the brightest minds in the industry. The team is focused on developing cutting-edge synthesizable IP cores that are deployed in a wide range of commercial, enterprise, and automotive applications. Working in a multi-site, global environment, you ll have opportunities to engage with cross-functional teams, contribute to technical excellence, and drive innovation in digital design. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Bengaluru View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

About the Company: Founded with the vision of building a runtime reconfigurable, future-proof processor, Morphing Machines is a fabless semiconductor company working on a ground-breaking technology that will transform the chip design landscape. Morphing Machines patent protected IP, REDEFINE, can concurrently accelerate heterogenous workloads, on a homogenous fabric of processing cores. REDEFINE combines ASIC (Application Specific Integrated Circuit) like performance with the reconfigurability of FPGAs (Field Programmable Gate Arrays). Morphing Machines innovation enables dataflow compute, which is a paradigm shift in the current processor industry. Due to the nature of our architecture, we can cater across domains from Data Centers, Quantitative Finance, AI/ML acceleration, Edge Vision to High Performance Compute (HPC) applications, all with the same hardware fabric. At Morphing Machines, we are building a cutting-edge technology guided by our vision to build truly software-defined hardware. Position Overview: As an Associate System Software Engineer at Morphing Machines, you will join the System Software team, building software for the REDEFINE Accelerator - a powerful RISC-V based computing platform for future technologies. This is a great opportunity to start a career in System Software Development, while learning from experienced Engineers and growing your skills under their guidance. You will help bridge the gap between hardware and AI workloads by working on bare-metal firmware, device drivers, Linux kernel modules as well as REDEFINE in-house Simulators and learn hardware-software co-design. Responsibilities: System Software Development: Develop/maintain system software components that enable the REDEFINE accelerator to interface with host systems and software. Design and implement software modules, libraries and APIs to facilitate integration and efficient utilization of accelerator features. Test and debug system software components and ensure functional correctness, reliability and fine-tuning of performance of software components. Firmware Development: Implement, test and debug features in bare-metal firmware and diagnose issues across hardware-software boundary using both industry-standard and in-house developed debug tools. Linux Device Driver Development: Hands on in writing Linux device drivers and Linux based applications. Develop and maintain Linux kernel device drivers for the REDEFINE accelerator. REDEFINE Simulator: Work in feature enhancement and testing of our in-house REDEFINE simulators which model complex interactions between diverse hardware and compute units to validate architecture and performance. Hardware-Software Interaction: Collaborate closely with hardware engineers to understand the accelerators architecture, memory mapping, and communication protocols. Support Senior engineers in testing, debugging features. Documentation and Support: Document code, flow-charts, design decisions and usage guidelines. Participate in code reviews and team discussions to grow your understanding and skills. Requirements: Bachelors / Master s in Computer Science, Electronics and Communication Engineering. Expertise in C/Embedded C programming, OOP concepts and shell scripting. One high-level language like C++, Python, Go, Rust is a plus. Fundamentals in Computer Architecture and familiarity with modern processor architectures (ARM, RISC-V, x86, etc). Knowledge of Operating System Concepts and experience with Linux internals and environment. Understanding of build infrastructure and exposure to software development tools eg. IDEs, debug methods, version management etc. Academic exposure and hands-on on software/application development, firmware development and Linux system programming. Passion for low-level programming, systems, and hardware-software interaction. Strong analytical and problem-solving skills. Eagerness to learn, ask questions, and grow in a collaborative environment. Ability to work in a dynamic startup environment and manage multiple tasks effectively. Apply Now

In your new role you will: 10+ years of Digital Verification experience and a deep understanding of all technical aspects of Verification, including 2+years of technical leadership activitie s Masters/bachelor s in electrical/Electronic Engineering or ComputerScience. Familiarity with version-controlling (eg, Git/Bitbucket, ClearCase,CVS, SVN) and bug-management systems (eg, JIRA). Good to have: Knowledge of ISO26262 and ISO21434. Outstanding Expertise in digital verification and all tasks needed to achieve design verification closure, including state of the art tools and methodologies (SV-UVM, Xcelium, vManager, Certitude, etc) Verification experience in Graphics IP design, cryptographic hardware IP design is a plus. A sense of urgency for upcoming innovation in the field of Verification Proven leadership skills, with experience in coordinating activities,providing technical guidance, and mentoring junior engineers. Self-motivated, flexible, good communication with interpersonal skills and is a good team player who can work well with both internal and external partners Candidate has proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities and self-initiatives A proven ability to solve problems with higher complexity by pro-actively involving expert networks You are best equipped for this task if you have: Digital verification of complex digital design IPs and Subsystems,ASIC and SoCs. Coordinate the overall digital verification activities such as verification planning, verification tracking and reporting, as well as requirement-based verification Collaborate with cross-functional teams, including concept, design to ensure high quality designs Hands-on contributor to digital verification either from scratch, or using legacy verification environments and flows Focus on reuse of the Verification Components to be implemented Identify and mitigate risks in dynamic projects, with pro-active communication to the project team Drive the enhancement of existing verification methodologies and flows, drive required innovation projects and get buy-in from management Foster process and efficiency improvements where applicable, as well as share your expertise to the other team members so that they can grow. As a technical lead inspire and mentor junior verification engineers while providing invaluable technical support and guidance to development teams and business partners We are on a journey to create the best Infineon for everyone.

Staff Processor Verification Engineer Hyderabad, Telangana, India Engineering Employee Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our Hardware Engineers at Synopsys are responsible for designing and developing cutting-edge semiconductor solutions. They work on intricate tasks such as chip architecture, circuit design, and verification to ensure the efficiency and reliability of semiconductor products. These engineers play a crucial role in advancing technology and enabling innovations in various industries. Play Video Job Description Category Engineering Hire Type Employee Job ID 12140 Remote Eligible No Date Posted 13/07/2025 We Are: You Are: You are a highly skilled and motivated ASIC Digital Design Engineer with a relentless passion for innovation and a commitment to excellence. Your deep expertise in digital design and verification is matched by your curiosity and willingness to tackle complex challenges. You have a solid foundation in microprocessor architectures and are adept at developing and maintaining hardware-software co-simulation environments. Your analytical mindset enables you to create comprehensive functional and code coverage models, and you handle regression testing with precision and care. Your technical toolkit is robust: you are fluent in HDL and verification languages such as SystemVerilog and Verilog, and you bring strong programming skills in C, C++, assembly, Python, and Perl. You are comfortable using RTL simulators and verification tools and are always eager to expand your technical horizons by learning new methodologies. Collaboration is second nature to you you thrive in multi-cultural, multi-time zone teams and foster inclusive teamwork. Your excellent communication skills ensure that your ideas are heard and understood, and you enjoy sharing your knowledge while learning from others. You take pride in delivering high-quality, reliable work, and you are driven by the opportunity to make a meaningful impact on the future of technology. What You ll Be Doing: Developing and automating advanced testbenches for ARC processor verification processes. Creating and maintaining functional coverage models and analyzing coverage reports for completeness and effectiveness. Performing comprehensive code coverage analysis to ensure thorough verification and identify potential gaps. Integrating both third-party and internal verification IPs into verification environments. Managing regression testing cycles, analyzing results, and ensuring robust test coverage across all features. Collaborating with multi-site and multi-cultural teams to drive next-generation ARC processor verification projects. Contributing to the improvement of verification methodologies and automation flows. The Impact You Will Have: Ensuring the reliability and high performance of next-generation ARC-V processors. Contributing to the delivery of cutting-edge silicon IP solutions that power industry-leading products. Enhancing the efficiency and effectiveness of verification techniques and processes. Reducing time-to-market for high-performance, low-risk products through rigorous verification. Championing collaboration and knowledge sharing across global engineering teams. Helping Synopsys maintain and strengthen its leadership position in the semiconductor industry. What You ll Need: Bachelor s degree in engineering or a related technical field (required). 4+ years of experience in digital design and verification, with a proven track record of success. Strong knowledge of digital design principles and methodologies. Proficiency in SystemVerilog, Verilog, C, C++, assembly, Python, and Perl. Hands-on experience with RTL simulators and verification tools. Experience with microprocessor architectures (RISC-V experience is a significant plus). Who You Are: An excellent communicator with strong verbal and written skills. A collaborative team player who thrives in a multi-cultural, multi-time zone environment. Analytically minded with exceptional problem-solving skills and attention to detail. Adaptable and eager to learn new technologies, tools, and methodologies. Self-driven, proactive, and passionate about delivering high-quality, reliable results. The Team You ll Be A Part Of: You will be a key member of the Synopsys DesignWare ARC Processor hardware team, working alongside talented engineers on next-generation ARC processor verification. The team is dedicated to developing and maintaining advanced verification environments, ensuring the high performance and reliability of our silicon IP solutions. You will collaborate with colleagues across various locations and time zones, contributing to innovative projects that drive the semiconductor industry forward. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. Apply Save Job test Share Email LinkedIn X Facebook Benefits At Synopsys, innovation is driven by our incredible team around the world. We feel honored to work alongside such talented and passionate individuals who choose to make a difference here every day. Were proud to provide the comprehensive benefits and rewards that our team truly deserves. Visit Benefits Page Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries. ** Benefits vary by country and region - check with your recruiter to confirm Get an idea of what your daily routine around the office can be like Explore Hyderabad View Map Hiring Journey at Synopsys Apply When you apply to join us, your resume, skills, and experience are first reviewed for consideration. Phone Screen Once your resume has been selected, a recruiter and/or hiring manager will reach out to learn more about you, share more about the role, and answer any questions you might have. Interview Next up is interviewing (in person or virtual). You ll be invited to meet with members of the hiring team to discuss your skills and experience, and what you re looking for in your next role. Offer Congratulations! When you have been selected for the role, your recruiter will reach out to make you a verbal offer (a written offer will follow your conversation), and we hope you accept! Onboarding There will be some steps you need to take before you start to ensure a smooth first day, including new hire documentation. Welcome! Once you ve joined, your manager, team, and a peer buddy will help you get acclimated. Over the next few weeks, you ll be invited to join activities and training to help you ramp up for a successful future at Synopsys!

About the Company: Founded with the vision of building a runtime reconfigurable, future-proof processor, Morphing Machines is a fabless semiconductor company working on a ground-breaking technology that will transform the chip design landscape. Morphing Machines patent protected IP, REDEFINE, can concurrently accelerate heterogenous workloads, on a homogenous fabric of processing cores. REDEFINE combines ASIC (Application Specific Integrated Circuit) like performance with the reconfigurability of FPGAs (Field Programmable Gate Arrays). Morphing Machines innovation enables dataflow compute, which is a paradigm shift in the current processor industry. Due to the nature of our architecture, we can cater across domains from Data Centers, Quantitative Finance, AI/ML acceleration, Edge Vision to High Performance Compute (HPC) applications, all with the same hardware fabric. At Morphing Machines, we are building a cutting-edge technology guided by our vision to build truly software-defined hardware. Role Overview: As the Senior FPGA Engineer, you will play a mission-critical role in integrating FPGA designs on both cloud-hosted (AWS F1/F2) and on-premise FPGA platforms. You will own the entire lifecycle of FPGA bring-up, from IP handoff and integration to multi-fabric orchestration and performance validation. You will work closely with product, compiler, and orchestration teams to ensure FPGA-resident applications can be easily deployed, monitored, and benchmarked. Your responsibilities will include validating bitstreams, implementing communication pipelines, and enabling test/demo infrastructure across compute fabrics implemented over various FPGA s. Key Responsibilities: FPGA Bring-Up & Bitstream Integration Interface with the IP team to integrate design drops into deployable bitstreams. Bring up bitstreams on AWS F1/F2 instances, Xilinx VCU platforms, or other compatible boards. Debug issues related to I/O wrapper logic, timing, etc. Platform and Tooling Integration Work with Switchboard and FireSim environments to support application execution across multiple FPGA boards. Contribute to building a Continuous Integration/Deployment (CI/CD)-like pipeline for FPGA validation and test deployment. Establish protocols to bring up and manage multi-FPGA topologies. Application Enablement and Profiling Support application developers in deploying and profiling workloads coded in C with Hardware specific pragmas on FPGA targets. Validate compute vs communication tradeoffs; capture latency, throughput, and power KPIs. Enable applications such as voxel pooling, BFS, and encrypted inference. Documentation and Enablement Document the end-to-end FPGA bring-up workflow, including toolchains, setup guides, debug logs, and issue trackers. Required Skills and Qualifications: Technical Skills: Strong experience with Xilinx toolchains (Vivado, Vitis) , FPGA flows and implementation of design across FPGA boards Hands-on exposure to cloud-based FPGA platforms such as AWS F1/F2 Solid understanding of RTL development using Verilog/SystemVerilog Familiarity with memory controllers, timing analysis, and interface protocols Tooling & Workflow Integration: Experience with FPGA integration in CI/CD environments Knowledge of simulation and emulation frameworks Understanding of software-hardware co-design and ability to assist with application bring-up (C/C++) Soft Skills: Strong debugging and problem-solving skills Comfortable working in fast-paced, ambiguous environments Excellent communication and collaboration skills Ability to take ownership of integration across multiple teams Education and Experience: Bachelor s or Master s degree in Electronics, Electrical, or Computer Engineering 10+ years experience in FPGA bring-up, hardware integration, or system-level FPGA projects Preferred Skills (Bonus): Experience with Switchboard, FireSim, or multi-fabric orchestration Familiarity with compiler-level hardware mapping Understanding of OpenCL, LLVM, or machine-generated IR flows Ability to assist in building test infrastructure for cloud FPGA CI/CD Apply Now

Since June 2021, frog is part of Capgemini Invent . frog partners with customer-centric enterprises to drive sustainable growth, by building and orchestrating experiences at scale, while harnessing the power of data and technology. Were inventing the future of customer experiences by delivering market-defining business models, products, services, brand engagements and communications. Joining frog means youll be joining the pond, a global network of studios, each with a thriving in-person and vibrant virtual culture. frogs are curious, collaborative, and courageous, united by our passion for improving the human experience across our areas of expertise, while each bringing our unique and diverse skills and experiences to the table. We draw on our global reach and local knowledge to solve complex problems and create innovative, sustainable solutions that touch hearts and move markets. frogs prize humour, positivity, and community just as highly as performance and outcomes. Our culture is open, flexible, inclusive, and engaging. Working at frog means being empowered to meet the moment, and Make Your Mark on every project, in your studio, your community and the world at large. Equal Opportunities at frog Frog and Capgemini Invent are Equal Opportunity Employers encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status, or any other characteristic protected by law.

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Entry level graduate with limited commercial and technical work experience. Build skills and expertise in a chosen Engineering Discipline. Works to instructions and directions and delivers reliable results. Keen to understand clients business needs. Solves routine problems. Organises own time with a short time horizon. Skills (competencies)

Post-Silicon ATE Lead to lead and manage post-silicon validation and production testing efforts using ATE platforms. This role requires strong technical expertise in silicon characterization, test development, and working closely with cross-functional teams including design, DFT, packaging, and product engineering. Own and lead post-silicon validation and ATE characterization for silicon devices (SoC/MCU/ASIC). Develop and debug ATE test programs for characterization, qualification, and production ramp-up. Collaborate with design and DFT teams to define test coverage and validation strategy. Analyze silicon test data to identify functional/parametric failures, yield issues, or corner case behaviours. Lead silicon debug and root cause analysis of test failures. Define and drive test cost optimization strategies (e. g. , multisite, parallel test, retest strategy). Work with OSATs and vendors for probe card, loadboard, and socket development. Define test limits, corner conditions, and environmental conditions (HTOL, AC/DC, ESD, etc. ). Support qualification testing (e. g. , HTOL, HAST, Temp Cycle) and drive correlation Qualifications B. E. / B. Tech or M. E. / M. Tech in Electronics, Electrical, or related field. 12+ years of experience in post-silicon validation and ATE development. Strong hands-on experience with ATE platforms (e. g. , Teradyne UltraFlex, Advantest 93K, NI STS). Solid understanding of mixed-signal, digital, and analog test methodologies. Experience with scripting (Python, Perl, and C) for automation and data analysis. Familiarity with lab equipment (oscilloscopes, source meters, BERTs, etc. ) for correlation and debug. Excellent problem-solving skills and ability to work across global teams. Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world s leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21, 000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what s next in electronics and the world.