776 Asic Jobs - Page 14

This role involves the development and application of engineering practice and knowledge in the following technologiesElectronic logic programs (FPGA, ASICs); Design layout and verification of integrated circuits (ICs),printed circuit boards(PCBs), and electronic systems; and developing and designing methods of using electrical power and electronic equipment; - Grade Specific Focus on Electrical, Electronics Semiconductor. Develops competency in own area of expertise. Shares expertise and provides guidance and support to others. Interprets clients needs. Completes own role independently or with minimum supervision. Identifies problems and relevant issues in straight forward situations and generates solutions. Contributes in teamwork and interacts with customers. Skills (competencies)

Required Skills Experience in Logic design / RTL coding is a must. Experience is SoC design and integration for complex SoCs is a must. Experience in Verilog/System-Verilog is a must. Experience in Multi Clock designs, Asynchronous interface is a must. Experience in using the tools in ASIC development such as Lint and CDC. Experience in Synthesis / Understanding of timing concepts is a plus. Experience in ECO fixes and formal verification. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture. Excellent oral and written communications skills. Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

Role Description: This is a full-time on-site role for a Senior Lead Physical Design Engineer based in Hyderabad. The Senior Physical Design Engineer will be responsible for tasks related to physical design, physical verification, logic design, circuit design, and RTL design in the development of silicon products. Qualifications: He/She should be able to do block level PNR including PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. Minimum of 7-15 years of experience in physical design. He/She should have worked on 7nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Lead a team of Physical design engineers and be responsible for their blocks closure Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Expertise in Timing closure on high speed interfaces is a plus Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

He/She should be able to do block level / top-level floor planning, PG Planning, partitioning (for hierarchical designs) , placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks and be able to fix the violations . S hould have worked on 4 5nm , 28nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design eng inee rs. Interface with front-end ASIC teams to resolve issues. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs.

Responsibilities Understand the standards/specifications Architecture development and documenting implementation level details Hands on work for every aspect of verification cycle Responsible for the compliance with the latest Methodologies. Developing Verification IPs Define Functional Coverage matrix and Comprehensive Test plan Regression management and functional coverage closure DUT integration and verification for IP delivery sign-off Leading small team Person Specification Required Skills Hands-on experience of complete verification cycle with strong verification concepts Strong knowledge of Verilog, SystemVerilog and UVM Experience in UVM based Verification IP development Experience in AMBA AXI/AHB/APB System buses Hands on work experience on any of PCIe/Eth/USB/DDR etc. Hands on experience with System Verilog Assertions Scripting for automation, release process, simulations, regressions Good command over written and oral communication Desirable Skills Lead the Verification IP development with 2 or more junior engineers Exposure to full verification cycle Desired Skills and Experience DV Engineer, Design Verification, Verification Engineer

MTS SILICON DESIGN ENGINEER THE ROLE: We are looking for an adaptive, self-motivative design engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMDs abilities to deliver the highest quality, industry-leading technologies to market. The Physical Design Engineering team furthers and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 8-12 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floor planning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SE NIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the physical integration and verification team , you will work closely with the physical design implementation, IP teams and fab contacts to achieve quality tapeout and first pass silicon success. THE PERSON: A successful candidate will work on block level and SoC physical integration, verification and tapeout with physical design engineers. The candidate is expected to be detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work with PD team on subsystem and block level physical verification and signoff Work closely with physical design implementation and signoff team to achieve faster TAT Work closely with CAD team to come up with new flows and methodologies in the physical verification domain PREFERRED SKILLSET: 6+ years of relevant experience Sound knowledge of physical verification and design flows Hands on experience on industry standard tools such as Calibre and ICV Sound understanding for DRC/LVS decks. Should be able to make updates as required. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SMTS S OFTWARE DEVELOPMENT ENG INEER THE ROLE: AMD is looking for an influential software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess l eadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Apply a data minded approach to target optimization efforts Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develo p new groundbreaking AMD technologies Participating in new ASIC and hardware bring up s Debugging /fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Develop technical relationships with peers and partne rs PREFERRED EXPERIENCE: Strong object-oriented programming background, C/C++ preferred Ability to write high quality code with a keen attention to detail Experience with modern concurrent programming and threading APIs Experience with Windows, Linux and/or Android operating system development Experience with software development processes and tools such as debuggers, source code control systems (GitHub) and profilers is a plus Effective communication and problem-solving skills Motivating leader with good interpersonal skills ACADEMIC CREDENTIALS: Bachelor s or M asters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent #LI-DNI Benefits offered are described: AMD benefits at a glance .

SE NIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work on full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 5+ years of professional experience in the industry in power integrity domains Good knowledge of Power delivery and power integrity flows Hands on experience on industry standard tools especially Redhawk based power integrity analysis Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SILICON DESIGN ENGINEER 2 THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on block level SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work on block level and sub-system level IR/EM convergence on multiple ASICs across different technology nodes. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 3+ years of professional experience in the industry in power integrity domains Good knowledge of power delivery and power integrity flows Hands on experience on industry standard tools especially Redhawk based power integrity analysis Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

SE NIOR SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC electrical signoff convergence with physical design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work on full chip IR/EM convergence on multiple ASICs across different technology nodes. Work closely with architecture, power management, package and floorplan team to come up with robust power delivery design. Work with RTL and PD team in coming up with the low power and UPF specification for the SoC. Work closely with CAD team to come up with new flows and methodologies in the power integrity domain. PREFERRED SKILLSET: 6+ years of professional experience in the industry in power integrity domains Good knowledge of Power delivery and power integrity flows Hands on experience on industry standard tools especially Redhawk based power integrity analysis Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER THE ROLE: As a member of the AECG Custom ASIC Group, you will help bring to life cutting-edge designs. As a member of the Power Delivery convergence team , you will work closely with the architecture, physical design teams, package, board, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work on full chip SoC low power convergence and power analysis. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. KEY RESPONSIBLITIES: Work closely with architecture, RTL, PD and power management teams for coming up with the chip low power intent and UPF. Work with architecture, RTL and PD team for chip level power estimation, analysis and optimization Work closely with CAD team to come up with new flows and methodologies in the power analyisis and low power domains. PREFERRED SKILLSET: 8+ years of professional experience in the industry in low power and power estimation domains. Hands on experience on industry standard tools especially PTPX, Power Artitst, VCLP and CLP. Good in scripting languages such as Tcl and Perl Self driven, positive attitude and team worker ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SR4 Benefits offered are described: AMD benefits at a glance .

THE ROLE: AMD is looking for a s enior software engineer to join our growing team. As a key contributor you will be part of a leading team to drive and enhance AMD s abilities to deliver the highest quality, industry-leading technologies to market. THE PERSON: The ideal candidate possesses an innovative and problem-solving mindset, has a keen eye for S oftware engineering development , and is diligent and passionate about Technology . A successful candidate will need to employ strong knowledge in computer technologies, leadership skills in technical areas, and SW engineering expertise as well as a strong ability to compete effectively in a fast-paced, relevant environment while working with different teams of engineers and collaborators. KEY RESPONSIBILITIES: Develop and drive execution of comprehensive , highly effective software for sophisticated new technology and new product introduction projects Validate new SW features before releasing them to customers Contribute to a high-functioning feature team C ollaborate closely with multiple teams to deliver key planning solutions and the technology to support them Help contribute to the design and implementation of future architecture for a highly scalable, durable, and innovative system Work very closely with dev teams and Project Managers to drive results PREFERRED EXPERIENCE: Strong digital design and simulations basics RTL (VHDL, Verilog & System Verilog) coding skills Understanding of FPGA design flow and tools (Synthesis, Simulation and implementation) ASIC/FPGA verification experience VHDL and Verilog Xilinx Vivado Design Suite experience Hands on experience on simulators like XSIM, Questa, Modelsim, VCS etc. Advanced Debug skills in software environment or strong problem-solving skills Hands on experience with scripting preferably tcl, pearl and python ACADEMIC CREDENTIALS: Bachelor s or Master s degree in Computer/Software Engineering, Computer Science, or related technical discipline #LI-NR1 Benefits offered are described: AMD benefits at a glance .

MTS SILICON DESIGN ENGINEER (Timing Constraints/STA Signoff ) THE ROLE: The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. T HE ROLE : As a member of the AECG ASIC Group, you will help bring to life cutting-edge designs. As a member of the Back-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE PERSON: A successful candidate will work with silicon design engineer s . The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. K EY RESPONSIBLITIES : Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff Ensuring constraints quality (SDC) using industry tools like Fishtail , GCA Well versed with timing signoff methodology and corner definitions Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Requires a mix of SDC knowledge, EDA timing tool competence and Tcl based scripting capability (in both EDA environment and standalone Linux Tcl shell scripts) Responsible for Timing closure of one or multiple sub chip/subsystem OR Full chip. Ensuring full chip level Interface timing closure along DRV closure Generating timing ECO using tools DMSA/Tweaker and leading subsystem/Subchip/FC timing closure P REFERRED EXPERIENCE : 8+ years of experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows. Proficient in analyzing SoC architecture to derive appropriate timing constraints and define STA methodology. Skilled in translating architectural and design specifications into accurate timing constraints (SDC), including clock definitions, generated clocks, exceptions (false paths, multi-cycle paths), and hierarchical timing. Owned timing budgets, constraint development, and timing ECOs, achieving first-pass silicon success. Experience with analyzing the timing reports and identifying both the design and constraints related issues. Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail, Tweaker etc. Excellent communication and interpersonal skills and always enthusiastic to collaborate with diverse teams. Experience in timing closure of high frequency blocks & subsystems (> Ghz range ) Experience in working full-chip STA closure, defining mode requirements and corners for timing closure. Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV,AOCV,POCV analysis. Strong TCL/scripting knowledge is mandatory. ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering # LI-SR4 Benefits offered are described: AMD benefits at a glance .

The Opportunity Were looking for the Wavemakers of tomorrow. At Alphawave Semi, we design, develop, and deliver advanced semiconductor solutions for a range of verticals and industries. Our connectivity IP division delivers cutting edge IPs in the most advanced technology nodes and enjoys close partnerships with leading tier 1 customers. We are leaders in high-speed networking and memory interface IP. Our ASICs are also seen in satellite communication systems, IoT and extreme low-power mobile devices. With our expertise in package-silicon codesign, we belong to the technology elite that leading-edge products based on advanced technology and packaging. We have a global presence with multiple development centres in North America, EMEA, China, Taiwan, and India. To support our growth and expansion plans, we are seeking to hire exceptional talent to expand our presence in India. What Youll Do: Own project schedules and execution tracking with engineering team. Track project milestones, deliveries & risk mitigation to align strategy with management team. Work with team leads to refine WBS and build into execution schedule. Drive internal signoff with engineering. Define and drive process frameworks across teams for efficient and consistent execution and quality deliverables. What Youll Need: Bachelors or Masters Degree in Electronics/Electrical/Computer Engineering with 5 or more years of relevant experience in a semiconductor or electronics product company Technical appreciation of IP, ASIC/SoC flows (front end and backend development processes, product and test engineering, char and validation, hardware/software design). Familiarity with IP development processes and product life cycle. Customer and program management skills, ability to organize information for internal/external consumption. Knowledge of Microsoft Project, Smartsheet, Confluence, defect tracking Tools and other program management tools for use in complex semiconductor programs. Additional skills and experience considered an asset Experience in stage gate process for new program development Experience in development and engineering role as part of Die to Die connectivity, Memory controller and Phy IP development for understanding of execution flow and cross team interdependencies Schedule development, tracking and reporting with MS Office Project or other program management tools Understanding of IP development challenges in advanced process nodes at 5nm and below Understanding of key IP deliverables and customer integration challenges Experience in vendor negotiations, contract management, project cost estimation and cost deviation analysis PMP certification an asset We have a flexible work environment to support and help employees thrive in personal and professional capacities As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

We are seeking a skilled SoC Frontend Design Engineer to join our integrated circuit (IC) design team. Will be focusing on RTL design, digital logic design, synthesis, linting, timing analysis, and verification for ASIC projects. Work closely with cross-functional teams to deliver high-quality and efficient SoC (System on Chip) designs. This role requires good knowledge of VHDL/Verilog, verification methodologies, testbench development, and debugging. You have: Bachelors Degree in Electrical, Computer Engineering, or a related field (Masters preferred) 3+ years of experience in RTL design and digital logic design. Proficiency in VHDL/Verilog for RTL design. Strong knowledge of digital logic design, synthesis, and timing analysis. Experience with linting tools and methodologies Familiarity with verification methodologies (UVM, System Verilog), testbench development, simulation, and functional coverage. Strong debugging skills to identify and resolve design issues Required Tools: Synopsys Design Compiler or Cadence Genus, Mentor Graphics QuestaSim, Spyglass VC It would be nice if you also had: Familiarity with high-level synthesis (HLS) tools Knowledge of scripting languages such as Python, Tcl, or Perl for automation Develop RTL designs using VHDL/Verilog for ASIC projects Perform digital logic design, synthesis, and timing analysis Conduct linting and static analysis to ensure code quality Develop and implement verification methodologies (UVM, System Verilog) Create and maintain testbenches for simulation and functional coverage Perform simulations and debugging to ensure design correctness Participate in design reviews and provide feedback to improve design quality

About Marvell . Your Team, Your Impact Marvell Custom Compute & Storage - CCS BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Strong analytical and problem-solving skills Ability to manage multiple tasks in a fast-paced environment Excellent communication, interpersonal, and teamwork skills Capable of interfacing effectively at all levels within and outside the organization Proactive in participating in problem-solving and quality improvement initiatives What Were Looking For Bachelor s degree in CS/EE with 8-12 years of relevant experience, or Master s degree in CS/EE with 8-10 years of relevant experience Strong background in IP, Subsystem and SoC verification, including methodology and testbench development Proficient in hardware verification languages such as Verilog, SystemVerilog, UVM, and C/C++ Solid understanding of verification methodologies: object-oriented programming, white-box/black-box testing, directed/random testing, coverage analysis, and gate-level simulations Experience in Unix/Linux environments; scripting skills in Shell, Perl, or Python are a plus Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Role & responsibilities Please interested candidate send me cv :galeiah.g@honeybeetechsolutions.com call me :7995220108. Client Name: Proxelera Industry: SEMICON Position Name RTL Design Lead/uArch/Design Engineer Position type: Permanent Total Exp: 10-15 years HBTS Budget: Open Notice Period: Immediate to 15days Work Location: Bangalore Job Description Must have: We're looking for a highly skilled RTL Design Lead to lead our digital design team. The successful candidate will be responsible for designing, developing, and verifying complex digital circuits using RTL design methodologies. The RTL Design Lead will work closely with cross-functional teams to ensure seamless integration of digital design blocks into larger systems. Key Responsibilities: 1. Lead a team of RTL designers to design, develop, and verify complex digital circuits. 2. Develop and maintain RTL design methodologies, standards, and best practices. 3. Collaborate with architects to define and implement digital architecture. 4. Work closely with verification teams to ensure seamless integration of digital design blocks. 5. Participate in design reviews, provide feedback, and ensure design quality. 6. Develop and manage project schedules, resource allocation, and budgets. 7. Mentor and train junior designers to improve team capabilities. Requirements: 1. Bachelor's/Master's degree in Electrical Engineering, Computer Science, or related field. 2. 10+ years of experience in RTL design, with at least 3 years in a RTL design/uArch leadership role. 3. Strong expertise in digital design principles, RTL design methodologies, and verification techniques. 4. Proficiency in HDLs (Verilog/SystemVerilog/VHDL), design tools (e.g., Synopsys, Cadence), and scripting languages (e.g., Perl, Python). 5. Excellent leadership, communication, and project management skills. 6. Strong problem-solving skills, with the ability to analyze complex design issues. Nice to Have: 1. Experience with ASIC/FPGA design flows. 2. Knowledge of computer architecture, microprocessors, and embedded systems. 3. Familiarity with industry-standard design methodologies (e.g., OVM, UVM). 4. Certification in RTL design or related field. AMD (Dont Share AMD Profiles) Preferred candidate profile

Program Manager 1 THE ROLE: We are seeking an experienced and dynamic Program Manager to join our Custom ASIC/SOC Development Group. In this role, you will lead high-impact technical programs from concept through tapeout to post-silicon validation. You ll manage cross-functional execution across RTL, verification, physical design, packaging, and bring-up, delivering complex SoC solutions to our global partners. THE PERSON: This role is ideal for someone with a strong technical background in chip design and 3 5 years of program management experience, capable of managing complexity, influencing stakeholders, and driving results in a highly matrixed organization. KEY RESPONSIBILITIES Own and drive SoC program execution from requirements through tapeout. Develop detailed plans of record, schedule, deliverables, resources, risks, and mitigation strategies. Coordinate across IP, SoC front-end, back-end, validation, test, and packaging teams. Act as the central point of contact for program status, issues, risks, and escalations internally and externally. Monitor and communicate progress using dashboards, KPIs, Gantt charts, and performance metrics. Ensure quality gates are met and engineering change requests are tracked and resolved promptly. Collaborate with engineering leads to make technical tradeoffs and align with design goals. Facilitate executive reporting and program reviews. Promote best practices in program execution and risk management. PREFERRED EXPERIENCE: Experience in managing multiple SoC programs in domains like mobile, compute, automotive, AI, etc. PMP certification or equivalent program/project management training. Familiarity with program tools such as MS Project, JIRA, Confluence, Power BI, or equivalent. Executive communication experience and ability to influence across technical and business functions. REQUIRED QUALIFICATIONS: Bachelor s or Master s degree in Electronics, Electrical, or Computer Science Engineering. 10-12+ years of experience in the semiconductor industry with 3 5 years in technical program management. Strong hands-on exposure in SoC design flows, IP development, integration, Verification/Validation, DFT, STA, physical design, and tapeout. Proven track record in leading cross-functional, geographically dispersed teams. Strong risk and issue management capabilities, with the ability to escalate and drive resolution effectively. #LI-SR4 Benefits offered are described: AMD benefits at a glance .

Job Description As an Implementation Engineer in Arm's Solutions Engineering group we like to think we are not just crafting sophisticated CPUs, GPUs and SoCs, but we are defining future chip design techniques Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC, CPU and GPU chip design possible At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners A key component of this is around the development of comprehensive implementation and analysis methodologies Responsibilities Synthesis, Physical design and implementation of CPU and GPU cores, system interconnect and other ARM IP, SoC Analyze design timing, area and power to help improve the quality of ARM IP Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP Converting R&D concepts into real implementation solutions Enable our partners to achieve the best possible quality of results Required Skills and Experience Bachelors or Masters degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields 8 to 12 Years years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification The ability to demonstrate that you can express new insights and communicate them effectively Possess a high level of dedicated, initiative and problem-solving skills Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams Previous experience in and knowledge of the entire IC design flow, from RTL through to GDS2 Proven programming and scripting skills eg Tcl, Perl, R, Make, sh ?Nice To Have? Skills and Experience Knowledge around Arm based CPUs and SoCs! Experience with low power design techniques (power gating, voltage/frequency scaling) Experience with Verilog RTL design Experience with ATPG tools/and or production testing In Return We are proud to have a set of behaviors that reflect our culture and guide our decisions, defining how we work together to defy ordinary and shape outstanding! Partner and customer focus Teamwork and communication Creativity and innovation Team and personal development Impact and influence Deliver on your promises Accommodations at Arm At Arm, we want our people to Do Great Things If you need support or an accommodation to Be Your Brilliant Self during the recruitment process, please email accommodations@arm com To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud or office accessibility Please email us about anything we can do to accommodate you during the recruitment process Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran Hybrid Working at Arm Arms hybrid approach to working is centred around flexibility, where we split our time between the office and other locations to get our work done Within that framework, we empower groups and teams to determine their own particular hybrid working pattern, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you Accommodations at Arm At Arm, we want to build extraordinary teams If you need an adjustment or an accommodation during the recruitment process, please email accommodations@arm com To note, by sending us the requested information, you consent to its use by Arm to arrange for appropriate accommodations All accommodation or adjustment requests will be treated with confidentiality, and information concerning these requests will only be disclosed as necessary to provide the accommodation Although this is not an exhaustive list, examples of support include breaks between interviews, having documents read aloud, or office accessibility Please email us about anything we can do to accommodate you during the recruitment process Hybrid Working at Arm Arms approach to hybrid working is designed to create a working environment that supports both high performance and personal wellbeing We believe in bringing people together face to face to enable us to work at pace, whilst recognizing the value of flexibility Within that framework, we empower groups/teams to determine their own hybrid working patterns, depending on the work and the teams needs Details of what this means for each role will be shared upon application In some cases, the flexibility we can offer is limited by local legal, regulatory, tax, or other considerations, and where this is the case, we will collaborate with you to find the best solution Please talk to us to find out more about what this could look like for you Equal Opportunities at Arm Arm is an equal opportunity employer, committed to providing an environment of mutual respect where equal opportunities are available to all applicants and colleagues We are a diverse organization of dedicated and innovative individuals, and dont discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran

Understanding the business requirements from Sivaltech clients and defining the scope and key objectives of Sivaltech IP- 20% : Collaborating with Sivaltech clients and other stake holders in order to understand the business background and clearly define the scope and key objectives of the project. Developing clear statement of objectives and performance metrics. Translating Sivaltech client needs in to business requirements into detailed analytical requirements in accordance with petitioner s problem-solving approach. Creating hypotheses of variable relationships relevant to that business problem. Designing the complete Architectural Framework and spec for future versions of the IP - 20% : Discussing the merits and demerits of various alternative analytical approaches and with respective to Sivaltech client needs. Working with the client to finalize intermediate, final deliverables, and the timelines for the project. Interacting with RTL Design, Verification and physical design teams inhouse to make and create sustainability report and defining achievable standards along with trade offs to meet the defined spec. Extracting relevant data from appropriate data sources for the execution of the project. Program Management - 25% : Data quality check - Ensuring data integrity by cross - checking the extracted data with the relevant stakeholders for data accuracy and consistency. Maintaining an accurate check on Open source vs indigenously developed components for the IP while not breaching the open source standards and agreements. The cndidate will work in conjunction with other team members to develop Business Process environments specification documents and modify high-level architecture of the IP. Sync Ups with RTL design team members and regular cross verification of the architecture document with simulation environment. Improving Sivaltech verification signoff process on a continuous basis for reusability and smooth handover to Physical design team by continuously tracking the methodology standards and updating the sign off methodology. Managing the overall schedule and incorporating inputs from marketing teams. Meeting clients and architecting variants of the IP- 35% : Candidate will travel extensively meeting clients to establish business cases for Sivaltech IP variants with different foundries and technology nodes. With sound understating of the ASIC business in US, candidate will be responsible for architecting different variants of the IP while understanding client specifications and will be responsible for embedding the same in architecture document. Will be responsible for feasibility analysis and clearly define the standards and variants of the VIPs that needs to be developed. Collating and presenting the recommendations and insights that would enable continuous measurable improvement in the client s business decisions. Preparing executive summary of the results for the senior management. The position of Programmer Analyst is a professional and specialized occupation which requires, at a minimum, a Bachelor s Degree in Computer Science, Computer Applications, CIS, Information Technology or related.

Overview: TekWissen is a global workforce management provider throughout India and many other countries in the world. Position: RTL Engineer Location: Hyderabad Work Type: Onsite Job Type: Full time Job Description: Key Responsibilities: Understand RTL at structural level, IP boundaries, IP parameters. Understand IP design. Add assertions where needed. Generate various constraints necessary for the IP. RTL build flow setup and maintenance. Do the quality checks of the IP like Lint/CDC/RDC/Synth/Timing checks/waiver creation across milestones. Participate in IP integration to the subsystem level. Write sample test bench to verify the basic functionality of the IP/block. Do the first level of triage of the functional issues reported. Understand the reports out of quality checks such as Lint/CDC/RDC/Synth/Timing checks and suggest fix in the RTL Work with functional verification team to meet coverage and quality standards. Guarantee quality/timely deliverables meeting projects schedule. Help to improve/automate design process. PREFERRED EXPERIENCE: Knowledge of ASIC development flows Knowledge of front-end RTL design tools and methodologies. Knowledge of system Verilog Multi-clock domain designs. Design constraints for synthesis and static timing analysis. Experience in RTL linting tools, reset domain crossings, clock domain crossings, synthesis, RAM generation (area, timing, power) Knowledge of AXI/AMBA protocol Ability to create a simple SV based Test benches, create sanity test plan, run the test cases Knowledge of front-end requirements and deliverables for verification, validation, physical design, architecture, security, dfx, power. Verification - coverage, test plan, debug Physical design – timing, clock crossings, reset crossings, ECOs (manual, formal) Ability to work and effectively collaborate with partners Knowledge of scripting languages like Perl, tcl or cshell Experience with DMAs, PCIe, ordering, data path virtualization, performance, flow control a plus. TekWissen® Group is an equal opportunity employer supporting workforce diversity.

We are seeking an experienced Senior CAD Engineer to join our team in Bangalore. The ideal candidate will play a critical role in deploying, automating, and supporting front-end CAD tools and flows for global hardware development teams. Key Responsibilities: Deploy and provide support for front-end tools, including: RTL simulators Low power analysis tools Static RTL checkers Develop and maintain scripts to automate regression, debug flows, and other repetitive tasks. Manage and optimize CI/CD processes for design and verification environments. Collaborate and interface with EDA vendors for tool support, issue resolution, and license management. Work closely with global engineering teams across geographies to provide consistent CAD tool support. Maintain and administer Linux systems used in design environments. Required Skills and Experience: 10+ years of experience in CAD engineering, particularly in front-end digital design flows. Strong scripting skills: Python, Bash, Makefiles, etc. Hands-on experience in Linux system administration. Proficiency in version control tools such as Git or Mercurial. Solid understanding of ASIC design flows and experience with standard CAD tools (e.g., Synopsys, Cadence). Ability to manage tool deployment, automation, and support in a multi-site, global environment. Strong communication skills and a proactive, problem-solving mindset. Preferred: Candidates with a notice period of 15 days or less.

As an Analog and Mixed-Signal (BiCMOS) ASIC / MMIC Design Engineer , you will develop state-of-the-art application-specific integrated circuits (ASICs) and monolithic millimeter-wave integrated circuits (MMICs) that provide competitive performance and cost advantages to Keysight's next-generation test and measurement products. You will work on complex high-speed analog and RF ICs using advanced semiconductor processes, collaborating with global engineering teams (US and Germany), and contributing across the entire design lifecyclefrom system-level analysis to hands-on validation. Key Responsibilities Design high-performance analog and mixed-signal ASICs and MMICs for measurement instrumentation using BiCMOS and RFIC technologies . Perform system-level analysis to define IC-level performance requirements aligned with instrument architecture. Design and simulate a wide range of RF/analog circuit topologies including amplifiers, mixers, and filters . Conduct circuit-level and EM simulations , leveraging tools such as ADS, Momentum, EMPro, Cadence, and SystemVue . Collaborate with global teams on IC layout, verification, packaging, and thermal design . Drive lab measurements and root cause analysis , using state-of-the-art test equipment to validate and troubleshoot IC performance. Provide technical documentation , design reviews, and effectively communicate results across cross-functional teams. Support continuous improvement in design methodology, tool flows, and knowledge sharing. Required Qualifications BS, MS, or PhD in Electrical Engineering (preferred: thesis or coursework in analog/mixed-signal or RFIC design). 3+ years of experience in analog and/or mixed-signal ASIC/MMIC design using advanced semiconductor processes. New MS/PhD graduates with relevant coursework or research experience will also be considered. Strong knowledge of RF/microwave design , signal integrity , and device-level parasitics . Experience with schematic capture, simulation, and layout tools. Solid understanding of bipolar transistor design , analog/RF building blocks , and microwave engineering . Excellent problem-solving , interpersonal , and communication skills. Demonstrated ability to work effectively in cross-site, cross-functional teams.

Lattice is seeking candidates for the position of Staff Software Development Engineer in FPGA place and route. This is a full-time position located in Pune, India. The successful candidate will join a team designing and developing Lattice FPGA implementation software tools. The candidate will contribute to delivering software solution for Lattice FPGA development with emphasis on Lattice synthesis mapper tool. The candidate is expected to be an expert in FPGA synthesis core engine and technological mapping with knowledge on how to achieve optimal solution for a given architecture and be able to support next generation FPGA with best result in Fmax, Area, Runtime as we'll as memory utilization The candidate will team up with other synthesis/mapper developers and develop synthesis mapping engine for various FPGA products. The responsibility also includes customer support, new software feature support as we'll as QoR improvement. The candidate is expected to maintain existing software products and interact with other teams to facilitate a value-added solution too. Accountabilities: Develop logic synthesis/mapper tool for Lattice FPGA products. Synthesize logic designs from Verilog/VHDL RTL to structural netlist. Improve synthesis/mapper engine QoR. Create test designs with test benches to verify implementation and ensure high quality. Qualifications: BS/MS/PhD in Electrical Engineering or Computer Science or Computer Engineering. Proficient with C/C++, Verilog/VHDL, logic design, Tcl and shell scripts. Strong background and experience in data structures and algorithms. Experience of logic design and EDA software is a must. Experience of logic optimization and technology mapping development is required. Experience of FPGA tool development is preferred. Strong written and verbal communication skills, and collaboration skill. Experience of multi-processing development is a plus. Solid understanding in FPGA architectures is a plus. 10+ years of experience in logic synthesis development in FPGA or ASIC domains