776 Asic Jobs - Page 10

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop and optimize low-level operating system components, including drivers, kernel modules, and firmware. Perform pre-silicon debugging on FPGA, prototyping, and emulation platforms to validate design functionality. Lead post-silicon bring-up and validation activities on new silicon platforms. Work closely with hardware, architecture, and design teams to debug complex system issues across software and hardware boundaries. Develop test cases, debug tools, and automation for validation and verification purposes. Analyze and solve challenging issues involving hardware-software interactions. Document design, debug procedures, test plans, and results effectively. Skills Must have 5-15y exp Strong proficiency in C programming and data structures (Minimum skill rating8/10). Solid understanding of computer architecture and operating system fundamentals. Excellent problem-solving and debugging skills. Experience in pre-silicon environments (simulation, FPGA prototyping, emulation platforms). Experience with post-silicon validation and system bring-up. Familiarity with embedded systems, RTOS, and low-level software development. Ability to analyze hardware-software interaction issues. Nice to have Strong communication and collaboration skills.

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Collaborate with design and verification teams to understand digital design specifications and ensure comprehensive verification coverage. Develop and execute verification plans for ASIC/FPGA designs using directed tests and/or SystemVerilog with UVM methodologies. Build and maintain testbenches, verification components, and assertion-based verification structures to validate complex digital designs. Perform simulation, debugging, and coverage analysis to ensure functional correctness and compliance with design requirements. Contribute to the automation of verification flows through scripting (Python, Perl, Bash) to improve productivity and consistency. Work in Unix/Linux environments for development, simulation, and regression testing activities. Document verification strategies, results, and maintain clear communication with cross-functional teams to support project milestones. Actively participate in code reviews and contribute to continuous improvement of verification methodologies and best practices. Skills Must have 1 position6+y, 1 position4+y Strong in digital design. Skills in ASIC / FPGA verification (directed test or System Verilog / UVM) A good knowledge of simulation flow Good basis in scripting Python, Perl, Bash.. Proficiency in Unix environment. Good communication skills Nice to have Bachelor's/Master's in ECE

Project description We are passionate about transforming lives through cutting-edge technology, enriching industries, communities, and the world. Our mission is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. At the core of our mission lies a culture of innovation. We challenge boundaries to solve some of the world's most critical problems. We are committed to execution excellence, fostering a culture of openness, humility, collaboration, and inclusivity, valuing diverse perspectives along the way. Responsibilities Develop System Verilog/UVM-based testbenches for block-level and system-level verification. Write and execute UVM test cases to verify functional correctness of RTL designs. Perform detailed functional coverage and code coverage analysis, and drive coverage closure. Debug simulation failures, root-cause issues, and work closely with design and verification teams for resolution. Collaborate with cross-functional teams to ensure successful verification closure within project timelines. * Develop and maintain scripts using Python or other scripting languages for automation, regression management, and data analysis (optional but preferred). Apply working knowledge of standard bus protocols such as AXI, APB, UART, and IJTAG for testbench development and debugging. Document verification plans, test specifications, test reports, and maintain traceability. Skills Must have 4-6y exp SV / UVM Test bench development and test cases coding Code and Functional coverage analysis and closure Work with team for verification closure Bus protocols AXI / APB / UART/ IJTAG protocol working knowledge is an advantage. Nice to have Experience with python or any other scripting language is a plus

A Senior Software Engineer is responsible for designing, developing, and maintaining high-quality software applications Designing and developing software applications: Senior Software Engineers are responsible for designing and developing high-quality software applications using programming languages such as Java, Python, C++, or others Senior Software Engineers are responsible for mentoring and providing guidance to junior developers, including reviewing their code and providing feedback Senior Software Engineers are responsible for optimizing software application performance, including tuning algorithms, optimizing data access, and improving memory management Senior Software Engineers are responsible for ensuring that the software applications follow best practices in software development, including writing clean, efficient, and maintainable code, and implementing software security measures

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview C-language Developer Exp: 3 to 5 years No of Positions: 3 Job Location : Hyderabad. What you ll do Operating system development. Proficient in C and embeddedsystems. Experience in Linux driverdevelopment (Multimedia/PCIe) and application development. Multimedia/PCIe driverdevelopment experience. Hands-on experience withConfiguration Management tools like GIT, Perforce. Have an interest to constantly learningand sharing new findings. A quality mindset, ability forstrategic thinking and a drive to always improve. Who you are Proficiency in C-languageprogramming. Linux application programming Linux device driver development Embedded C, MMU, Cache policies Excellent debugging skills atkernel and user space and exposure to different debugging tools Knowledge of Multimedia, PCIe,Ethernet, TCP, I2C protocols, DMA framework is a plus. Make files Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. . Tessolve is not responsible for any losses incurred dueto such fraudulent activities

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview C-language Developer Exp: 5 to 15 years No of Positions: 3 Job Location : Hyderabad. What you ll do Operating system development. Proficient in C and embeddedsystems. Experience in Linux driverdevelopment (Multimedia/PCIe) and application development. Multimedia/PCIe driverdevelopment experience. Hands-on experience withConfiguration Management tools like GIT, Perforce. Have an interest to constantly learningand sharing new findings. A quality mindset, ability forstrategic thinking and a drive to always improve. Who you are Proficiency in C-languageprogramming. Linux application programming Linux device driver development Embedded C, MMU, Cache policies Excellent debugging skills atkernel and user space and exposure to different debugging tools Knowledge of Multimedia, PCIe,Ethernet, TCP, I2C protocols, DMA framework is a plus. Make files Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. . Tessolve is not responsible for any losses incurred dueto such fraudulent activities

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview C-language Developer Exp: 2 to 3 years No of Positions: 3 Job Location : Hyderabad. What you ll do Operating system development. Proficient in C and embeddedsystems. Experience in Linux driverdevelopment (Multimedia/PCIe) and application development. Multimedia/PCIe driverdevelopment experience. Hands-on experience withConfiguration Management tools like GIT, Perforce. Have an interest to constantly learningand sharing new findings. A quality mindset, ability forstrategic thinking and a drive to always improve. Who you are Proficiency in C-languageprogramming. Linux application programming Linux device driver development Embedded C, MMU, Cache policies Excellent debugging skills atkernel and user space and exposure to different debugging tools Knowledge of Multimedia, PCIe,Ethernet, TCP, I2C protocols, DMA framework is a plus. Make files Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. . Tessolve is not responsible for any losses incurred dueto such fraudulent activities

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Hardware Design - 5-8 years of experience Job Location : Whitefield ,Bangalore. What you ll do Leading the design,development, and implementation of high speed boards for servers, includingprocessors, memory, storage and network interfaces. Experience in full HDLC likeschematic design, PCB layout,SI-PI, mechanical and software integration. Experience in High Speed boarddesign with interfaces like PCIe 5.0,LPDDR4/5, SSD s,M.2,U.2 NVMe, SATA, USB,Ethernet etc Understanding customerrequirements, translating them into technical specifications, and working withother departments to ensure a robust and scalable solution Who you are Hands on experience in serverclass of board design with AMD or Intel GPU s and FPGA, with high speedinterfaces like PCIe 5.0,LPDDR4/5, SSD s,M.2,U.2 NVMe, SATA,CXL,USB,Ethernet.etc. Hands onexperience in Hardware Development Life Cycle like design, bringup, testing and validation of boards,functional testing, trouble shooting, debugging and Failure analysis. Experiencein at least one complete project starting from the high-level design to thefinal validation. Should beable to independently handle schematic design, design analysis and reviewcoordination with peer designers. Mentoringand guiding a team of hardware engineers, providing technical expertise andsupport, and ensuring team members adhere to industry standards. Collaboratingwith cross function teamin managing PCB layout, SI-PI simulations, Software development, mechanical , thermal, siliconIP Validation, BIOS and Driver Development/QA etc. and other stakeholders to ensure a cohesive andefficient system design. Experiencewith relevant design tools like Altium and Orcad. Handon experience in using instruments like high speed Oscilloscopes, DMM,electronic loads etc. Should be able to develop the board bring-up plan,be able to identify the test equipment required and execute independently. Experiencein preparing and reviewing hardware design documentation and issueinvestigation reports. GoodCommunication and interpersonal skills Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. . Tessolve is not responsible for any losses incurred dueto such fraudulent activities

Analyzing customer needs to determine appropriate solutions for complex technical issues Creating technical diagrams, flowcharts, formulas, and other written documentation to support projects Providing guidance to junior engineers on projects within their areas of expertise Conducting research on new technologies and products in order to recommend improvements to current processes Developing designs for new products or systems based on customer specifications Researching existing technologies to determine how they could be applied in new ways to solve problems Reviewing existing products or concepts to ensure compliance with industry standards, regulations, and company policies Preparing proposals for new projects, identifying potential problems, and proposing solutions Estimating costs and scheduling requirements for projects and evaluating results

Sr. Staff Systems Engineer, WiFi/Bluetooth in Bangalore, India Sr. Staff Systems Engineer, WiFi/Bluetooth Description Synaptics is leading the charge in AI at the Edge, bringing AI closer to end users and transforming how we engage with intelligent connected devices, whether at home, at work, or on the move. As the go-to partner for the world s most forward-thinking product innovators, Synaptics powers the future with its cutting-edge Synaptics Astra AI-Native embedded compute, Veros wireless connectivity, and multimodal sensing solutions. We re making the digital experience smarter, faster, more intuitive, secure, and seamless. From touch, display, and biometrics to AI-driven wireless connectivity, video, vision, audio, speech, and security processing, Synaptics is the force behind the next generation of technology enhancing how we live, work, and play. Synaptics is looking for Sr. Staff Systems Engineer, WiFi/Bluetooth to join our dynamic and growing organization. You will be responsible for developing and driving new technologies working on the PHY algorithm development, system integration, and working with RF/CHIP/SW team in validating and optimizing overall performance of connectivity chips. This position reports to the Director, WLAN System Algorithms and Architecture. Responsibilities & Competencies Job Duties Be involved in the algorithmic partition across software, firmware and hardware Lead development of connectivity PHY baseband algorithms and new features in wireless system that enhance system performance or reduce cost and die-size Be closely involved in the standardization activities in IEEE /WFA/or BT SIG Partner closely with RF, ASIC and SW teams to implement algorithms in the hardware/firmware Function as a highly skilled individual contributor and provide technical guidance in the systems design team Work closely with RF, Software, Algorithm, Chip, AE/FAE, Marketing teams for productizing WLAN&BT Combo chip for Home IOT and Automotive markets Competencies Strong research and development background in wireless technologies Track record of taping out multiple chips Proactive, self-starter, able to work independently in a fast-paced environment Well organized with strong attention to detail; proactively ensures work is accurate Positive attitude and work ethic; unafraid to ask questions and explore new ideas Ability to become part of and lead geographically distributed, cross functional project teams as necessary Resourceful and able to solve problems through adapting technology and a solid understanding of product architecture Analytical and able to make informed decisions based on experience Sets clear expectations and objectives, and brings parties together to drive key initiatives Ability to work within a diverse team and mentor developing team members Excellent verbal and written communication Strong team player with the ability to work within a geographically diverse team and willingness to mentor developing team members Qualifications (Requirements) Master s degree in Electrical Engineering with emphasis on Communication Engineering or Signal Processing or related field or equivalent 12+ years of experience working on systems engineering in modem design Proven experience in design and delivery of communication algorithms for the wireless PHY layer protocols such as 802.11 a/b/g/n/ac/ax/be, or cellular technologies (3G/4G/5G) or other wireless technologies Proven experience with successful tape-outs of new products Strong inter-personal skills Belief in Diversity Synaptics is an Equal Opportunity Employer committed to workforce diversity. Qualified applicants will receive consideration without regard to race, sex, sexual orientation, gender identity, national origin, color, age, religion, protected veteran or disability status, or genetic information.

Looking for Siemens EDA ambassadorsLead Software Engineer for Product Validation and Customer support for PowerPro We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. Do you want to use curiosity, passion, and creativity to make the lives of millions of people easier and betterJoin us – whichever path you take, we’re looking forward to seeing your point of view! As an integral part of the Siemens EDA team, you will contribute to Siemens EDA by growing efficiency and customer satisfaction Siemens EDA’s Power platform. This is an ambitious position that will assist in growing Siemens's EDA business in India. About the group: We are in DDCP (Digital Design Creation Platform group) which include top industry tools like Tessent, PowerPro, Catapult, Aprisa. We are part of DPRS (Devops, Product, Release & Support group) inside DDCP which works on cutting edge tools like PowerPro. Our team is responsible for Product Validation, Customer Support & Release work for PowerPro tool. PowerPro is the commercially available RTL sequential power optimization and power analysis tool. We are a team driven with lots of energy, synergy and passion. Job Responsibilities: Work as an integral part of Product Validation and Customer Support team to validate and educate feature of PowerPro. Being the internal end-user of the tool, validate all features and report issues. Development of test plan and writing test cases. Take measures to improve quality of Product and test environment. Support and debug customer test design methodologies using our products. Participate in architecture reviews and involve in defining features prototyping. Get along with field teams to understand customer design flows requirements and propose measures to optimize and improve flow results. Analyse customer reported bugs and plug gaps in testing, incorporate newer designs/flows. Use technical expertise to respond to customer inquiries, demonstrate products. Provide field application support to customer. Role may involve interaction with customers on critical issues to narrow down the problem. Lead 1-2 junior folks or Intern. guide them and help them in day-to-day activities. Technical Skills (Must have): B.Tech (EE/ECE) or M.Tech (VLSI/Microelectronics) with working experience of 5+ Years. Good knowledge of ASIC design flows, Verification, Digital Logic, Synthesis, HDL Languages Verilog/VHDL/SV. Good understanding of low-power SOC design principles. Experience with class of products like simulation, synthesis, Place & Route, etc. Excellent problem-solving and debugging capability. Technical Skills (Good to have): Low Power concepts, RTL/Gate Simulation and Emulation, SPEF, Different tech nodes. Knowledge of one of the scripting languages like Perl, Tcl. Python will be a plus. Worked on designs to apply power solutions, UPF etc. Different Tool knowledge like Power Artist, Joules, Prime Power/PTPX, Questa, VCLP, DC etc. Worked in EDA CAD team for RTL Soft Skills: Excellent verbal and written communication skills. Self-starter, motivated and strong teammate. Team Contributor, Quick learner. Hard working, sincere and committed to work. Team leader We’ve got quite a lot to offer. How about you A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Transform the everyday Accelerate transformation #li-eda #li- Hybrid

Develop Detailed Documentation for Verification Strategy and Test Plan for IP, Subsystem and SoC. Directed and Random Verification at IP, Subsystem and SoC Level for complex ARM / RISC-V processor based MCU, MPU products, Mixed Signal SoCs, Processors, Memory Subsystems, Connectivity Platforms, Analog, Security Acceleration, General Peripherals. Perform Functional and Code Coverage Analysis. Experience and Skills Required 5 to 15 years of experience in IP SoC Verification. Expertise in Verilog, System Verilog, UVM, Constrained Random Verification, Formal Verification, Mixed Signal Verification, Post-Layout Gate Level Simulations, Code Coverage and Functional Coverage analysis. Development of Verification IP and Testbenches. Experience with AMS simulations desired. Must have strong debug and analytical capabilities, root cause analysis. In-depth understanding of SoC Design Flow, RTL Implementation, Analog Circuit models. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Front End Integration of Digital, Analog IPs and Subsystems to build complete SoC Netlist. IOMUX and Padring generation and integration. Design of SoC Specific Logic IPs. Perform quality checks like Lint and CDC at SoC level. Implement all feedback from Verification and Physical Design teams for all changes required. Develop SoC level Testbench for RTL and Postlayout Simulations. Collaborate with ATE and Test teams and deliver test patterns for Probe and Package level testing. Support Verification and Post-Silicon Debugging of issues. Experience and Skills Required 10-15 Years Experience in front end integration for complex SoCs. Strong scripting skills. Hands on experience in RTL coding, Lint, CDC. Experience in developing IOMUX and Padring. Expertise in developing testbench for SoC to support directed and random verification. Experienced with working with ATE teams for delivery of test patterns. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Development of Specifications, Micro Architecture, RTL Development for Digital IPs. Setup and use standard EDA tools for Verification, Lint CDC, Synthesis, Power Analysis tools for Verification and Ensuring PPA for IP developed. Conduct Reviews for Documentation, RTL and Verification Tests. Experience and Skills Required 5 to 15 years of experience in SoC/IP Design. Expertise in Writing Detailed IP Specifications, Micro Architecture, IP design, Subsystem and SoC level integration. Expertise on RTL Development. Follow Coding Standards, expertise on Lint, CDC tools, verification and debugging of test cases, code and functional coverage analysis. In-depth knowledge of Clocking Methodology, Low Power Implementation. Hands on experience on writing constraints and exceptions, performing Synthesis, Timing Analysis and Design for Test Implementation. Experience of power partitioning and usage of CPF/UPF. Exposure to IP Design for ARM Microcontrollers based SoCs. Good understanding of AMBA bus protocols (AXI, AHB, ATB, APB). Knowledge of one or more of the interface protocols, PCIe, DDR, Ethernet, I2C, UART, SPI. Experience in Matlab Simulations and Implementing Signal Processing IPs like Digital Filters, Math Functions or FFT engines. Experience in developing Security IPs for various Encryption standards. Experience in implementing On-chip Memory and Flash controllers. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

Define SoC Function, Performance requirements. Define SoC Connectivity, Interconnectivity, Memory Map, Interrupt Map, Pin Muxing, Power Management, SoC Clock Distribution, SoC Debug. Define Data Flow and Use Cases. Maintain SoC Die Size and Power Estimates and ensure competitive PPA. Close collaboration with SoC Design and Verification Teams. Experience and Skills Required 10 to 15 years of experience in SoC / IP Design, IP Architecture SoC Architecture. Experience with ARM Microcontrollers, Memory and Interconnect technologies. Hands-on experience with defining Clocking Strategy, Power Management and Low Power strategies. Must be familiar with various Connectivity standards, SoC Security. Hands on experience with IP Design / Micro Architecture required. Experience with Signal Processing IP is preferred. Good Understanding of SoC Front End and Back End Design Flow, SoC Verification and Validation flows. Must have deep understanding Software requirements - Secure Boot, RTOS, Device Drivers. Soft Skills Strong analytical, problem-solving, and hands-on skills. Self-driven and thrives when facing open-ended tasks. Start-up mentality: fast-paced, flexible and team-oriented. Good written and verbal communication skills with great documentation skills. Flexibility to work with varied schedules and tolerance for ambiguity.

System Architecture Design Cross-Functional Collaboration Technical Leadership Compliance and Standards Performance Optimization Innovation and Development Required Candidate profile We are seeking an experienced EmbeddedSystem Architect to lead the architecture and development of embedded systems within the automotive electronics domain.

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. 3-6 yrs of experience Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.,

Tasks: Verificationof SoCs, automotive ASICs, subsystems, IPs. Application of Metric-driven Verification (MDV) and/or Formal Verification methodologies Developing and tracking of Verification plans Develop verification environments from scratch Create VIP Integration of VIP ( Verification-IP ) Measure and analyze regression results Continuous improvement of verification methods/tools/flows/processes together with EDA partners Requirement: 5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM. Sound knowledge of constrained random verification, UVM/OVM Sound knowledge in System Verilog. Experience of developing functional coverage code, coverage analysis. Experience of developing verification environments from scratch is desirable. Good hands on experience with cadence/Synopsys/Mentor tools. Exposure to configuration management, bug tracking tool etc. Knowledge of scripting language, Perl TCL etc. Good experience with AMBA protocols Working knowledgeon ARM processor-based subsystem/SoC verification Formal verification experience is a desirable but not must. Must have been a part of one or more ASIC/SoC tape outs. Knowledge of VHDL/VERILOG. SPECMAN knowledge is a desirable but not must.

Role & responsibilities: Extensive hands on and teaching experience on Digital / SV /UVM/ Verilog / VHDL /DFT tools Extensive experience in Back-end design Experience on Mentor Graphics EDA flow is an added advantage Responsible for development and support of Projects. Responsible for Debugging the source codes in Verilog, SV, and UVM. Responsible for Training Delivery and Support Preferred candidate profile Sound Knowledge on Digital / Verilog / VHDL / SV / UVM / DFT / Back-end design 3 to 8 years industry/teaching experience Good communication & presentation skill

About Client Hiring for One of the Most Prestigious Multinational Corporations! Job Description Job Title : VLSI Back-end Services Practice Head/ VLSI Director Engg. Required skills and qualifications : Create differentiated VLSI Services offerings, capabilities, and talent to exponentially grow VLSI services business. Ability to engage with customer design managers in technical discussions and secure design wins Create strong VLSI technical teams through training/upskilling and focused hiring. Mentor the VLSI team to ensure their skills are continuously advanced & aligned to customer/industry needs. Build strong customer relationships and deliver VLSI services projects. Create differentiated proposals to win new projects. Work within in-house resourcing teams and external partner ecosystem to staff and ramp-up VLSI team based on customer needs Strong technical expertise in ASIC backend processes: physical design & verification, implementation, and optimization, timing analysis, power analysis, Design For Test (DFT). Strong understanding of semiconductor technologies, including standard cells, IOs, memory, and IP integration. Hands-on expertise with commercial EDA tools from Synopsys, Cadence or Siemens Intimate familiarity with Verilog and standard design formats (LEF, DEF, SPEF, etc.) Proficiency in scripting languages like Python, Perl, or Tcl for automation purposes. Familiarity with advanced node technologies such as 7nm, 5nm, or below. Good industry connects with EDA tool companies, foundries and Tier 1 semiconductor companies Drive innovations and optimizations to enhance power, performance, and area (PPA) metrics. Maintain awareness of emerging technologies and methodologies to improve backend development practices. Exposure to ASIC-package codesign a plus. Create and leverage VLSI partner ecosystem for expanding offerings and talent Stay updated on semiconductor industry trends and competitor activities to refine the strategy accordingly and gain customer mindshare. Work closely with design, verification, and manufacturing teams to align backend strategies with overall ASIC development goals. VLSI services Strategy, Business Plans and roadmaps SoW and MSA reviews Roles and Responsibilities: Drive VLSI services strategy, offering, capabilities, and talent creation and scaling Own and meet the VLSI services business growth Collaborate with academia, partners and talent teams to grow VLSI talent Create differentiated design methodologies, offerings and solution demos to showcase at industry events Collaborate with Presales and Sales teams to develop compelling customer propositions and sales collateral Ability to engage confidently at senior levels within customer organizations Review and ensure smooth delivery of VLSI services engagement Utilize industry trends, competitive insights to enhance sales strategies and provide input to offering owners. Excellent stakeholder management and client facing skills Excellent communication and analytical skills Qualification : Any Graduate or Above Relevant Experience : 15 to 24 yrs Location : BANGALORE/HYDERABAD CTC Range : 60 TO 80 LPA Notice period : ANY Mode of Interview : Virtual Mode of Work : In Office Sana.F Staffing analyst - IT recruiter Black and White Business solutions PVT Ltd Bangalore, Karnataka, INDIA sana.f@blackwhite.in I www.blackwhite.in +91 8067432462

About Client Hiring for One of the Most Prestigious Multinational Corporations! Job Description Job Title : VLSI Front-end Services Practice Head/ VLSI Director Engg Required skills and qualifications : Create differentiated VLSI Services offerings, capabilities, and talent to exponentially grow VLSI services business. Ability to engage with customer design managers in technical discussions and secure design wins Create strong VLSI technical teams through training/upskilling and focused hiring. Mentor the VLSI team to ensure their skills are continuously advanced & aligned to customer/industry needs. Build strong customer relationships and deliver VLSI services projects. Create differentiated proposals to win new projects. Work within inhouse resourcing teams and external partner ecosystem to staff and ramp-up VLSI team based on customer needs Strong technical expertise in ASIC frontend development: logic design & verification (including UVM), power specification (e.g. UPF), timing specifications (SDC), formal verification and emulation Hands-on expertise with commercial EDA tools from Synopsys, Cadence or Siemens Intimate familiarity with Verilog and standard design formats (LEF, DEF, SPEF, etc.) Good industry connects with EDA tool companies, foundries and Tier 1 semiconductor companies Exposure to ASIC-package codesign a plus. Create and leverage VLSI partner ecosystem for expanding offerings and talent Stay updated on semiconductor industry trends and competitor activities to refine the strategy accordingly and gain customer mindshare. VLSI services Strategy, Business Plans and roadmaps SoW and MSA reviews Roles and Responsibilities: Drive VLSI services strategy, offering, capabilities, and talent creation and scaling Own and meet the VLSI services business growth Collaborate with academia, partners and talent teams to grow VLSI talent Create differentiated design methodologies, offerings and solution demos to showcase at industry events Collaborate with Presales and Sales teams to develop compelling customer propositions and sales collateral Ability to engage confidently at senior levels within customer organizations Review and ensure smooth delivery of VLSI services engagement Utilize industry trends, competitive insights to enhance sales strategies and provide input to offering owners. Excellent stakeholder management and client facing skills Excellent communication and analytical skills Qualification : Any Graduate or Above Relevant Experience : 15 to 24 yrs Location : BANGALORE/HYDERABAD CTC Range : 60 TO 80 LPA Notice period : ANY Mode of Interview : Virtual Mode of Work : In Office Sana.F Staffing analyst - IT recruiter Black and White Business solutions PVT Ltd Bangalore, Karnataka, INDIA sana.f@blackwhite.in I www.blackwhite.in +91 8067432462

Position: Digital Head Semiconductor BU (Confidential Search) Location: Hyderabad / Chennai/Bangalore We are partnering on a confidential leadership mandate for a Digital Head to drive digital strategy, delivery excellence, and innovation across global semiconductor programs. Key Responsibilities: Lead and grow multi-disciplinary teams Semiconductor Digital Design (RTL, PD, DV, DFT) Own delivery of complex SoC/ASIC programs across global accounts Define capability roadmap, drive innovation in AI/ML + EDA Partner with sales, pre-sales, and engineering to shape go-to-market Ideal Profile: 15 to 25 years in semiconductor design, with 5+ years in senior leadership B.E./B.Tech in ECE/VLSI; M.Tech/MS preferred with 20+ years of experience Proven track record in RTL, DV, DFT, and EDA toolchains Must have Leadership experience Candidates currently or previously working in these companies would likely have relevant experience) Semiconductor Product/Design Companies: Engineering Services/Design Services Companies: EDA & IP Companies If you meet 80% of the requirement contact : bdm@intellisearchonline.net M 9341626895(whatsapp) Role & responsibilities

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 10 years of experience with software design and development for software layers found in ASIC such as boot, drivers, embedded firmware, libraries, and API for applications. 5 year of experience in people management and developing employees. 5 years of experience driving ASIC architecture decisions from a software point of view. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. Knowledge of interaction types between hardware and software for different types of standard hardware blocks, CPU and accelerators. Experience with Android OS and similar, with a focus on power management, debug, quality of service or drivers. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Software Manager, you will understand software product requirements, use cases and applications, and how they relate to specific hardware blocks or sub-systems. You will represent the goal of the software team and their constraints, working at system architecture definition of hardware blocks with the hardware architects, and the implementation definition working with the Hardware Implementation team. You will define or influence their work with the goal of ensuring fulfillment of software requirements, striving for optimal software programming model and interfaces, discuss and come to an agreement on hardware/software trade-off solutions, ensure scalability to future software and applications, and backwards compatibility as much as possible. You will make decisions using a data driven approach adopting or developing a modeling platform that will help you side your requests. You will also be required to estimate the complexity of specific implementations with the intent of supporting educated estimation of staffing and schedule required by managers or planners. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Responsibilities Collaborate with company-wide stakeholders like product management, architecture, silicon architecture, silicon implementation, silicon software, and product software engineering team, to identify user experiences characteristics and how they can be mapped onto hardware in existence or in development. Understand interactions between hardware components and drive towards the definition of architecture and block s interactions design, providing options or trade-offs, identifying issues and driving them to resolution. Design architecture and software interfaces that enable a software programming model that can ultimately delight our application developers, and that can let them make use of hardware accelerators seamlessly and timely. Design and improve hardware from generation to generation based on the results of productization efforts, and to reduce technical debt.

Minimum qualifications: Bachelor s degree in Electrical Engineering or Computer Engineering, or equivalent practical experience. 15 years of experience in ASIC RTL design. Experience with RTL design using Verilog/System Verilog and microarchitecture. Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: Master s degree in Electrical Engineering or Computer Engineering. Experience driving multi-generational roadmap for IP development. Experience leading interconnect IP design team for low power SoCs. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Lead a team of people to deliver fabric interconnect design. Develop and refine RTL design to aim power, performance, area, and timing goals. Define details such as interface protocol, block diagram, data flow, pipelines, etc. Oversee RTL development, debug functional/performance simulations. Communicate and work with multi-disciplined and multi-site teams.

Minimum qualifications: Bachelor's degree in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 3 years of experience in software development in the area of consumer electronics or other embedded systems. 2 years of experience driving application-specific integrated circuit (ASIC) architecture , OS kernel, system on a chip (SoC) architecture, power and performance analysis. Preferred qualifications: Master's degree or PhD in Electrical/Electronics Engineering, Computer Engineering, Computer Science, or equivalent practical experience. 5 years of experience in software design and development for software layers found in SoC (e.g., bootloaders, kernel, hypervisor, secure monitor, device drivers and embedded firmware). Experience with Android and any Real-time OS. Knowledge of interaction types between hardware and software for different types of standard hardware blocks, CPU, and accelerators. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The Silicon Software team has the long term charter to develop software for a variety of custom silicon being developed within Google. This includes IP for many diverse applications. We are working generations ahead of the market to enable groundbreaking features. In this role, you will be involved in developing software across a few domains such as platform software (BSP, firmware, drivers) delivered to our customers, silicon validation software to be used in the pre-silicon, and post-silicon validation, compilers, drivers, runtime, embedded firmware and tools in the machine learning domain, security architecture and systems, system power and performance, related engineering productivity and test engineering activities.Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Responsibilities Collaborate with stakeholders to identify user experiences characteristics and how they can be mapped onto hardware and software. Design architecture and software interfaces that enable application developers to make use of hardware accelerators and other IP. Understand interactions between hardware components, identify issues and bottlenecks, provide trade-off options and drive them to resolution. Help design or improve hardware from generation to generation based on lessons learned from productization efforts, and to reduce technical debt.