776 Asic Jobs - Page 12

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Excellent Design verification domain expertise. Develop test strategy, TB architecture and test plan for new IP’s/new features Develop strategies for re-useable, scalable and enhance Sub system level verification environment Excellent C/System Verilog/Verilog skills to handle C based TB environment Strong skills in debug, post silicon debug-failure re-creation and root cause analysis Scripting proficiency - PERL, Python, for developing applicable automation AMBA, AXI bus protocols Power intent verification, GLS etc. Capable of communicating effectively with all stakeholders across the globe Capable of seeding a new team for new IPs, able to hire and expand the team in expertise and efficiency Capable of mentoring the team members for their career growth, maintaining diversity in the team, collaborating with other leads and managing multiple parallel projects Take initiatives to enable various ideas for improving efficiencies. Good to have: Image Processing, DSI/DP/HDMI Protocols Good knowledge of new methodologies, flows and tools to be incorporated. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Senior/Lead ASIC Verification Engineers with an experience of minimum 5+ yrs Very strong experience with Verilog, System Verilog and UVM Working experience on development of Verification IP of layered protocol High Speed peripheral Interface protocol PCIe Gen4+ onwards, PCIe Experience is a must Strong knowledge on UVM RAL and common register interfaces such as APB, AHB, AXI (ARM), RAM. Working experience on scripting and automation Strong Past experience of developing verification plan from scratch and testbench development using the detailed Specification and TestPlan from the scratch Strong base knowledge on digital design, blocks/components Strong debugging skills and Good knowledge of assertions and functional coverage coding and closure. Good knowledge on code coverage analysis and closure. Good knowledge of any scripting language Strong documentation and presentation skills. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Looking for a highly talented and a technically strong leader with an eye for quality to lead a high performing and talented team of engineers in the implementation domain for Display Sub-System. Able to handle multiple project execution that are time critical and complex Able to communicate effectively with all stakeholders across the organization Able to collaborate with cross functional teams for upholding the best practices and enabling smooth execution Focus on improving execution efficiency and improve on the optimizations in area, power and performance. Able to grow the team in terms of technical depth and size as we do more and more projects Able to innovate and bring fresh ideas Bachelor’s or master’s degree in engineering with 9-13+ Years of experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Responsibilities include Synthesis, LEC, Low power checks, Memory BIST insertion, Constraints validation. Development of signoff quality constraints and the development of power intent constraints. May also include running RTL Lint, CLP, MEMBIST, DFT DRC etc. TCL script development in addition to running/analyzing/debugging designs. Hands on with Synopsys DCG/Genus/Fusion Compiler. Hands on with Synopsys Prime Time including constraint development for complex blocks with multiple clock domains. Hands on with Cadence Conformal LEC and Cadence Conformal Low Power including UPF development Experience with either RTL development or Physical Design is also a plus

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in connectivity and new possibilities. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform its potential into world-changing technologies and products. In the role of GPU Functional Verification Engineer , your project responsibilities will include the following, Develop deep understanding of 3-D Graphics hardware pipeline, feature sets, data paths, block functionalities & interfaces Strategize, brainstorm, and propose a DV environment, develop test bench, own test plan, debug all RTL artefacts, and achieve all signoff matrices Engage with EDA vendors, explore new and innovative DV methodologies to push the limits of sign off quality Collaborate with worldwide architecture, design, and systems teams to achieve all project goals Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Currently, we are looking for candidates who can match one or more of the profiles listed below, Strong knowledge of UVM based System Verilog TB Knowledge of GPU pipeline design is a plus, not mandatory Proficiency with formal tools – working knowledge of Property based FV is a plus, not mandatory Strong communication skills (both written and verbal) Most importantly, ability to learn, improve and deliver Experience Minimum 3 years of Design verification experience Senior positions will be offered to candidates with suitable years of experience and proven expertise matching the profiles listed above Education BE/ME/M.Sc. in Electrical, Electronics, VLSI, Microelectronics, or equivalent courses from reputed universities Selected candidates will be part of the GPU HW team which is passionate about developing and delivering the best GPU Cores for all Qualcomm Snapdragon SOC products. Qualcomm GPU is an industry-leading solution which is driving the benchmarks in mobile computing industry and the future of mobile AR/VR. The pre-Si verification team in Bangalore is currently heavily involved in the following UVM/SV based constrained random test bench for functional verification Subsystem level TB for complete GPU workload analysis and compliance Emulation platforms to analyze performance and pipeline bottlenecks Formal tools – both for reduced time to bug & property based FV sign-off Power Aware & Gate level simulations to deliver a high-quality GPU implementation Perl/Python scripts for automation in managing regressions, optimize run time, manage database and bug

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Candidate will be responsible for IP Level Verification of Qualcomm Spectra Camera Sub Systems Modules for next gen Qualcomm product portfolio. This role will require the candidate to understand details of the camera signal processing modules, verify them at module & subsystem level for enhanced features. Engineer should independently be able to own the verification of IP level modules end to end with continuous enhancements and collaborate with IP Verification, Design and System leads. Necessary skills/experience: 1+ years of experience in RTL design verification using SystemVerilog/UVM and industry-standard simulation tools (Mandatory) Experience in power aware simulation is a big plus Experience on camera verification is a big plus Expertise in Coverage closure , RTL debug skills Expertize in SV – UVM, Assertions based verification, DPI Familiarity in Firmware/emulation (exVeloce) based verification , GLS Familiarity with bus protocols like AHB, AXI, ARM based system architecture Experience with Perl, Python, or similar scripting language Excellent problem solving skills & Verification aptitude Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Additional PMIC Systems & Validation Engineer Team & Product Overview: Qualcomm's Power Management Systems, Validation & Integration team (PMIC-SVI) leads the industry in the system architecture and post-silicon validation of high-performance feature-rich Power Management Integrated Circuits (PMICs), that are embedded in our Chipsets - for smartphones, tablets, laptops, wearables and a variety of cutting-edge consumer electronics. This team gets to work on state-of-art technology to enable products with world’s leading brands. A typical Qualcomm PMIC is a highly advanced IC that has a multitude of IPs viz. switching DC-DC converters, linear regulators, clock oscillators, battery charger, fuel gauge, LED drivers, and ADCs. Additionally, there is an embedded mini-processor running critical firmware (FW) to support power sequencing, interrupt servicing, crash handling and various device reset scenarios. It is also responsible for maintaining various stability & performance related configurations that are part of SoC software driver initializations. Furthermore, it provides an intelligent-framework for sequencing of time-critical-operations, which otherwise can't be guaranteed by any OS / higher-level software. Often, Qualcomm chipset solutions contain multiple PMICs working together in sync – which together constitute a ‘PMIC-System’. Job Responsibilities This job involves a mix of Architecture, HW Systems, Functional Validation, Chipset integration & customer issue debug support. We are looking for Systems & Validation engineers with preferably 1 -5 years of experience in analog/power electronics. Depending on your experience level and area of technical expertise you will own and participate in systems definition, HW/SW debugging and validation of PMIC solutions by partnering with various engineering teams like Analog/Digital Design, Software and Customer Engineering in a fast-paced environment. Systems involves coming up with a Top-Level specification (involving HW/FW/SW level partitioning of feature-design, HW Register interfaces, memory sizing, protocol selection, multi-PMIC connectivity grid, debug framework support, etc) to satisfy all chipset level requirements. Validation involves coming up with a comprehensive functional validation plan (that covers both manual and scripted automated test cases), executing them within stipulated time-period, analyzing results at HW-level (via signal measurements), debugging issues & creating reports. Engineers will be responsible to perform risk assessment of development and validation plans; and interact with PMIC Product Management, Design & Characterization teams; other SoC HW/SW Architecture, Development & Validation teams; and finally Customer-Engagement teams across worldwide sites. Education A Bachelor's degree in Electronics related Engineering is a must. Master’s degree is preferred esp. with specialization in VLSI / Microelectronics, Power Management, etc. Minimum Qualifications We are looking for applicants with 1-3 years of job-experience – relevant to various HW/S aspects of any electronic product development. They should be well-versed with knowledge of entire ASIC Flow (from concept-stage to commercial-product support). Preferred Qualifications Applicants should be aware of fundamentals of PMIC, Power Management, Microcontroller architecture, basic-firmware & HW-SW interaction. Applicants should also have strong hands-on lab-experience in Post-Si Validation. (HW-level Bench measurement and/or SW-level logs-based verification). Preferred Skills: Hands-on ability & comfort in using various lab instruments like oscilloscopes, power supplies, JTAG debuggers etc. Good understanding of PMIC, Power Electronics , digital & embedded electronics concepts Good Hardware Debug Skills related to DC -DC (SMPS, LDO) converters preferred. Good programming skills in at least one of the followingC#, F#, Python, Perl, LabVIEW or any other scripting language (used in VLSI/Embedded Domain) + understanding of few OOPS concepts. Familiarity with HW schematics and ability to trace inter connections on a PCB. Good analytical & communication (verbal/written) skills. Ability to seek information pro-actively, understand priorities and juggle multiple tasks in a highly paced environment. Experience in automating test-cases via SW-control for HW-systems Ability to come up with a High-Level Strategy for any objective and being able to break it into Mid-level flows & Low-level tasks – for efficient execution. Prior experience in leading & executing white-box validation efforts of a HW-module or sub-module, is a big plus. Exposure to Assembly-language programming (for microcontroller) is good-to-have. Exposure to tools like JIRA and GIT are a plus. Keywords PMIC, Power Systems, System Architecture, switch mode power supply, SMPS, DC-DC, LDO, ADC, functional Validation, test automation, Voltage Regulators, Battery Chargers, Battery Management/Gauging

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification engineer candidate will be responsible to manage I2C/I3C/SPI/UART/UFS/ /high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage (code, toggle, functional). Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solutions to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ years’ experience in verification domain. Prior work experience on IP level or Soc level. Prior work on Serial Protocols I2C/I3C/SPI/UART , SDCC , UFS ,USB Good understanding of processor-based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AHB, AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelor’s degree in Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Verification engineer candidate will be responsible to manage I2C/I3C/SPI/UART/UFS/ /high speed IP verification at one or more SoC (System On Chip) during project work. Responsibilities Understand the design specification and implementation, define the verification scope, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. Responsible to implement and analyze system Verilog assertion and coverage (code, toggle, functional). Work alongside other members of the verification team to analyze, develop and execute verification test cases and able to provide relevant solutions to issue. Collaborate with architects, designers, and pre and post silicon verification teams to accomplish your tasks. Adhere to quality standards and good test and verification practices. B.E/B. Tech/M.E/M. Tech in electronics with 5+ years’ experience in verification domain. Prior work experience on IP level or Soc level. Prior work on Serial Protocols I2C/I3C/SPI/UART , SDCC , UFS ,USB Good understanding of processor-based Soc level verification which includes native ,Verilog ,system Verilog and UVM mix environment. Hand on experience with verification tools such as VCS, waveform analyzer and third party VIP integration (such as Synopsys VIPs). Hands on experience in UVM. C/C++ ,System Verilog verification language. Good understanding of AHB, AXI-AMBA protocol variants. Can work with scripting language (shell, Makefile, Perl ) Strong understanding of design concepts and ASIC flow. Good problem solving , analytical and debugging skill is must. Minimum Qualifications: Bachelor’s degree in Electrical/Electronics Engineering, Engineering, or related field. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualifications: Bachelor’s or Master’s degree from a top-tier institute. 2- 5 years of experience in physical design from product-based companies. Experience: Proven experience in managing complex subsystems and small teams. Proficiency in synthesis, place and route (PnR), and sign-off convergence, including Static Timing Analysis (STA) and sign-off optimizations. Job : Expertise in meeting demanding Power, Performance, and Area (PPA) requirements for complex subsystems/System on Chips (SoCs), place and route, and IP integration. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Strong understanding of circuit design, device physics, and deep sub-micron technology. Experience working on multiple technology nodes in advanced processes. Proficiency in automation to drive improvements in PPA.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job AreaHardware Engineering (Verification) QCT's Bangalore Wireless R&D Bluetooth HW team is looking for experienced Wireless HW design verification engineers to work on Qualcomm’s best in class chipsets for mobile phones, wearables and IOT. Candidate will be working with ASIC designs on the latest technology nodes. This role will require the candidate to understand and work on all aspects of VLSI Verification cycle like Testbench architecture, Verification Planning, Testbench and Test development, Verification closure with best-in-class methodologies including simulation, emulation, GLS and Formal techniques. The role also requires deep understanding of the Bluetooth Hardware Architecture. Candidate will require close interactions with Global Design, Systems, SoC, Validation and FW teams for design convergence and required to work with minimal supervision. Candidate must be able to take ownership of IP/Block/Sub-System verification. Incumbent will be analyzing HW design spec and develop a verification test plan/strategy for it, breaking down the work for new features, perform feasibility studies, estimate effort and mitigate risk. The role also required the candidate to mentor new joiners and less experienced colleagues. The candidate will work with design team on RTL debug during Pre-silicon HW development phase. Skills/Experience 6-10 years of strong experience in design verification Strong knowledge of HDLs like Verilog, System Verilog Proven experience of writing efficient constraint random tests Proven experience of building or maintaining a medium to complex SV/UVM environments Strong debugging and analytical skills and independent problem solving ability Proficient in debugging RTL/TB issues using Verdi or similar tools Demonstrate good judgment in selecting methods and techniques for obtaining solutions Strong communication skills, both written and verbal, with ability to evaluate and create testplans detailing complex features and relationships Bachelor’s or Master’s Degree in Engineering in Electronics, VLSI, Communications or related field Minimum Qualifications Bachelor’s Degree in Engineering in Electronics, VLSI, Communications or related field 6 years of VLSI industry experience in verification Preferred Qualifications Exposure to Bluetooth/BLE Technologies Knowledge on scripting languages such as Perl and(or) Python Skills: Functional Verification, Functional/Code Coverage, SystemVerilog Assertions, Universal Verification Methodology (UVM), Verification IP (VIP) Integration, SoC Integration, Formal checks Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Join Qualcomm's design verification team in verifying the Digital Low Power IPs for exciting products targeted for 5G, AI/ML, compute, IOT, and automotive applications. The team is responsible for the complete design verification lifecycle (including Functional, Low Power Verification, Gate Simulation, Formal Verification) from system-level concept to tape out and post-silicon support.Responsibilities:Define pre-silicon and post-silicon testplans based on design specs and using applicable standards working closely with design team.Architect and develop the testbench using advanced verification methodology such as SystemVerilog/UVM, Low power verification, Formal verification and Gate level simulation to ensure high design quality.Author assertions in SVA, develop testcases, coverage models, debug and ensure coverage closure.Work with digital design, analog circuit design, modeling, controller/subsystem, & SoC integration teams to complete the successful IP level verification, integration into subsystem and SoC, and post-silicon validation.Minimum Qualifications:Master's/Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field.8+ years ASIC design verification, or related work experience.Knowledge of a HVL methodology like SystemVerilog/UVM.Experience working with various ASIC simulation/formal tools such as VCS, Xcellium/NCsim, Modelsim/Questa, VCFormal, Jaspergold, 0In and others.Preferred Qualifications:Experience with Low power design verification, Formal verification and Gate level simulation.Knowledge of standard protocols such as Power Management Flows, PCIe, USB, MIPI, LPDDR, etc. will be a value addExperience in scripting languages (Python, or Perl).

The Opportunity Were looking for the Wavemakers of tomorrow. We have a global presence with multiple development centers in North America, EMEA, China, Taiwan, and India. To support our growth and expansion plans in India, we are seeking to hire exceptional talent to join our Bangalore Office. You will lead customer engagements and new product programs that are critical to the success of the business unit. You will collaborate with a diverse, global team that is on a mission to deliver world-class SoC products and programs What Youll Do: Take SoC products through the Product Lifecycle (PLC) from Concept, through Planning, Development, Prototyping and Testing, Pilot Production to release to Mass Production Support pre-sales/business teams to win new designs & expand Alphawave Semi s footprint. Understand the customer s IC development requirements and roadmaps and scope and develop execution plans for their devices/systems. Program planning, schedules, budgeting, risk assessment, resource planning and management, and tracking customer activities associated with the programs. Track program financial performance as a function of our deliverables and expense profile Review, disposition and communicate changes in scope / schedule / expense. Plan and manage delivery of engineering samples (ES), customer samples (CS) and NPI volume ramp. Manage customer feedback and work with the team to ensure customer expectations are exceeded. Conducts regular meetings to ensure customers and internal teams are clear on expectations and problem-solving actions are in place to address issues in a timely manner. Maintain adequate technical depth and managerial skill to address program and product issues. Maintain management and key stakeholder alignment. Present status of your assigned program to executive management during program reviews What Youll Need : Bachelors or Masters Degree in Electronics/Electrical/Computer Engineering with 5 or more years of relevant experience in a semiconductor or electronics product company Technical appreciation of ASIC/SoC flows (front end and backend development processes, product and test engineering, char and validation, hardware/software design) Customer and program management skills, ability to organize information for internal/external consumption. Knowledge of Microsoft Project and Office Tools and other program management tools for use in complex semiconductor programs Able to motivate and energize teams and lead by influence in a matrixed organization. Strong communication skills and the ability to keep calm and make progress in high stress situations. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

Architecting and implementing advanced RTL designs for next-generation high-performance DDR PHY and related IP cores. Analyzing and interpreting standard and functional specifications to create detailed architecture and micro-architecture documentation for medium to high complexity features. Executing hands-on RTL coding, synthesis, CDC analysis, and debug, ensuring robust and efficient designs. Developing and executing comprehensive test plans to validate functional correctness and performance. Collaborating with global teams and interacting with customers to understand and refine specification requirements. Mentoring junior engineers, providing technical guidance, and potentially leading small project teams to drive successful project outcomes. Continuously improving design flows and methodologies by leveraging feedback and industry best practices. The Impact You Will Have: Advance the performance and reliability of industry-leading IP cores, directly contributing to Synopsys reputation for technical excellence. Enable customers to deliver cutting-edge products by providing robust, high-quality digital design solutions. Drive innovation in the development of next-generation memory and interface technologies. Foster a culture of technical mentorship and knowledge sharing within a global engineering team. Strengthen Synopsys collaborative relationships with key industry partners and customers. Shape the future of silicon design through your technical contributions and leadership. What You ll Need: Bachelor s or Master s degree in EE, EC, VLSI, or related field, with5+ years of relevant industry experience. Strong hands-on experience in RTL design using Verilog/SystemVerilog for ASICs, including data path and control path architecture. Expertise in design trade-offs (area, latency, throughput) and familiarity with protocols such as DDR, PCIe, USB, or HBM. Proficiency with synthesis, CDC analysis, lint, static timing analysis, and formal verification flows. Experience in developing and interpreting functional specifications, and translating them into detailed design documents. Knowledge of scripting languages (Perl, Shell) for automation is a plus. Prior experience as a technical lead or mentor is highly desirable. Who You Are: Innovative and detail-oriented, with a strong analytical mindset. Effective communicator who thrives in collaborative, cross-cultural environments. Proactive problem solver with a high degree of initiative and ownership. Team player who values diversity and inclusivity in thought and approach. Resilient, adaptable, and eager to continuously learn and grow. Strong leadership and mentoring skills, with a passion for developing others

About Tessolve Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide a full turnkey solution for silicon bring-up, validation, and characterization. We are a preferred partner for several top-tier semiconductor companies and are constantly expanding our engineering capabilities. Job Description We are looking for a passionate and skilled DFT Engineer with 1 3 years of experience in Design for Test to join our VLSI team in Bangalore. The ideal candidate will be involved in DFT architecture, implementation, and validation across various SoC/ASIC projects. Job Title: DFT Engineer Experience: 1 to 3 Years Location: Bangalore Key Responsibilities Implement and verify DFT features such as scan insertion, boundary scan (JTAG), MBIST/Logic BIST. Perform ATPG and fault simulation. Support pattern generation and ATE pattern bring-up. Collaborate with RTL designers, backend teams, and validation engineers to ensure high-quality DFT implementation. Debug and resolve issues in scan/MBIST/ATPG. Prepare DFT reports and documentation for sign-off and customer delivery. Required Skills Strong knowledge of DFT concepts like scan, ATPG, BIST, boundary scan, and test compression. Hands-on experience with tools like Synopsys DFT Compiler, TetraMAX/SpyGlass DFT, or Cadence Modus/Genus. Good understanding of RTL design (Verilog/VHDL) and simulation. Exposure to scripting (TCL, Perl, Python) for automation. Basic knowledge of STA and timing constraints related to DFT paths. Preferred Qualifications Bachelors/Master s degree in Electronics/Electrical/Computer Engineering. Familiarity with ATE platforms (like Teradyne/Advantest) is a plus. Strong problem-solving and analytical skills. Ability to work collaboratively in a team-oriented environment.

We are developing state-of-the-art SoCs from architecture to final product involving automotive centric design methodologies and flows tailored for functional safety. We have a presence across multiple geographies and are currently in search of a Principal level IP/SoC Design Verification Engineer. RESPONSIBILITIES Develop testbenches using System Verilog and UVM for functional and power aware RTL Develop UVM component like agents (active and passive), scoreboards and environment etc., Develop assertions, functional coverage. Develop test plan, UVM based test sequences, layered sequences, virtual sequencers Drive closure of verification metrics to cover verification space. Work with the team to identify and close gaps in functional, power aware and Gate level timing simulation. Develop C testcases for HW-FW simulation and FPGA prototyping Provide regression setup, debug of RTL and gate level netlist Review industry standard spec and augment test plan to improve quality of verification Participate in post silicon bring up, validation and compliance testing and debug Work collaboratively with cross-functional teams like ASIC Architect, ASIC Designers, firmware development team to ensure successful delivery of product MINIMUM QUALIFICATIONS Proven track record of verification, taking several chips from specification to tape out Proven expertise with UVM and/or System Verilog based verification Excellent understanding of ASIC verification methodologies and proven experience of verification Experience working with source control tools, bug management tools and release management tools such as Jenkins, Git, and Jira. Experience with SoC interfaces, embedded processors, networking protocols, security protocols and video formats will be a big plus. Strong written and verbal communication skills and ability to work independently. Bachelors in Electrical Engineering or equivalent and 5+ years of experience

Seeking a highly motivated and innovative digital design engineer with knowledge of ASIC development flow. As a Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL design of subsystems in MCU SoCs, ensuring they meet performance, power, and area specifications Support SoC integration and delivery of subsystem views to Back-end and Design verification team Own Quality Checks and support Functional Verification of the owned blocks Collaborate with cross-functional teams, including system architects and software engineers, to define specifications and ensure seamless integration Preferred Experience Micro Architecture Design, High Level Digital Design, RTL coding. Experience in owning complex IPs or Subsystem designs in ASIC Good understanding and experience in using RTL QC tools such as Spyglass CDC/RDC Qualifications Required and Preferred Qualifications Required: Bachelors degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE a minimum of 8 years of digital design with a proven track record of delivering high-quality designs Expertise in RTL design using Verilog/VHDL and familiarity with analog/mixed-signal design concepts Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Experience with industry-standard EDA tools for synthesis, simulation, and static timing analysis Scripting experience in Shell, Perl, Python and TCL is a plus Preferred: Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Familiarity with synthesis and timing constraints

Seeking a highly motivated and innovative Senior digital design engineer with knowledge of ASIC development flow. As a Senior Staff IC Design Engineer at Renesas India, you will play a crucial role in the design and development of advanced integrated circuits that power our innovative MCU products. You will leverage your expertise in IC design to lead complex projects, mentor junior engineers, and drive the evolution of our design methodologies and processes. Responsibilities Lead the RTL synthesis and constraints generation/validation for MCU SoCs, ensuring they meet performance, power, and area specifications Develop and implement innovative implementation methodologies and tools to enhance productivity and design quality Be the bridge between Backend and Frontend teams to reconcile on hand-off and timing issues Conduct thorough design reviews and provide constructive feedback to peers and junior engineers Collaborate with cross-functional teams to not only resolve collateral issues but also to improve the overall PPA Support Low Power Implementation Support formality checks Preferred Experience Experience in owning RTL synthesis and constraints for complex IPs/SS/SoC Experience in owning or supporting STA at full-chip level Exposure to latest methodologies in constraints generation, promotion/demotion and validation Familiarity with Low Power Implementation flows Qualifications Required and Preferred Qualifications Required: Bachelors degree in Electronics and communication, Electrical Engineering, Computer Engineering, or a similar technical field and with a proven track record of delivering high-quality designs BSEE degree and 12+ years of experience in IC design, or MSEE (or PhD) with 9+ years of experience and with a proven track record of delivering high-quality designs Experience with industry-standard EDA tools for synthesis, constraints validation and static timing analysis Strong understanding of digital design principles and methodologies, timing analysis, and verification methodologies Ability to mentor and guide junior engineers in IC design best practices and methodologies Scripting experience in Shell, Perl, Python and TCL is a plus Good communication skills for interacting between different design groups cross functional groups are required Preferred: Experience with low-power design techniques and methodologies Familiarity with SoC design and integration Some level of understanding of DFT flows and steps Exposure to Automotive SoC designs

About Marvell . Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: Lead End-to-End SoC DV execution and sign-off Define and drive improvements in DV processes for efficient and high-quality execution Collaborate with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure, and gate-level simulations Coordinate with cross-functional teams including Architecture, Chip Lead, Emulation, and Program Management to drive SoC-level DV execution Partner with Silicon bring-up and Firmware teams to support post-silicon validation and bring-up activities Own and debug simulation failures to identify and resolve root causes Architect and implement simulation testbenches using UVM & C. Develop and execute test plans to verify design correctness and performance Collaborate with logic designers for thorough verification coverage and closure What Were Looking For Technical Requirement s: Bachelor s degree in CS/EE with 20+ years of relevant experience, or Master degree in CS/EE with 18+ years of relevant experience Experience in Leading core technical leads Must have experience in SOC/Subsys/IP level verification of ARM-based SOC and experience in ARM boot sequences Must have knowledge of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. Experience with industry standard interfaces such as DDR, HBM, PCIE, Ethernet and USB. Experience coding UVM SOC/Subsys/block level testbenches, BFM, scoreboards, monitors, etc. Proficient in writing and debugging tests in UVM as well as C. Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. Experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Familiarity with TLMs in SystemC. Experience in Version tools like CVS, SVN, GIT etc Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

About Marvell . Your Team, Your Impact Marvell Data Centre Engineering (DCE) - Compute & Storage (CCS) BU has been at the forefront of developing and delivering leading-edge, high-performance data processing silicon platforms. By delivering a stream of technical innovations through a diverse set of fast growing product lines, Marvell technology is powering the next generation data processing and workload acceleration platforms for the Carrier, Cloud/Enterprise and Automotive Compute market segments. The team focusses on the Custom ASIC business, Cloud AI solutions & Enterprise/Career solutions including the CXL product line. What You Can Expect Job Responsibilities: SOC, Sub system & Block verification activities - should have participated in successful completion of SOC/Subsys projects across all phases from SOC/Subsys Specification to Silicon. Responsible for complete SOC/Subsys/Block verification activities like - develop verification architecture and verification plan, develop UVM based testbench, Integrate in-house verification components + complex VIP s ( ARM, Cadence, Synopsys, etc), develop test cases (UVM & assembly), verify and do coverage analysis in RTL and gate level design. Conduct reviews in all the SOC/Subsys verification phases, to achieve desired quality + on-schedule deliverables and drive SOC/Subsys verification process improvement. Mentor junior engineers and technically guide and monitor them on their day to day technical tasks. Work effectively with a global team and be self-motivated to manage deliverables Communicate clearly both verbally and in writing. What Were Looking For Technical Requirement s: Bachelor s degree in CS/EE with 14-18 years of relevant experience, or Master degree in CS/EE with 12-16 years of relevant experience Must Lead a team of 4-6 engineers Experience in SOC/Subsys level/Block verification of ARM-based SOCs; experience in ARM based boot environment preferred. Knowledgeable of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE. Experience with industry standard interfaces such as DDR, eMMC, PCIE, Ethernet and USB. Experience in coding UVM SOC/Subsys level testbenches, BFM, scoreboards, monitors, etc. Proficient in writing and debugging tests in UVM as well as C. Exposure to Cadence, Synopsys, Mentor and/or ARM verification tools. Experience with assertion-based formal verification tools. Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support. Familiarity with TLMs in SystemC. Experience in Version tools like CVS, SVN, GIT etc. Additional Compensation and Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We re dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it s like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. #LI-CP1

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Responsibilities & Skills Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a team first organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you re looking for. Lattice Semiconductor is seeking a Sr. Staff Physical Design Engineer to join the HW design team focused on IP design and full chip integration. This position is an opportunity to be part of a dynamic team with ample opportunity to contribute, learn, innovate and grow. Role specifics: This is a full-time individual contributor position located in Pune, India. The qualified candidate will be implementing and lead RTL to GDSII flow for complex design. The qualified candidate will work and lead one or more aspects of physical design including place & route, CTS, routing, floorplanning, powerplanning, timing and physical signoff The qualified candidate is expected to have experience in physical design signoff checks, including timing closure, EM/RV and physical verification (DRC, LVS). The qualified candidate is expected to drive efficiency and quality of physical design flow and methodology and work together with internal EDA team and external tool vendors The qualified candidate is expected to have scripting knowledge or perl /python etc to improve design efficiency and methodology development. Collaborate with RTL, DFT , verification and full chip teams to ensure robust design implementation. The successful candidate will be open and willing to both (a) teach best-known-methods to an existing FPGA team and (b) learn from the team about the complications of highly programmable FPGA fabrics. This role carries the need to be both a strong educator and a open-minded student. Accountabilities: Serve as a key contributor to FPGA design efforts. Drive physical design closure of key ASIC blocks & full chip and bring best-in-class methodologies to achieve best power, performance, and area. Ensuring design quality through all physical design quality checks and signoff. Develop strong relationships with worldwide teams. Mentor and develop strong partners and colleagues. Occasional travel as needed. Required Skills: BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent. 12+ years of experience in driving physical design activities of ASIC blocks and full chip. Must have experience of multiple tapeouts Experience on working with industry standard physical design tools including Innovus, Genus, Tempus, voltus, calibre, conformal etc. Independent worker with demonstrated problem-solving abilities. Proven ability to work with multiple groups across different sites and time zones Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA , CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com . You can also follow us via Twitter , Facebook , or RSS . At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace. Applications are welcome from all qualified candidates. Lattice Feel the energy.

Are you looking for a unique opportunity to be a part of something great? Want to join a 20,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology, Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values ; we affectionately refer to it as the Aggregate System and it s won us countless awards for diversity and workplace excellence. Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you. Visit our careers page to see what exciting opportunities and company perks await! Job Description: The successful candidate will join the rapidly growing Data Center Solutions (DCS) business unit at Microchip. DCS has a broad portfolio of products widely deployed by the industry s cutting-edge server/storage OEMs and hyperscale datacenters. Customers deploy DCS solutions into applications ranging from Big Data capacity storage to artificial intelligence and machine learning that are helping to shape the next digital age. Our product portfolio includes SAS/PCIe/NVMe/CXL products that connect, manage, and secure the world s information, including Flash Controllers, High Performance Switches, RAID Controllers and Memory Controllers. Join a team where you can expand your skill set and drive key elements of the industry s technology leadership. An opening exists for Technical Staff Design Engineer with an interest in developing the next generation of storage and memory controller SoC products. This will involve taking a design from initial concept through to production. Throughout you will work beside experienced engineers and be exposed to Microchip s Best-In-Class engineering practices. Working side-by-side with some of the brightest minds and most innovative people in the industry, you wont just fill a position, you will be given an opportunity to work on a team where your contributions matter. Microchip fosters continuous learning in a challenging and rewarding environment. If this sounds like the kind of environment youd like to participate in, wed like to hear from you! As a Technical Staff Design Engineer, your job will entail the following: Lead the Design planning of pad rings and package substrates, bump pattern construction. Dynamically define and optimize pad ring connectivity. Work with CFTs (Cross-Functional Team) on the deliverables (DEF, Verilog netlist etc.,) Interface with and support Architect, PD, PE, technology development and foundries teams. Support Verification, Emulation, ASIC lab validation including lab debug and providing logic modifications and workarounds. Additional responsibilities include: Collaborate closely with the Manager to define team structure, skill requirements, and hiring strategy for the local IP development team. Support and participate in end-to-end recruitment activities, including job description creation, candidate screening, interviews, and onboarding. Help identify and engage top technical talent through various sourcing methods in alignment with project and business goals. Assist in establishing a strong, high-performance team culture by supporting team integration, training, and knowledge-sharing initiatives. Work cross-functionally with HR, Talent Acquisition, and Engineering leadership to ensure a streamlined hiring process and effective team ramp-up. Contribute to the development of a scalable team that aligns with long-term IP roadmap and organizational growth. Requirements/Qualifications: B.S or M.S degree in electrical engineering with 12+ years of related experience Prior experience in IC and multicore SoC designs Experience with front-end CAD tools (eg. top-level I/O planning tools) is required. Experience with Verilog/System Verilog is required Familiarity with Verilog models and Liberty files Experience in Fin-Fet technologies is a plus. Scripting experience or knowledge is a plus. Excellent analytical, communication (written and verbal), and documentation skills Excellent problem solving and debugging skills. Travel Time: 0% - 25% To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Brief description about the Job. Job Location : Electronic -City, Phase II,Bangalore. Who you are Port and develop tests for baremetalenvironments on mobile SoC platforms. Design, implement, and debug firmwarefor embedded systems, ensuring robust and scalable solutions. Work closely with hardware teams to define system requirements and validatehardware functionality. Utilize JTAG and other debugging tools for low-level troubleshooting andvalidation. Develop and execute test plans for various SoC subsystems (CPU, GPU,multimedia, TPU, PCIe, USB). Optimize code for performance,efficiency, and memory usage in resource-constrained environments. Automate test execution and reportingusing Python or Bash scripts. Document test procedures, results, and codebase for maintainability andknowledge sharing Who you are Proficiency in C and Assemblyprogramming for embedded systems. Experience with firmware development and debugging on baremetal or RTOSenvironments. Strong understanding of JTAG and otherhardware debugging interfaces. Hands-on experience with at least two SoC subsystems: CPU, GPU, multimedia,TPU, PCIe, or USB. Familiarity with SoC architectures and low-level hardware/software interaction. Experience with test automation using Python or Bash is a plus. Excellentproblem-solving skills and attention to detail. Strong communication and teamwork abilities. Experiencewith Linux, Android, or RTOS environments. Knowledge of device drivers and peripheral interfacing (I2C, SPI, UART). Exposureto performance verification and systemvalidation methodologies. Familiarity with version controlsystems (e.g., Git) Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. . Tessolve is not responsible for any lossesincurred due to such fraudulent activities

System Validation engineers in this group are responsible for driving validation specifications & methodology and deliver on the validation of IPs for the next generation of compute solution. .You will work closely with architecture, design, verification, modelling, performance analysis, SW development, Emulation and FPGA and Board development engineers. Responsibilities: Work with project team to understand, review the system requirements and deliver emulator testbench specifications. Key responsibilities will include owning the development of validation platform in emulation, debug methodology, developing and implementing the test content, finding bugs, and running various validation checks for IPs (CPUs and SystemIPs), Interfaces (like CHI, PCIe etc) in emulation environment. Will guide other members of the team as needed to enable the successful completion of project activities Required Skills and Experience : Bachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering - although other degrees will be considered with relevant work experience You will need experience of Emulation and system level validation for IPs and sub-systems and ASIC products. Emulation build skills and knowledge for a subsystem in at least one emulation system is required. Execution of the design in emulation platform and knowledge of hardware and software interplay is required. You possess the knowledge of Validation test content using C, C++ etc and how they can be performed in an emulation-based system. Expertise on hardware behavioral language (Verilog, System Verilog) Exposure to producing validation specifications and documentation describing sophisticated designs Ability to work under time-scale pressure and meet ambitious targets without compromising on quality Understanding of the fundamentals of computer architecture, system IP, memory subsystem, accelerator. Practical experience of working on Processor based system designs Nice To Have Skills and Experience : Demonstrated understanding of CPU/ GPU subsystem in SoC environment and proven expertise in owning validation requirements & Validation Plan. Hands on Experience in validating multiple sub systems for ASICs/ SoCs in system environment ( across Emulation, FPGA and Development/Eval board), owning all phases of validation ( Test development, Execution and Debug) for owned sub systems. Understanding of SoC security aspects

Candidate should have experience in Software development, tools development role, firmware development role or validation tools development.Candidate shall design and develop algorithms for Post Silicon Validation of next generation IBM server processors, SOCs and ASICs. He/She will be working on processor Bringup Activities and own key debugs during the bring up/power on phase. The candidate will be expected to interface with multiple stakeholders in hardware design teams, lab teams, performance teams and characterization teams. Candidate must work on coverage closure by developing comprehensive test plans and strategies and drive to achieve coverage goals while interacting with stakeholders, verif teams and design teams. He/She must be skilled in utilizing object-oriented programming skills in C/C++ and scripting languages like Python/Perl to write complex test scenarios to automate/optimize. Candidate must possess experience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Proficiency in emulator env/FPGA validation is preferred. She/he must possess excellent communication skills and understand agile processes. The candidate must have an eagerness and curiosity to learn and be willing to code and participate hands on. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise Technical ExpertiseVery proficient in C programming, Strong Scripting skills. Over 10 years experience in hands on Software development using C, C++. Computer Architecture KnowledgeIn-depth knowledge of computer architecture, including processor core design specifications, instruction set architecture, and logic verification. Multi-Processor Cache CoherencyExperience in verifying multi-processor cache coherency and memory subsystems, ensuring seamless operation in complex systems. Operating Systems and ConceptsAtleast 2 years experience with Multithreading, context switching, memory management related development Preferred technical and professional experience IO device drivers, firmware exposure(NIC controller, PCIe device controllers, ASIC FW development experience) ARM architecture RISC V architecture Spike simulator experience, QEMU simulator

" Key Responsibilities Product Innovation Leadership : Drive breakthrough innovations in SME-focused switching features including zero-touch provisioning, cloud-based management integration, and AI-powered network optimization SME Feature Development : Lead development of enterprise-grade features optimized for SME deployments: simplified network segmentation, automated VLAN provisioning, intelligent traffic prioritization, and plug-and-play enterprise security Cost-Performance Optimization : Innovate cost-effective solutions that deliver enterprise functionality at SME price points while maintaining performance Customer-Driven Innovation : Lead research into SME networking pain points and develop innovative software solutions for simplified network management Platform Differentiation : Drive technical differentiation through innovative features like ML-based network anomaly detection, automated capacity planning, and predictive maintenance for SME environments Market-Focused Architecture : Design switching architectures that balance advanced enterprise features with SME deployment simplicity and cost constraints Innovation Partnerships : Collaborate with product management and field teams to identify market opportunities and drive product innovation Competitive Analysis : Lead technical competitive analysis and drive innovation to maintain market leadership in SME managed switching SME Market Product Knowledge SME Network Challenges : Deep understanding of SME networking constraints including limited IT staff, budget sensitivity, and simplified management requirements Market Positioning : Knowledge of SME switching market dynamics, competitive landscape, and differentiation opportunities Enterprise Feature Adaptation : Expertise in adapting complex enterprise features for simplified SME deployment and management TCO Optimization : Understanding of total cost of ownership considerations for SME customers including deployment, management, and maintenance costs Advanced Switching Features for SME Market Intelligent Auto-Configuration : Zero-touch VLAN setup, automated QoS policies, and self-configuring network segmentation Cloud Integration : Seamless integration with cloud management platforms and hybrid cloud networking Security Automation : Automated threat detection, network access control, and security policy enforcement optimized for SME environments Performance Intelligence : ML-driven bandwidth optimization, traffic analytics, and capacity planning for growing SME networks Simplified Network Virtualization : Easy-to-deploy network segmentation and micro-segmentation for SME security requirements Branch Office Connectivity : Advanced SD-WAN integration, site-to-site VPN automation, and centralized branch management Guest Network Management : Sophisticated guest access control with time-based policies, bandwidth limiting, and secure isolation IoT Device Management : Automated IoT device discovery, classification, and policy enforcement for SME environments Voice/Video Optimization : Advanced QoS for unified communications, video conferencing optimization, and real-time application prioritization Network Analytics : Comprehensive network visibility, user behavior analytics, and automated reporting for SME IT teams Innovation & Technical Leadership Emerging Technology Integration : Drive adoption of AI/ML, edge computing, and IoT integration in SME switching solutions Patent Development : Lead development of patentable innovations in SME networking and switching technology Industry Standards : Contribute to industry standards development with focus on SME networking requirements Technical Thought Leadership : Represent company technical innovation at industry conferences and technical forums Expert Technical Requirements Switching Architecture Mastery : Deep expertise in switching ASIC architectures optimized for SME market requirements Advanced Broadcom SDK : Expert-level knowledge of Broadcom SDK optimization for cost-effective, high-performance SME solutions Product-Level Systems : Advanced experience with complete product development from conception to market delivery Innovation Methodologies : Experience with design thinking, rapid prototyping, and customer-driven innovation processes Qualifications Bachelors or Masters degree in Computer Science, Electrical Engineering, or Computer Engineering 8-10 years of embedded switching software development with focus on product delivery 5+ years of experience developing SME networking products or similar market-focused solutions Proven track record of delivering innovative networking products to market with measurable business impact Experience with customer-driven innovation and market-focused product development