Formal Verification Staff Engineer

Synopsys

3 - 8 years

20 - 25 Lacs

bengaluru

Posted:1 day ago| Platform:

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Skills Required

asic semiconductor simulation digital design chip design circuit designing healthcare perl system verilog python

Work Mode

Work from Office

Job Type

Full Time

Job Description

You are a highly skilled and experienced Formal Verification Specialist with a strong background in RTL design and a passion for ensuring the correctness and reliability of digital designs. You have a minimum of 3 years of industry experience, with at least the last 2 years focused on formal techniques for verification.
You possess deep knowledge of architectures of designs and digital logic, synthesis flow, static timing flows, and formal checking. Your hands-on experience with HDLs such as Verilog or System Verilog and understanding of temporal logic assertions make you an ideal candidate for this role. You have worked on complex verification projects and have experience withformal verification tools like Jasper or VC-Formal.
Your skills in Python, Perl, or Shell scripting are a plus.You are a team player with excellent communication skills, capable of mentoring junior engineers and collaborating with geographically diverse cross-functional teams. Your problem-solving abilities and attention to detail enable you to debug RTL designs effectively and identify causes of failure scenarios. You hold a Bachelors or Masters degree in Computer Science or Electrical Engineering from a reputed engineering college.What Youll Be Doing:* Specifying, implementing, and maintaining an integrated end-to-end formal verification flow for the formal verification objective.* Guiding and training team members on effective usage of FV tools.* Reviewing formal setups and proofs with design and verification teams.* Maintaining and extending assertion libraries, including support for both simulation and formal verification.* Identifying key behaviors for verification of DUT and creating a formal verification plan.* Developing verification environments, including environment assumptions, assertions, and cover properties in the context of the verification plan.* Applying various formal verification techniques to prove the correctness of digital designs.* Debugging RTL to identify causes of failure scenarios.The Impact You Will Have:* Enhance the reliability and quality of our digital designs through rigorous formal verification.* Contribute to the development of high-performance silicon chips and software content.* Improve the overall design and verification process by maintaining and extending assertion libraries.* Facilitate knowledge sharing and skill development within the team by providing guidance and training on FV tools.* Ensure the correctness of designs by identifying key behaviors and creating comprehensive verification plans.* Support the success of geographically diverse cross-functional teams through effective collaboration and communication.What Youll Need:* Strong knowledge of architectures of designs and digital logic.* Experience with synthesis flow and static timing flows, formal checking, etc.* Hands-on experience with HDLs such as Verilog / System Verilog.* Understanding of temporal logic assertions.* Experience with at least one formal verification tool (e.g., Jasper, VC-Formal).* Experience with complex verification projects that used formal techniques for closure.* Skills in Python, Perl, or Shell scripting (a plus).Who You Are:* A seasoned professional with a comprehensive understanding of formal verification techniques.* A collaborative team player with excellent communication skills.* A problem solver with strong debugging skills.* A mentor capable of guiding junior engineers and interns.* An individual with a proactive and detail-oriented approach to work.

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