776 Asic Jobs - Page 9

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Brief description about the Job. Job Location : Electronic -City, Phase II,Bangalore. What you ll do Create detailed PCB layoutsusing design software. Work with cross-functional teams todefine and implement design requirements. Optimize circuit designs formanufacturability and performance. Perform design rule checks andvalidation procedures. Generate and maintain documentation forPCB designs. Coordinate with manufacturing teams tofacilitate prototype and production builds. Evaluate and implement improvementsbased on feedback from testing. Who you are . 4 to 7+ years of experience Hands on experience in board designusing AM62x Sitara Processors, microprocessor TI, ARM cortex, or any one highspeed Processor from TI. Experience in interfacing of display,memory and communication modules with the processor. Experience on high speed and low speed interfaces like DDR ,memory, audio, USB,Ethernet, SATA, MIPI,HDMI, I2C SPI,UART, etc. Hands on experience in HardwareDevelopment Life Cycle like design, bringup, basic programming, testing andvalidation of boards, functional testing, trouble shooting, debugging andFailure analysis. Collaborating with cross function team in managing PCB layout, SI-PIsimulations, Software development, mechanical, thermal and other stakeholdersto ensure a cohesive and efficient system design. Should have knowledge on basics on programming and basic Linux commands Should be able to design the schematics in Altium and orcad. Hand on experience in using instrumentslike high speed Oscilloscopes, DMM, electronic loads etc. Good Communicationand interpersonal skill Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. If you receive any such communication, we stronglyadvise you to refrain from making any payments and to promptly report theincident to us at hr@tessolve.com. Tessolve is not responsible for any lossesincurred due to such fraudulent activities

JOB DESCRIPTION Title/Position:BSP Developer Location:Bangalore/Kochi India Education:Bachelor s degree Key Responsibilities: Work closely withBusiness Unit head in defining strategy for the BU Responsible accountable for engineering execution and deliveries for customer projectsacross globe Work proactivelywith different stake holders in the organization for successful execution andproject reporting Work proactivelywith HR team for hiring talented and capable engineers to fulfil the businessneeds Mentor the teams growth create a conducive environment in the BU for their success Support salesteam in customer facing activities, proposal preparation to win business Key Skills: Bachelors in Electronics Engineering is aminimum requirement Masters in Electronics or Computer ScienceEngineering is an added advantage 4+ years of Industry experience in theindustry Automotivedomine experience is added advantage. Mustkey skills-Linux device drivers, BSP Must. Languages:Embedded C with Data Structures OperatingSystem: Linux / Android / RTOS Experiencein BSP development activities for Linux Android based embedded devices Experiencein embedded development, Linux device driver development, integration, boardbring-up activities such as programming, debugging, troubleshootingand functionality testing WorkingKnowledge in I2C, SPI, UART, USB, SDIO, Audio and Video, Ethernet, PCIeinterfaces WorkingKnowledge in Yocto, kernel, board bring up, porting Aboutus: Tessolve Semiconductors, a venture of Hero Electronix,is a Design and Test Engineering Service Company providing End to End Solutionsfrom Product Engineering, Software, Hardware, Wireless, Automotive and EmbeddedSolutions. Tessolveoffers a unique combination of pre-silicon and post-silicon expertise toprovide an efficient turnkey solution for silicon bring-up, spec to theproduct. With 3000+ employees worldwide, Tessolveprovides a one-stop-shop solution with full-fledged hardware and softwarecapabilities, including its advanced silicon and system testing labs. Tessolveoffers a Turnkey ASIC Solution, from design to packaged parts. We have a globalpresence with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers ahighly competitive compensation and benefits along with an electric workenvironment to scale one s intellect, skills and growth

JOB DESCRIPTION Title/Position: HardwareEngineers- Lead Location: Bangalore Education: Bachelor s degree Key Responsibilities: Work closely withBusiness Unit head in defining strategy for the BU Responsible accountable for engineering execution and deliveries for customer projectsacross globe Work proactivelywith different stake holders in the organization for successful execution andproject reporting Work proactivelywith HR team for hiring talented and capable engineers to fulfil the businessneeds Mentor the teams growth create a conducive environment in the BU for their success Support salesteam in customer facing activities, proposal preparation to win business Key Skills: Bachelors in Electronics Engineering is aminimum requirement Masters in Electronics or Computer ScienceEngineering is an added advantage 6+years of experience in hardwaredesign and Development Experience in Digital design relatedto Microprocessors/ Microcontrollers, DSP, FPGAs, scillators, Memories, ADC,DACs, Op-Amps High/Low side drivers, clock circuits, etc Experience in designing and testinginterface for all type of peripherals e.g. I2C, SPI, RS- 232/422, RS-485, CAN,Ethernet, etc.). Experience in designing and testing ofhigh-speed interfaces like MIPI, HDMI, DVI, PCIe, USB, LVDS, Ethernet, etc Experience in design and testing of Memoryinterfaces like DDR3, DDR4 Experience in Circuit analysis likepower budget, DC drop, tolerance, Derating, thermal etc Experience working in hardwaredevelopment, bring up, debug and validation Experience working on high-speedboard design Exposure to Power integrity, Signal Integrity,Thermal Analysis Exposure on designing power deliverysolutions for various chipsets. Experience in Thermal design andknowledge of EMI/EMC filter design and ESD. Able to develop test procedures andtest the electronics circuit Experience using high end scopes,logic analyzer, Signal Generator and appropriate tools required for board debug Experience with tools for hardware versioncontrol and bug tracking Strong analytical and problem-solving skillswith ability to work independently Should be able to co-ordinate with variouscross-functional teams like, PCB Design, Simulation, SCM, Firmware development,Application Development teams Strong verbal communication andpresentation skills Aboutus: Tessolve Semiconductors, a venture of Hero Electronix,is a Design and Test Engineering Service Company providing End to End Solutionsfrom Product Engineering, Software, Hardware, Wireless, Automotive and EmbeddedSolutions. Tessolveoffers a unique combination of pre-silicon and post-silicon expertise toprovide an efficient turnkey solution for silicon bring-up, spec to theproduct. With 3500+ employees worldwide, Tessolveprovides a one-stop-shop solution with full-fledged hardware and softwarecapabilities, including its advanced silicon and system testing labs. Tessolveoffers a Turnkey ASIC Solution, from design to packaged parts. We have a globalpresence with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers ahighly competitive compensation and benefits along with an electric workenvironment to scale one s intellect, skills and growth

JOB DESCRIPTION Title/Position:BSP Developer Location:Bangalore Education:Bachelor s degree Key Responsibilities: Work closely withBusiness Unit head in defining strategy for the BU Responsible accountable for engineering execution and deliveries for customer projectsacross globe Work proactivelywith different stake holders in the organization for successful execution andproject reporting Work proactivelywith HR team for hiring talented and capable engineers to fulfil the businessneeds Mentor the teams growth create a conducive environment in the BU for their success Support salesteam in customer facing activities, proposal preparation to win business Key Skills: Bachelors in Electronics Engineering is aminimum requirement Masters in Electronics or Computer ScienceEngineering is an added advantage 3+ years of Industry experience in theindustry Automotive domine experience is addedadvantage . Must key skills-Linux device drivers, BSP Must. Languages: Embedded C with DataStructures Operating System: Linux / Android /RTOS Experience in BSP developmentactivities for Linux Android based embedded devices Experience in embedded development,Linux device driver development, integration, board bring-upactivities such as programming, debugging, troubleshooting andfunctionality testing Working Knowledge in I2C, SPI, UART,USB, SDIO, Audio and Video, Ethernet, PCIe interfaces Working Knowledge in Yocto, kernel,board bring up, porting Aboutus: Tessolve Semiconductors, a venture of Hero Electronix,is a Design and Test Engineering Service Company providing End to End Solutionsfrom Product Engineering, Software, Hardware, Wireless, Automotive and EmbeddedSolutions. Tessolveoffers a unique combination of pre-silicon and post-silicon expertise toprovide an efficient turnkey solution for silicon bring-up, spec to theproduct. With 2500+ employees worldwide, Tessolveprovides a one-stop-shop solution with full-fledged hardware and softwarecapabilities, including its advanced silicon and system testing labs. Tessolveoffers a Turnkey ASIC Solution, from design to packaged parts. We have a globalpresence with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers ahighly competitive compensation and benefits along with an electric workenvironment to scale one s intellect, skills and growth

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Brief description about the Job. Job Location : Electronic -City, Phase II, Bangalore. What you ll do Collaborate with design, PHY andarchitecture teams to understand the DRAM requirements Develop and maintain firmware for DRAMbring up and training in both pre and post Si Bring up DRAM interface andanalyze margins. Debug Si issues in collaboration with HWand SW teams to identify root cause. Who you are 5 to 10 years of Experience Experience in Si validation and firmware development Experience in Si bring up and pre-Si orpost Si validation Excellent C programming skills Experience in Si debug using T32, JTAG and awareness of debug methodologies Experience in DRAM firmware creation Knowledge of SoC architecture and LPDDRinterface Experience on firmware development forbare metal platform Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. If you receive any such communication, we stronglyadvise you to refrain from making any payments and to promptly report theincident to us at hr@tessolve.com. Tessolve is not responsible for any lossesincurred due to such fraudulent activities

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theRD center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Brief description about the Job. Job Location : Electronic -City, Phase II,Bangalore. What you ll do Development Testing of IO controller hub diagnostic test cases forAMD SoCs Debugging of the test case failures and reporting them to the designteam Involvement in test planning of diagnostics Collaboration with various related cross-teams Who you are Expertise in C++ programming Post Silicon diagnostics development validation Good understanding of data/address busarchitecture, caches, memory management. Understanding of PC Hardware, SoC, Chipsets,CPU, GPU, BIOS, firmware etc. Knowledge of x86 / computer architecture Understanding of OS internals Solid knowledge of software development lifecycle Strong analytical and problem-solving skills Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. If you receive any such communication, we stronglyadvise you to refrain from making any payments and to promptly report theincident to us at hr@tessolve.com. Tessolve is not responsible for any lossesincurred due to such fraudulent activities

Position: DFT-Design Engineer 2 Experience: 2+ years relevant experience. Location - India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of delivering of complex IPs using the latest advance Design for Test skills and Tools . Technical Skillset Required: Good knowledge in DFT Skills Sound knowledge in DFT Architecture and hands on in Scan , ATPG , Simulation GLS . Prior experience in Synsopsys or Cadence or Mentor tools Like Tetramax, Modus ,Tessent and DC tools Hands on in MBIST insertion and simulation Knowledge on JTAG is an added advantage . Good Simulation debugging skills Technical Documentation: uArchitecture Specification, SoC Integration Specification Good exposure to Scripting skills like Perl or Python or Shell or TCL . About us: Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one s intellect, skills and growth.

About Us: Tessolve offers a unique combination ofpre-silicon and post-silicon expertise to provide an efficient turnkey solutionfor silicon bring-up, and spec to the product. With 3200+ employees worldwide,Tessolve provides a one-stop-shop solution with full-fledged hardware andsoftware capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution,from design to packaged parts. Tessolve s design services include solutions onadvanced process nodes with a healthy eco-system relationship with EDA, IP, andfoundries. Our front-end design strengths integrated with the knowledge fromthe backend flow, allows Tessolve to catch design flaws ahead in the cycle,thus reducing expensive re-design costs, and risks. We actively invest in theR&D center of excellence initiatives such as 5G, mmWave, Silicon photonics,HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-endproduct design services in the embedded domain from concept to manufacturingunder an ODM model with application expertise in Avionics, Automotive,Industrial and Medical segments. Tessolve s Embedded Engineering servicesenable customers a faster time-to-market through deep domain expertise,innovative ideas, diverse embedded hardware & software services, andbuilt-in infrastructure with world-class lab facilities. Tessolve s clientele includes Tier 1clients across multiple market segments, 9 of the top 10 semiconductorcompanies, start-ups, and government entities. We have a global presence over12 countries with office locations in the United States, India, Singapore,Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, andTest Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit www.tessolve.com . Job Overview Brief description about the Job. Job Location : Electronic -City, Phase II,Bangalore. What you ll do Collaborate with design, and architectureteams to understand requirement and create validation plan to uncover Siissues. Develop and maintain firmware for SoCfor functional bring up and validation. Debug Silicon issues in collaborationwith HW and teams to identify root cause Who you are 5 to 10 years of Experience Experience in Si bring up and pre-Si orpost Si validation Excellent C programming skills Experience in Si debug using T32, JTAGand awareness of debug methodologies Experience in bringing up power on Post Si Knowledge of SoC architecture, ARMarchitecture, SD/SPI protocol and boot flows Experience on firmware development for bare metal platform Good Communication and interpersonal skills Tessolve Semiconductor Private Limited, aswell as its affiliates and subsidiaries ( Tessolve ) does not requirejob applicants to make any payments at any stage of the hiring process. Anyrequest for payment in exchange for a job opportunity at Tessolve is fraudulentand should be ignored. If you receive any such communication, we stronglyadvise you to refrain from making any payments and to promptly report theincident to us at hr@tessolve.com. Tessolve is not responsible for any lossesincurred due to such fraudulent activities

Title/Position: Analog LayoutEngineer Experience: 4-8 years Location: Bangalore / Hubli About us: Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 3500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one s intellect, skills and growth. Qualification : BE/BSC/Diploma Technical Skillset required: 4-8 years experience in Mixed Signal and Analog Layout. Conversant with Cadence Tools and Mentor Tools(Calibre) Experience with higher nodes like 180/150/130nm and below preferable. Experience on Dongbu PDK. Experience with layout of Analog blocks (reference, amplifier, data converters) is critical Experience with BCD process. Tessolve offers a highlycompetitive compensation and benefits along with an electric work environmentto scale one s intellect, skills, creates and environment for people who thrivefor success and grow with the organizations growth. Tessolve has somethingunique to offer to everyone depending on their interest levels. Disclaimer: At Tessolve, we are committedto fostering a workplace that embraces and celebrates diversity in all itsforms. We believe that diverse teams drive innovation, creativity, and success.We are dedicated to creating an inclusive environment where all employees,regardless of their race, color, religion, gender, gender identity orexpression, sexual orientation, national origin, genetics, disability, age, orveteran status, feel valued and respected. We believe in fair and equitabletreatment for all employees and aim to eliminate any biases or barriers thatmay hinder personal or professional growth.

Develop knowledge on protocols and products based on industry leading protocols such as I3C, DDR, SD, AXI, AHB Gain knowledge on ASIC flow and learn various tools used in the ASIC flow Work with a team of highly experienced applications engineers to provide comprehensive consulting on our IP products Participate in providing feedback on product documentation and collateral Develop presentation and team working skills What you'll Need: Currently pursuing a masters degree in Electrical/Electronic/Computer Engineering with exposure to VLSI, Verilog, coding skills, FPGAs A self-motivated and excellent communicator will be ideal candidate for this role

Linux Device Driver Development Engineer - MosChip Technologies Linux Device Driver Development Engineer Job Description Requirements Very good C programming and Linux skills. Good to have experience in embedded/automotive software and/or driver development on ARM SoCs on Linux/Android etc Good to have multi-threaded programming experience. Good at Linux System programming. Good understanding of Linux OS concepts and Linux Kernel internals. Awareness of RTOS operating system fundamentals / processor architecture /embedded system and microprocessor concepts. Familiarity with parallel-processing concepts such as threads, signals, priorities, semaphores, mutexes, race-conditions, deadlocks, etc. Experience with scripting languages (Python, Shell scripts) Implement Tools and Test applications to enable and streamline testing process. Contribute in pre-silicon and post-silicon bring-up of future chipsets. Good system debugging skills and root cause analysis. Excellent Linux kernel debugging skills with ability to Find the exact root cause. Experience in using debugging tools like Lauterbach, Trace tools and the ability to use Oscilloscope and Protocol Analysers Good understating of working debug tools like JTAG/TRACE. Strong analytical and problem-solving skills Should be a good team-player and easy to work with various stake holders. Good to have experience dev ops tools like Git/Perforce/Gerrit/Code Collab etc.. Candidate should be familiar in understanding the peripheral hardware, Device Data sheets, Schematics, Specification and Reference manual. Good understanding of communication protocols (SPI, I2C, UART) Knowledge on LDO/SMPS, Crystals/Clocks, Battery charging and Fuel gauge Driver s design and development on multiprocessor and multithreaded ASIC platforms. Preferably good understanding about ARM32/64 chipset architecture. good to have experience working in Linux USB/HSIC/PCIe Core drivers. Working knowledge of any of the peripheral Linux driver s areas such as: DMA, PMIC, USB, PCIe, HSIC Job Specifications Years of Experience: Apply for this position Allowed Type(s): .pdf, .doc, .docx By using this form you agree with our Privacy, and T&C. * Lost your password? Please enter your username or email address. You will receive a link to create a new password via email. Email Reset Link Scroll to top Welcome to MosChip DigitalSky Download the Latest MosChip DigitalSky Brochure PRESS RELEASE: Launching MosChip DigitalSky for Building Connected Intelligent Enterprises

Siemens EDA is a global technology leader in Electronic Design Automation software. Our software tools enable companies around the world to develop highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics to deliver better products in the increasingly complex world of chip, board, and system design. This role is based in Bengaluru. But you’ll also get to visit other locations in India and globe, so you’ll need to go where this job takes you. In return, you’ll get the chance to work with teams impacting entire cities, countries, and the shape of things to come We make real what matters! This is your role Deploy Siemens EDA ProFPGA prototyping software and hardware solutions at customers and guide the customers to successful design bring-up Work closely with R&D to solve problems, review product specs, and find good general solutions that improve the overall product Train AE’s and customers on the solutionWin pre-sales engagements in cooperation with the technical sales teams Successfully deploy our solutions at early customer sites. This means educating the customer on best practices and tool requirements. It also means working with R&D to make the tool improvements necessary for the customer’s success. Ensure existing customers maximize the value they receive from the solution by developing and enhancing methodology that exploits the solution’s capabilities Ensure customers are kept up-to-date with the latest enhancements Provide customer requirements to R&D and marketing Work with QA and Docs to help them create tests and documentation that will improve our solutions Create examples and tutorials that are shipped with our products. Develop and/or refine methodology employed in creating and using prototypes and maximizing the value of our prototyping solution We don’t need superheroes, just super minds! A good understanding of FPGA based hardware prototyping platforms Working knowledge of multi FPGA prototyping flows(Synthesis, partitioning, PnR, runtime and debug) Practical insights into the application and usage of FPGA prototyping systems Knowledge of design mapping, testbench mapping and transactor development Expertise of hardware/software debug solutions related to FPGA prototyping Knowledge of test bench acceleration, ICE and co-model solutions Highly proficient in HDLs (Verilog/SV) for RTL design and HVLs (SV/UVM) for verification Solid background in Functional Verification, RTL synthesis and PnR flows Conversant with SoC design and architecture concepts Good communication and inter-personal skills. A collection of over 377,000 minds building the future, one day at a time in over 200 countries. All employment decisions at Siemens are based on qualifications, merit and business need. Bring your curiosity and creativity and help us shape tomorrow! Siemens Software. Where today meets tomorrow #LI-EDA #LI-Hybrid

The position will involve working with a very experienced physical design team and is responsible for delivering the physical design of blocks/tiles to meet challenging goals for frequency, power and other design requirements for AMD next generation chips in a fast-paced environment on cutting edge technology. THE PERSON: Engineer with good attitude who seeks new challenges and has good analytical and communication skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR, Formal Equivalence Handling different PNR tools - Synopsys Fusion Compiler, ICC2, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk, Cadence Genus, Innovus Provide technical support to other teams PREFERRED EXPERIENCE: 5-7 years of professional experience in physical design, preferably ASIC designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Strong analytical/problem solving skills and pronounced attention to details ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering

Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. For more information about Astera Labs, see www.AsteraLabs.com . Key Responsibilities Lead and scale high-performing Firmware QA teams in India. Own the full software development lifecycle, from architecture and design to testing and deployment. Develop and implement software development and QA best practices, including test automation, process monitoring, and quality metrics. Collaborate cross-functionally with hardware, product, and customer-facing teams to define and deliver robust software solutions. Communicate regularly with global customers including Hyperscalers and Tier 1 OEMs to provide updates, support audits, and resolve escalations. Help build large-scale test farms and automation frameworks. Mentor, coach, and grow engineering talent through effective performance management and career development. Drive continuous improvement in team efficiency, quality, and delivery. Basic Qualifications : Bachelor s degree in Electrical Engineering or Computer Science (Master s or PhD preferred). 10+ years of experience in firmware software QA. Proven ability to build and manage complete software development teams in India. Expertise in Agile software development methodologies. Deep understanding of software test methodologies, automation, and management tools. Excellent communication and interpersonal skills, especially in customer-facing roles. Strong planning, prioritization, and project management skills in fast-paced environments. Entrepreneurial, proactive mindset with a passion for innovation and customer success. Required Experience : Proficiency and demonstrated experience with ASIC based hardware systems and SQA mechanisms. Knowledge of PCIE is required. Building and scaling technical teams with a focus on collaboration and innovation. Proficient in C and Python programming. Expert-level user of Git, Jira, and Confluence. Experience defining and tracking software KPIs and quality metrics. Development and implementation of firmware design and test plans. Knowledge of hardware/software architecture and its impact on system performance. Preferred Experience : Experience with Security Development Lifecycle and FIPS certification. Familiarity with cryptographic protocols and implementation. Knowledge of memory (DDR4/DDR5/HB) technologies. Deployment of AI based SQA and FW development

Development/configuration of new API on Apigee API management platform Strong in reviewing the specification files/swagger files. Have an active enthusiasm in automation areas Policy , credentials and any other administration of existing API. Troubleshoot priority incidents, facilitate blameless post-mortems and ensure permanent closure of incidents. Engage with development team throughout the life cycle in ensuring minimal refactoring or changes. Participate in the 24x7 support coverage as needed. Have an enthusiastic, go-for-it attitude. When you see something broken, you cant help but fix it. Have an urge to collaborate and communicate asynchronously. Have an urge for delivering quickly and iterating fast. Strong in basics B asic Qualifications: Bachelor degree, preferably in Computer Science, Software Engineering, or any other Engineering field. 3+ years with Apigee API management platform with AWS expertise (will be plus) . Technical Experience: Knowledge on Key AWS services: EC2, S3, VPC, Route 53, RDS, CloudFormation, EC2, DynamoDB (NoSQL), Lambda, logging/CloudWatch, IAM, Certificate Manager, ELB, EBS, ECS, CloudFront/WAF, SQS, SNS, SES. Experience with identifying API from business processes design and implementing API using latest and emerging technology. Working knowledge of API security certification, authentication, authorization, IP security setup, and end point configuration. Hands on experience with building service policies using various Policy Assertions that implement XML/JSON transformation, routing, encryption/decryption, dig. signatures, auditing, PKI, threat prevention, ICAP integration, logical assertions, etc This includes hands on experience with Access Control, TLS, XML Security, Message Validation/Transformation, Routing, Policy Logic and Threat Protection Policy assertion categories. Hands on any modern API Gateways, preferably Apigee . Knowledge of REST best practices preferred. Understanding of Git, Bitbucket, Jira, Jenkins, Sonar, Splunk, Maven, AIM and/ or Continuous Delivery tools. Knowledge of at least one modern programming language such as: Java, C, C++, Perl, or Python. Responsibilities: Meeting SLO, SLA, SLI defined in the Operations model. Setting task prioritization and troubleshoot to closure of incidents. Participate on-call /on-rotation. Improve Service observability. Proactively testing the flexibility and resilience of the system.

Lead STA and PNR activities for complex subsystems, ensuring robust timing closure and physical implementation with a focus on power, performance, and area optimization. Develop and refine methodologies for STA and PNR tailored to the unique challenges of large, multi-interface, or mixed-signal subsystems. Drive automation and validation of timing and physical design data across subsystem boundaries. Mentor and guide junior engineers, fostering technical growth and knowledge sharing within subsystem teams. Collaborate cross-functionally to resolve design, timing, and physical implementation challenges specific to complex subsystem integration. Exhibit excellent communication skills to present technical solutions and lead discussions with internal teams and customers, especially regarding subsystem-level trade-offs and integration Qualifications 10+ years of experience in Static Timing Analysis (STA) and Place and Route (PNR) for complex subsystems within ASIC/SoC design, including advanced technology nodes (7nm, or below). Demonstrated expertise in STA tools (e. g. , Synopsys PrimeTime, Cadence Tempus) and PNR tools (e. g. , Synopsys ICC2, Cadence Innovus) applied to large, multi-block or hierarchical subsystems. Proven track record in timing closure, floorplanning, placement, clock tree synthesis, routing, and physical verification for high-complexity subsystems. Proficient in scripting languages (Tcl, Perl, Python) for automating STA and PNR flows across multiple subsystem blocks. Deep understanding of SoC design flows, with experience collaborating across frontend, physical design, and verification teams to integrate complex subsystems. Experience with IP collateral generation and quality assurance for timing and physical design at the subsystem level preferred. Background high-speed interfaces, or mixed-signal SoC subsystems

Post-Silicon ATE Lead to lead and manage post-silicon validation and production testing efforts using ATE platforms. This role requires strong technical expertise in silicon characterization, test development, and working closely with cross-functional teams including design, DFT, packaging, and product engineering. Own and lead post-silicon validation and ATE characterization for silicon devices (SoC/MCU/ASIC). Develop and debug ATE test programs for characterization, qualification, and production ramp-up. Collaborate with design and DFT teams to define test coverage and validation strategy. Analyze silicon test data to identify functional/parametric failures, yield issues, or corner case behaviours. Lead silicon debug and root cause analysis of test failures. Define and drive test cost optimization strategies (e. g. , multisite, parallel test, retest strategy). Work with OSATs and vendors for probe card, loadboard, and socket development. Define test limits, corner conditions, and environmental conditions (HTOL, AC/DC, ESD, etc. ). Support qualification testing (e. g. , HTOL, HAST, Temp Cycle) and drive correlation Qualifications B. E. / B. Tech or M. E. / M. Tech in Electronics, Electrical, or related field. 1 2+ years of experience in post-silicon validation and ATE development. Strong hands-on experience with ATE platforms (e. g. , Teradyne UltraFlex, Advantest 93K, NI STS). Solid understanding of mixed-signal, digital, and analog test methodologies. Experience with scripting (Python, Perl, and C) for automation and data analysis. Familiarity with lab equipment (oscilloscopes, source meters, BERTs, etc. ) for correlation and debug. Excellent problem-solving skills and ability to work across global teams.

A highly-skilled ASIC Digital Verification Engineer with a passion for developing functional verification solutions for RTL based IP Cores. You are experienced in handling complex protocols and thrive in a collaborative international environment. With over 15 years of experience, you possess a deep understanding of verification methodologies and are proficient in SystemVerilog (SV) and Universal Verification Methodology (UVM). You are adept at making architectural decisions, implementing test benches, and driving innovation in verification solutions. You are a proactive team player with excellent communication and problem-solvin g skills, ready to contribute to cutting-edge projects in AI/machine learning, automotive, and server farm applications. What You ll Be Doing: Making architecture decisions on test bench design. Writing verification plans and s pecifications. Implementing test bench infrastructure and writing test cases. Utilizing a coverage-drive n methodology. Providing technical leadership and guidance to the team. Collaborating with architects, designers, and other verification team members across multiple sites worldwide. The Impact You Will Have: Ensuring the reliability and performance of IP Cores used in critical applications. Driving innovation in verification methodologies and solutions. Contributing to the development of industry-leadi ng technologies in AI, automotive, and server farms. Enhancing productivity and throughput through effective verification strategies. Maintaining high standards of quality and functionality in IP verification. Mentoring and guiding junior engineers, fostering a culture of continuous learning and improvement. What You ll Need: Extensive knowledge of protocols such as DDR, PCIe, AMBA (AXI, CHI), SD/eMMC, Ethernet, USB, MIPI. Hands-on experience in creating test environments from functional specifications using UVM/VMM/OVM. Proficiency in SystemVerilog (SV), UVM, and object-oriente d coding and verification. Ability to provide innovative verification solutions for enhanced productivity and performance. Experience with scripting languages like C/C++, TCL, Perl, Python is an added advantage. Experience of working with Functional safety, ISO26262 , FMEDA is an added advantage Who You Are: You are an independent thinker with a precise approach to work, capable of driving innovation and leading technical projects. Your communication skills are excellent, and you thrive in a team-oriented environment. You are committed to continuous learning and possess a strong problem-solvin g aptitude. Experience with functional safety standards like ISO26262 and FMEDA is a plus. The Team You ll Be A Part Of: You will be part of the Solutions Group at our Bangalore Design Center, India. This team is dedicated to developing functional verification solutions for IP used in diverse applications, including server farms, AI/machine learning, and automotive sectors. You will work closely with architects, designers, and other verification team members across multiple international sites, contributing to innovative and challenging projects. Benefits Health & Wellness Comprehensive medical and healthcare plans that work for you and your family. Time Away In addition to company holidays, we have ETO and FTO Programs. Family Support Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more. ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back. Retirement Plans Save for your future with our retirement plans that vary by region and country. Compensation Competitive salaries

The ideal candidate should have a minimum of 4+ years of relevant experience in the following areas: - Proficiency in C and C++ programming languages. - Knowledge of 3GPP, LTE, and 5G NR Telecom standards. - Familiarity with RAN, BaseBand, and L1/L2/L3 protocol layers. - Experience working with Linux and Networking technologies. Required Skill Sets: - Strong programming skills in C, C++, C-Linux, and Bash. - Understanding of Telecom-IP Com and Telecommunication concepts. - Knowledge of 3GPP2, 3GPP, GSM, 2G, 3G, LTE, 5G, Networking, Wireless, and Baseband technologies. - Experience in DSP, RTOS, VxWorks, ARM, x86, ASIC, PHY, Embedded systems, Time series, and Digital signal processing. - Familiarity with CPRI, eCPRI, NETCONF, YANG, gNb, eNb, BTS, and RBS. The successful candidate should be able to demonstrate expertise in the mentioned areas and contribute effectively to the team's projects and goals.,

As an RTL Design Engineer at Google, you will utilize your expertise in designing RTL digital logic using System Verilog for FPGA/Application-Specific Integrated Circuit (ASIC). Your role will involve scripting in languages such as Perl or Python, as well as focusing on area, power, and performance optimization. Ideally, you hold a Master's degree or PhD in Electrical Engineering, Computer Science, or possess equivalent practical experience. Experience in designing and developing security blocks or crypto blocks will be beneficial for this position. Join a diverse team at Google that is dedicated to pushing boundaries and creating custom silicon solutions for the future of direct-to-consumer products. Your contributions will drive innovation behind globally loved products, shaping the next generation of hardware experiences with a focus on performance, efficiency, and integration. In this role, you will be responsible for Register-Transfer Level (RTL) design development of security IP and subsystems. This includes tasks such as Micro architecture, RTL coding, UPF definition, constraints, IP release flows, Power Performance Area (PPA) optimizations, test planning collaboration, coverage reviews, and closure to ensure high-quality and optimized security designs. At Google, our mission is to organize the world's information and make it universally accessible and useful. Our team combines Google AI, Software, and Hardware to create radically helpful experiences, researching, designing, and developing new technologies and hardware to enhance computing speed, seamlessness, and power for the betterment of people's lives. Your responsibilities will include participating in test planning and coverage analysis, developing RTL implementations meeting power, performance, and area goals, engaging in synthesis, timing/power closure, FPGA and silicon bring-up, Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, as well as conducting Lint/CDC/FV/UPF checks. Additionally, you will create tools and scripts for task automation and progress tracking.,

Your impact Looking forward to getting an exciting start to your career? You will bring your outstanding talents to the group that works on Cisco's Switching technology, which large enterprises now consider to be the Networking Equipment of choice for critically important networks. In your role as a Software Engineer, you will develop and integrate products that are deployed by some of the leading Enterprises in the world. You will work with a BU-wide vibrant technical community, learning from experts and translating this learning into exciting opportunities for personal growth. You will work on networking equipment that forms a crucial backbone of many offices, hospitals, educational and financial institutions. You will learn about ground breaking technologies and platforms while developing software for these equipments. Experience the exhilaration of taking a product through development and integration. Minimum Qualifications 4 - 8 years proven experience in internetworking technologies and applications. Good experience in developing software in C, under multi-threaded environment with Excellent problem-solving skills SDK Development: Design, implement, and maintain SDKs that enable seamless integration between software applications and underlying hardware or network layers Familiarity with DPDK (Data Plane Development Kit), P4 programming language, or similar frameworks for high-performance packet processing. Experience with hardware platforms such as ASICs, FPGAs, or NPUs Hands on Data Structures, Operating Systems and Data Networking fundamentals Experience in development of Layer 2 (Ethernet) and/or Layer 3 Networking protocols including Routing, IPV4/6 (unicast/multicast) Is preferable Expertise in working with Linux OS Experience in any Cisco OS XR, XE or NXOS would be a plus Good hands on implementation experience with one or more of the following: RTOS Internals, High Availability, IPC, Memory management, Distributed communications Infrastructure, Serviceability, Linux, Containers, Virtualization Preferred Qualifications Bachelors degree in computer science or related field (MS preferred). 4 - 8 years proven experience in internetworking technologies and applications.

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco's silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact Responsible for implementing the Hardware Design-for-Test (DFT) features that support ATE, in-system test, debug and diagnostics needs of the designs. Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL. Work closely with the design/design-verification and PD teams to enable the integration and validation of the Test logic in all phases of the implementation and post silicon validation flows. Your team will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies. The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship. Minimum Qualifications: Bachelor's or a Masters Degree in Electrical or Computer Engineering required with at least 7+ years of experience. Knowledge of the latest innovative trends in DFT, test and silicon engineering. Background with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Background with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Verification skills include, System Verilog Logic Equivalency checking and validating the Test-timing of the design Knowledge of the latest innovative trends in DFT, test and silicon engineering. Experience with Jtag protocols, Scan and BIST architectures, including memory BIST and boundary scan. Prior experience with ATPG and EDA tools like TestMax, Tetramax, Tessent tool sets, PrimeTime Prior experience working with Gate level simulation, debugging with VCS and other simulators. Prior experience with Post-silicon validation and debug experience; Ability to work with ATE patterns, P1687 Prior experience with Scripting skills: Tcl, Python/Perl. Preferred Qualifications: Verilog design experience developing custom DFT logic & IP integration; familiarity with functional verification DFT CAD development Test Architecture, Methodology and Infrastructure Background in Test Static Timing Analysis Past experience with Post silicon validation using DFT patterns.

MTS SOFTWARE DEVELOPMENT ENG INEER THE ROLE: AMD is looking for a specialized software engineer who is passionate about improving the performance of key applications and benchmarks . You will be a member of a core team of incredibly talented industry specialists and will work with the very latest hardware and software technology. THE PERSON: The ideal candidate should be passionate about software engineering and possess leadership skills to drive sophisticated issues to resolution. Able to communicate effectively and work optimally with different teams across AMD. KEY RESPONSIBILITIES: Work with AMD s architecture specialists to improve future products Work on datapath components of programmable ASIC based products ( DPU, AI-NICs) Design, Develop and Own critical components of next generation product software stack Stay informed of software and hardware trends and innovations, especially pertaining to algorithms and architecture Design and develop new groundbreaking AMD technologies Participating in new ASIC and hardware bring ups Debugging/fix existing issues and r esearch alternative, more efficient ways to accomplish the same work Debug at system level with keen understanding of concepts and penchant to solve technical challenges. Be prepared to develop, own tools, unit tests (including frameworks) to automate the features they work on PREFERRED EXPERIENCE: Ability to write high quality code with a keen attention to detail Strong proficiency in C and C++ programming languages with experience in developing high-performance software. Working knowledge of python,go is a plus. Solid understanding of computer architecture, data structures, and algorithms. Experience with system-level debugging tools and techniques (e.g., gdb, memory analyzers, logic analyzers). Knowledge of parallel programming and multithreading concepts is a plus. Familiarity with hardware design (FPGA, ASIC) and related tools is advantageous. Proven problem-solving skills and the ability to work effectively in a collaborative team environment. Attention to detail and a commitment to delivering high-quality, reliable solutions. ACADEMIC CREDENTIALS: Bachelor s or Masters degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent #LI-PM2

Job Description : We are looking for a VLSI MBIST Engineer with strong expertise in Memory Built-In Self-Test (MBIST) methodologies for ASIC/SoC designs. The ideal candidate should have hands-on experience using Synopsys SMS tool and a solid understanding of MBIST test development, pattern generation, and fault simulation. Key Responsibilities : Develop and implement MBIST algorithms and test patterns for embedded memories (SRAM, DRAM, ROM, CAM) Use Synopsys SMS tool for MBIST pattern generation and validation Perform fault modeling, fault simulation, and fault coverage analysis Integrate MBIST macros into SoC designs in collaboration with RTL and physical design teams Debug MBIST issues in pre- and post-silicon stages Document MBIST flows, generate test reports, and provide support for DFT reviews Stay updated on industry trends and best practices in MBIST and memory testing Required Skills : B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, VLSI, or related fields 4+ years of experience in MBIST implementation and validation Strong experience with Synopsys SMS tool Proficiency in scripting languages like TCL, Perl, or Python Good knowledge of Verilog/SystemVerilog and digital design fundamentals Familiarity with simulation tools like VCS, ModelSim Preferred Skills : Experience with DFT tools such as Tessent Knowledge of ATPG, JTAG (IEEE 1149.1), and IEEE 1500 standards Exposure to silicon bring-up and failure analysis