Application Specific Integrated Circuit Design Engineer

Senior ASIC Design Engineer XBAR IP

Location:

Job Type:

Role Summary ::

Senior ASIC Design Engineer

2. Key Responsibilities

A. RTL & Micro-Architecture Ownership

• Own micro-architecture and RTL development for assigned design modules.
• Define and implement features that meet performance, power, and area targets.
• Make architectural trade-offs based on design constraints and requirements.

B. Cross-functional Engineering Collaboration

• Partner with hardware architects to define critical features and requirements.
• Work with verification teams to validate correctness and completeness.
• Collaborate with timing, VLSI, and physical design teams to ensure:
• Timing closure
• Interface compatibility
• Routability of the design

C. Prototyping & Post-Silicon Support

• Interact with FPGA and software teams to prototype the design.
• Ensure smooth software testing and integration.
• Support post-silicon validation and debug activities.

3. Required Qualifications

A. Education & Experience

• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.

• 5+ years

  of hands-on ASIC design experience.

B. Technical Expertise

• Strong experience in RTL design of complex blocks across 23 projects.
• Proficiency in

  Verilog

  .
• Experience with design and verification tools such as:
• VCS or equivalent simulators
• Debug tools (Debussy, GDB, etc.)
• Deep understanding of the full ASIC design flow:
• RTL design & verification
• Logic synthesis
• Prototyping
• DFT
• Timing analysis
• Floorplanning
• ECO
• Silicon bring-up & lab debug

4. Preferred Qualifications

• Experience with

  memory subsystem

  or

  network interconnect (XBAR) IP

  design.
• Strong debugging and analytical problem-solving abilities.
• Scripting knowledge (Python, Perl, Shell).
• Leadership experience managing small teams (23 members).
• Strong interpersonal, communication, and teamwork skills.