Logic Synthesis Jobs – Apply to Latest Logic Synthesis Job Vacancies

5.0 - 8.0 years

0 Lacs

Bengaluru / Bangalore, Karnataka, India

On-site

Foundit logo

Introduction Physical design team is responsible for designing high performance microprocessor blocks for IBM Power and z mainframe servers. Your role and responsibilities . Responsible for high performance microprocessor blocks RTL to GDSII implementation . Perform block level synthesis, floor-planning, placement and routing. . Close the design to meet timing, power budget and area. . Implement ECOs to address functional bugs and timing violations. . Team player, with good problem solving and communication skills. Required education Bachelors Degree Preferred education Masters Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge andhands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC.. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL ,SKILL and/or TCL

Posted 2 weeks ago

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Senior Manager- Digital/RTL ASIC Design Randstad

15 - 20 years

55 - 95 Lacs

Bengaluru

Hybrid

Exciting Career Opportunity for Senior Manager, Digital/RTL Design (ASIC) Location: Bangalore, India Experience: 12+ Years Work Mode: Hybrid (3 days from the office) Company: A Leading Japanese Semiconductor Manufacturing Company Are you a seasoned Digital ASIC Design professional ready to take on a leadership role? We are seeking a Senior Manager Digital ASIC Design to join one of the worlds top Japanese Semiconductor Manufacturing companies in Bangalore. This is a unique opportunity to work on cutting-edge ASIC designs in a dynamic and innovative environment. Please Note: This role is exclusively for ASIC design (not FPGA or IT-related digital design). Key Responsibilities: Digital Design Leadership: Oversee and manage the Digital Design team, including resource planning, methodology development, and staffing, to support device/silicon design requirements and deliver on program deadlines . Mixed-Signal IC Expertise: 12+ years of experience in Digital Design , with a strong focus on Mixed-Signal ICs , particularly Power Management ICs (PMICs) . Define Digital-Analog boundaries and outline the Digital design scope for Analog-intensive ICs . Design & Architecture: Define micro-architectures and sub-blocks to enable optimized Digital design , RTL design , and Gate-level netlist development. Manage Clock Domain Crossing (CDC) across multiple clock domains while ensuring glitch-free operation. Technical Collaboration: Lead and collaborate on Logic Synthesis , Formal Verification , Power Estimation , and Static Timing Analysis (STA) . Drive the development of OTP, MTP, Efuse read/write , controller design, data bus management, and DFT architecture/integration . If you are passionate about leading advanced Digital Design and driving innovation , we want to hear from you! Apply Now! Send your resume by clicking "Apply" and sharing your CV. Lets connect on LinkedIn: linkedin.com/in/heena-kausar-3a2b94a4 Tag your connections who might be interested! Join us and shape the future of semiconductor technology !

Posted 3 months ago

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