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Job Title : Senior Design Verification Engineer (5+ Years Experience). Location : Bangalore / Hyderabad. Experience : 5+ Years. Domain : SoC/IP/ASIC Verification. Notice Period : Immediate to 15 Days. About The Role We are looking for a Senior Design Verification Engineer (5+ years) with expertise in IP and SoC-level verification. This role requires strong technical expertise, leadership skills, and the ability to collaborate across teams to deliver high-quality, first-time-right silicon. If you have a passion for UVM-based methodologies, debugging complex issues, and mentoring junior engineers, this is the perfect opportunity!. Key Responsibilities Own and drive verification strategy for complex IPs in SoC/ASIC designs. Design and maintain UVM-based testbenches, ensuring high reusability and scalability. Develop and execute comprehensive test plans to achieve high functional and code coverage. Identify, root-cause, and debug complex design and verification failures. Work closely with RTL designers, architects, and system engineers to analyse and resolve issues efficiently. Debug complex verification failures and collaborate with RTL designers and architects to resolve design bugs. Optimize test environments for performance, efficiency, and automation. Work on constraint-random stimulus generation and formal verification methodologies. Communicate technical issues, debug findings, and design concerns effectively across teams. Mentor junior engineers and contribute to the development of best practices in verification methodologies. Automate verification tasks using Python, Perl, or TCL. Required Skills & Qualifications 5+ years of hands-on experience in IP or SoC-level verification for ASIC/FPGA designs. Strong expertise in Verilog, System Verilog, C, and UVM for testbench development. Deep understanding of BUS protocols (AMBA, AXI, AHB, APB, PCIe, DDR, USB etc.) Experience in coverage-driven and assertion-based verification. Strong debugging skills using waveform viewers (VCS, ModelSim, Questa, or similar tools). Hands-on experience with constrained-random verification. Knowledge of formal verification methodologies and static verification tools is a plus. Proficiency in scripting languages such as Python, Perl, or TCL for automation is a plus. Ability to work independently and mentor junior verification engineers. (ref:hirist.tech) Show more Show less
