5 years
3 - 6 Lacs
Posted:1 day ago|
Platform:
On-site
Part Time
We are looking for a Verification Engineer to work on IP-level functional and performance verification using a UVM-based environment. The role involves integrating System C models into UVM, performing functional and performance correlation with RTL, and debugging issues to support timely delivery of RTL-aligned models.
Develop and maintain UVM-based verification environments for complex IP blocks, ensuring comprehensive functional coverage.
Create, execute, and debug testcases in System Verilog to validate RTL functionality and identify design issues early in the cycle.
Analyze design specifications and define verification plans, coverage goals, and test strategies aligned with project requirements.
Collaborate closely with design, architecture, and validation teams to drive resolution of functional bugs and ensure high-quality deliverables.
Continuously improve verification workflows by enhancing testbench components, refining methodologies, and promoting best practices.
Must have
5-8 years of experience in UVM-based IP-level verification.
Strong hands-on expertise in:
System Verilog and UVM methodology
RTL verification and debugging
Solid understanding of digital design concepts and verification methodologies.
Excellent communication and collaboration skills.
Ownership mindset with a focus on quality and timely delivery.
Nice to have
Experience with NOC Subsystem
Good Knowledge of Memory Protocols DDR, LPDDR, HBM
SystemC/TLM modeling concepts
Experience with SystemC-RTL co-simulation setups.
Knowledge of profiling and performance analysis techniques.
Exposure to C++ modeling and high-level performance models.
Experience with scripting languages (Python, Perl, Shell) for automation.
Languages
English: B2 Upper Intermediate
Seniority
Regular
Hyderabad, IN, India
Req. VR-119768
Manual Testing
Automotive Industry
12/12/2025
Req. VR-119768
Luxoft
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3.0 - 6.5 Lacs P.A.
3.0 - 6.5 Lacs P.A.
