600 Timing Closure Jobs - Page 5

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

Physical Implementation activities for Sub systems include Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. You should have good exposure to PD implementation of PPA critical Cores and making right PPA trade-off decisions. Your expertise should include timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. You should be well-versed with Block level PnR convergence using Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. A good understanding of clocking architecture is essential. Collaboration with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc. is a critical part of the role. Proficiency in Tcl/Perl Scripting is required. Experience in working as part of a larger team, meeting project milestones and deadlines, and handling technical deliverables with a small team of engineers is expected. Strong problem-solving skills and good communication skills are essential. Qualcomm India Private Limited is looking for candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience will be considered. A PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience are also acceptable. Qualcomm is an equal opportunity employer and is committed to providing an accessible process for individuals with disabilities. If you require accommodation during the application/hiring process, you may contact Qualcomm at disability-accommodations@qualcomm.com. Employees at Qualcomm are expected to adhere to all applicable policies and procedures, including those related to security and protection of Company confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is only for individuals seeking a job at Qualcomm. Unsolicited submissions from agencies or individuals being represented by an agency will not be considered. Qualcomm does not accept unsolicited resumes or applications from agencies. For more information about this role, please contact Qualcomm Careers.,

As an ASIC Digital Design Engineer, Design Lead at Synopsys, you will be at the forefront of driving innovations that revolutionize the way we work and play. From self-driving cars to artificial intelligence, from the cloud to 5G and the Internet of Things, we are powering the Era of Smart Everything with cutting-edge technologies for chip design and software security. If you are passionate about innovation, we are excited to meet you. Our Silicon IP Subsystems business focuses on accelerating the integration of capabilities into System on Chips (SoCs). With the widest range of silicon IP offerings including logic, memory, interfaces, analog, security, and embedded processors, we help customers meet unique performance, power, and size requirements for their applications. Join us in developing differentiated products and bringing them to market quickly with reduced risk. As a Lead Design Engineer, your responsibilities will include RTL Design, Architecting & Integrating the Subsystems, signing off on the front-end implementation flows, and collaborating with Design and Verification teams to drive the life-cycle of the Subsystems from requirement to release phases. You will work with protocols such as AMBA (APB, AXI, CHI), DDR, PCIe, Ethernet, UFS, USB, and other interface protocols. To excel in this role, you should have knowledge of programming languages like System Verilog, TCL, Perl, or Python, the ability to work independently and drive innovation, and strong communication skills. You will be expected to understand requirements, architect Subsystems based on them, integrate RTL, and lead the Verification closure by interacting with the Verification teams. Key qualifications for Design Engineers include hands-on/lead experience in Subsystems/SOC Design, Architecture, and Implementation, familiarity with Verilog/System Verilog coding and simulation tools, and experience with implementation flows such as synthesis flow, lint, CDC, low power, and others. If you are ready to be part of a collaborative team environment that thrives on innovation and developing cutting-edge solutions, we encourage you to get in touch with us. We are looking forward to speaking with you about this exciting opportunity!,

Physical Design Lead, Manager Job Description The Physical Design Manager leads and mentors teams responsible for designing and delivering customer-specific silicon solutions based on detailed requirements. This role drives the creation of custom integrated circuits (ICs) and oversees building a solid re-use methodology, enabling fast turnaround through physical design flows and ensuring project efficiency, quality, and innovation. Key Responsibilities Manage and mentor a team of physical design engineers, overseeing project schedules, resource allocation, and team performance. Lead all phases of the physical design process, including synthesis, floor planning, placement, clock tree synthesis, place and route, timing closure, power and noise analysis, and verification. Develop and execute design strategies to meet customer-specific silicon requirements, ensuring the final deliverable meets performance, area, and power objectives. Build and maintain a robust re-use methodology, standardizing design practices and enabling quick reuse of IP, flows, and blocks to accelerate project schedules. Resolve complex issues, including timing and congestion challenges in custom high-speed and high-density blocks. Collaborate with cross-functional teams, product managers, and customers to capture requirements and deliver optimized solutions. Champion best practices and drive adoption of leading EDA tools and physical design standards. Guide and participate in physical design verification (LVS, DRC), supporting efficient debugging activities. Promote innovation and continuous improvement through feedback, coaching, and knowledge-sharing. Required Qualifications Bachelor s or Master s degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience managing teams in physical design, plus 5 years of technical experience in the field. Specialized expertise in customer-specific silicon development, from capturing requirements to tape-out. Deep understanding of RTL to GDSII flows, physical synthesis, PNR, STA, and physical verification methodologies. Proven experience implementing re-use strategies and managing design libraries for efficiency. Hands-on proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics. Strong leadership, project management, and communication skills. Desired Attributes Strategic thinker with experience delivering custom silicon solutions for a variety of applications. Inspirational leader adept at developing and mentoring high-performing teams, fostering a culture of re-use and innovation. Customer-focused and proactive in solving technical challenges. Passionate about continuous learning and implementing industry best practices. What MIPS Offers At MIPS, you ll be a member of a fast-growing team of technologists that are creating the industry s highest performance RISC-V processors. Small teams that are part of a non-compartmentalized structure you ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry s most experienced CPU engineers. An unlimited growth path with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting-edge applications with industry-leading customers. At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave! About MIPS MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power-efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products. Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.

Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

ofAbout the Job 3 to 8 years of relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and preferably hands on experience on SoC STA, Power, Physical Verification and other sign-off. Good problem-solving capabilities, proactive, hardworking with strong interpersonal skills. Bachelor's Degree in Electrical, Electronics or Computer Engineering

We are looking for a highly skilled Synthesis & Static Timing Analysis (STA) expert to join our Flows & Methodologies Team in Noida with a hybrid work model where you will be required to work 3 days in the office. As an ideal candidate for this role, you should have a minimum of 6 to 15 years of experience along with strong analytical skills, attention to detail, and the ability to collaborate effectively with cross-functional teams. Proficiency in EDA tools and digital design principles is a must-have for this position. Your key responsibilities will include working closely with SoC cross-functional teams to define and develop Synthesis & STA methodologies for advanced nodes such as 3nm, 5nm, and 16nm. You should possess a strong knowledge of RTL, Synthesis, LEC, VCLP, Timing Constraints, UPF, Timing Closure & Signoff. Experience with EDA tools like Genus, Fusion Compiler, PrimeTime, Tempus, and Conformal will be beneficial for this role. Additionally, strong scripting skills in Perl, TCL, and Python for automation and flow development are required. If you meet the above requirements and are excited about this opportunity, click on the Apply option or share your resume with Heena at heena.k@randstad.in.,

The position of ASIC RTL Engineer [SOC Integration] is currently available in Bangalore, and the work mode is in the office. The ideal candidate should have 4-10 years of experience and hold a B.E./B.Tech or M.E./MTech degree in ECE, EE, or a related field. As an ASIC RTL Engineer focusing on SOC Integration, your primary responsibilities will include leading complex SoC integration efforts. This involves developing top-level architecture and interconnect fabric, designing and implementing critical integration components like clock/power distribution networks, reset controllers, and system-level arbitration. You will also be tasked with resolving sophisticated interface compatibility issues between IP blocks from various sources and developing integration verification strategies. Collaboration with IP teams to ensure seamless integration of all subsystems will be essential, as well as conducting thorough clock domain crossing (CDC) and power domain crossing (PDC) analysis. You will be expected to drive timing closure at the integration level in coordination with physical design teams, implement and optimize system-level power management schemes, and lead design reviews while providing technical guidance to junior integration engineers. Additionally, you will be responsible for developing technical specifications for SoC-level integration requirements. If you are interested in exploring this opportunity, please share your updated resume at vagdevi@semi-leaf.com. Your reference for this position would be greatly appreciated.,

As a Senior ASIC Physical Design Engineer at Synopsys, you will play a crucial role in shaping the future of the semiconductor industry by driving innovations in IC design and physical implementation. Your expertise in high-performance digital design, low-power design, and high-speed clock design will be instrumental in developing cutting-edge solutions for creating high-performance silicon chips. You will collaborate with cross-functional teams to streamline the physical design process, enhance product offerings, and exceed customer expectations. Your responsibilities will include floor planning, developing timing constraints, physical synthesis, clock tree optimization, routing and extraction management, timing closure, signal integrity analysis, physical verification, and design for manufacturability (DFM) checks. By contributing to the development and enhancement of physical design flows for advanced technology nodes, you will drive innovation and improve efficiency in the physical design process. To excel in this role, you should have a solid understanding of IC design principles and physical implementation, experience with the full design cycle from RTL to GDSII, proficiency in deep sub-micron design flows, and hands-on experience with complex design projects and successful tape-outs. You should be a detail-oriented professional with strong analytical and problem-solving skills, an effective communicator, a proactive learner, a dedicated team player, and a creative thinker who can contribute to innovative solutions and improvements. You will be part of a dynamic and innovative team at Synopsys, dedicated to pushing the boundaries of IC design and physical implementation. Together, you will work collaboratively to address complex challenges and deliver exceptional results, driving the technological advancements that shape the future of the semiconductor industry. Synopsys offers a comprehensive range of health, wellness, and financial benefits to cater to your needs. Your recruiter will provide more details about the salary range and benefits during the hiring process. Join us at Synopsys to transform the future through continuous technological innovation and contribute to the growth of our innovative group.,

As an RTL Design Engineer at Alphawave Semi, you will play a crucial role in the advancement of digital technology by contributing to the next generation Chiplet designs. You will be involved in the complete ASIC development cycle, from concept to product, and work on cutting-edge technologies that power innovation in data-demanding industries. Your responsibilities will include microarchitecting and RTL Design of SoC SubSystem/IP blocks, developing UPF and running CLP checks, ensuring RTL quality checks, creating documentation for hardware blocks, and collaborating with various teams to ensure the successful tapeout of high-quality SoCs. To excel in this role, you should possess a Bachelor's or Master's degree in Electrical, Electronics and Communication, or Computer Science Engineering, along with 8+ years of experience in SoC architecture and full-chip design for multi-million gate SoCs. Your expertise should encompass the design convergence cycle, IP dependencies management, project milestone tracking, and experience in CPU, high-speed serial interfaces, or coherence/noncoherent NOC domains. Your skills in communication, collaboration, and leadership will be essential in working effectively in a fast-paced, distributed team environment. You should have a strong understanding of bus protocols, memory controllers, chip IO design, test plans, verification, synthesis, formal verification, timing closure, post-silicon debug, and decision-making under incomplete information. At Alphawave Semi, we offer a hybrid work environment and a comprehensive benefits package that includes competitive compensation, Restricted Stock Units (RSUs), provisions for advanced education, medical insurance, wellness benefits, educational assistance, advance loan assistance, and office lunch & snack facilities. We are committed to equal employment opportunity and welcome applicants from diverse backgrounds, providing accommodations during the recruitment process to ensure a fair and inclusive environment for all candidates.,

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities: Expected to be an SME, collaborate, and manage the team to perform. Responsible for team decisions. Engage with multiple teams and contribute on key decisions. Provide solutions to problems for their immediate team and across multiple teams. Lead and mentor junior team members. Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS. Strong understanding of SOC Architecture Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform. Hands-on experience with ARM (A/M) architecture. Knowledge of C language. Additional Information: The candidate should have a minimum of 5 years of experience in Emulation. This position is based at our Bengaluru office. A 15 years full-time education is required. Qualification 15 years full time education

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group, specifically in the Hardware Engineering area. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, and various other systems to contribute to the development of cutting-edge products. You will collaborate with cross-functional teams to find solutions and meet performance requirements. The ideal candidate should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 4 years of experience in Hardware Engineering, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. Strong understanding and knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools is required. Experience in writing timing constraints, STA, timing closure, pipelining, and multi-clock domain designs is essential. Familiarity with MCMM synthesis, low-power design implementation using UPF, scripting languages such as Perl/Python, TCL, power optimization flows like clock gating, and handling ECOs and formal verification are also necessary. Qualcomm is an equal opportunity employer and is committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by contacting disability-accommodations@qualcomm.com or Qualcomm's toll-free number. The company expects its employees to adhere to all applicable policies and procedures, including those related to security and protection of confidential information. For this role, Qualcomm does not accept unsolicited resumes or applications from staffing and recruiting agencies. Any submissions from unauthorized sources will be considered unsolicited. For more information about this position, please reach out to Qualcomm Careers.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join the Engineering Group. As a Qualcomm Hardware Engineer, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will involve launching cutting-edge, world-class products by collaborating with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. The role involves Physical Implementation activities for high-performance Cores for various technologies, including floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), Low Power verification, PDN, Timing Closure, power optimization, and more. The ideal candidate should have exposure to PD implementation of PPA critical cores, timing convergence of high-frequency data-path intensive Cores, advanced STA concepts, clocking architecture, and should be proficient in Tcl/Python/Perl Scripting for automation. Strong problem-solving skills, communication skills, and the ability to work well in a team are essential. Collaboration with design, DFT, and PNR teams to support issue resolutions is also a key aspect of the role. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations can be requested by contacting disability-accommodations@qualcomm.com. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security and confidentiality requirements. Recruitment agencies are advised that Qualcomm's Careers Site is intended for individuals seeking jobs at Qualcomm. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

You will be responsible for Physical Implementation activities for sub systems, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization. Your role will involve ensuring good exposure to PD implementation of PPA critical Cores and making the right PPA trade-off decisions. You should possess knowledge in timing convergence of high-frequency data-path intensive Cores and advanced STA concepts. Additionally, familiarity with Block level PnR convergence using tools like Synopsys ICC2/ Cadence Innovus and timing convergence in PTSI/Tempus is essential. A good understanding of clocking architecture is required for this role. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, etc. Proficiency in Tcl/Perl Scripting and strong problem-solving skills, along with effective communication skills, are vital for this position. Qualcomm India Private Limited is seeking candidates with a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field and 2+ years of Hardware Engineering or related work experience. Alternatively, a Master's degree in a relevant field and 1+ year of Hardware Engineering experience, or a PhD in a related field, are also acceptable qualifications. The ideal candidate should have 1-3 years of experience in Physical Design/Implementation. Qualcomm is an equal opportunity employer and is committed to providing reasonable accommodations for individuals with disabilities during the application/hiring process. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to security and the protection of Company and proprietary information. It is essential to ensure workplace accessibility for individuals with disabilities. For further information about this role, please contact Qualcomm Careers.,

As a skilled professional with a Bachelor's degree in Electrical or Computer Engineering or equivalent practical experience, along with 6 years of expertise in ARM-based System on a chip (SoCs), interconnects, and Application-Specific Integrated Circuit (ASIC) methodology, you are well-equipped to take on the responsibilities of this role. Additionally, your 5 years of experience in Register-Transfer Level (RTL) design using Verilog/System Verilog and microarchitecture, coupled with your proficiency in a coding language like Python or Perl, make you an ideal candidate for this position. Ideally, you hold a Master's degree or a PhD in Electrical Engineering, Computer Science, or possess equivalent practical experience. Your 6 years of industry exposure in Intellectual Property (IP) design, familiarity with methodologies for RTL quality checks such as Lint, CDC, RDC, and expertise in low power estimation, timing closure, and synthesis further enhance your qualifications for this role. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that drive the future of Google's direct-to-consumer products. Your contributions will play a pivotal role in innovating products that are cherished by millions worldwide. Your expertise will be crucial in shaping the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration. In this role, you will be responsible for designing foundation and chassis IPs (such as Network on Chip (NoC), Clock, Debug, IPC, Memory Management Unit (MMU), and other peripherals) for Pixel System on a chip (SoCs). Collaborating with cross-functional teams including architecture, software, verification, power, timing, and synthesis, you will be involved in specifying and delivering high-quality Register-Transfer Level (RTL). Your role will entail solving technical challenges related to micro-architecture, low power design methodology, and evaluating design options while considering performance, power, and area requirements. Google's mission to organize the world's information and make it universally accessible and useful is at the core of our work. By combining the best of Google AI, Software, and Hardware, we strive to create remarkably helpful experiences for our users. Our team is dedicated to researching, designing, and developing cutting-edge technologies and hardware to make computing faster, seamless, and more powerful, ultimately aiming to improve people's lives through technology. Key Responsibilities: - Participate in test planning and coverage analysis. - Develop Register-Transfer Level (RTL) implementations aligning with power, performance, and area objectives. - Engage in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA) and silicon bring-up processes. - Conduct Verilog/SystemVerilog RTL coding, functional and performance simulation debugging, and Lint/CDC/FV/UPF checks. - Create tools and scripts to automate tasks and monitor progress effectively.,

Exciting Opportunity for Analog Layout Engineers ! Elevate your career with Digicomm Semiconductor Private Limited and take the next leap in your professional journey Join us for unparalleled growth and development, Responsibilities:- Excellent work experience in Analog / Mixed Signal Layout design in advanced FinFET processes like 16nm, 12nm, 10nm, 7nm, 5nm, 3nm Expertise on complete PNR flow CTS,routing, Timing Closure, Hands on experience in any or multiple critical blocks such as SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier etc Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Excellent understanding of CMOS / Bi-CMOS / SOI / FinFET process Experience in AMS IP integration in full chip according to the guidelines demanded by the Full Chip needs Excellent problem-solving skills in Routing Congestion, Physical Verification in Custom Layout Qualifications:BTECH/MTECH Experience:The Engineers with 2 to 8 years of Experience

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SMTS SILICON DESIGN ENGINEER THE ROLE: The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc. Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering #LI-SR4 Benefits offered are described: . AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants needs under the respective laws throughout all stages of the recruitment and selection process.

As a CPU/GPU/IP Implementation Methodologies Engineer, you will be responsible for developing innovative methodologies to implement high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tools to enhance the quality of results and streamline the implementation process. Your role will also involve contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs. You will work with industry-leading Synopsys tools like RTLA and Fusion Compiler to address critical design challenges. Collaboration with a global team will be essential to ensure staying ahead of technological advancements and design complexities. Your contribution will be crucial in driving continuous improvement in PPA and turnaround time (TAT) metrics. To excel in this role, you must possess deep knowledge of synthesis, timing closure, power optimization, and constraints management. Your experience with low-power, high-performance design at advanced nodes below 5nm will be valuable. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX is required to effectively carry out your responsibilities. Familiarity with scripting languages such as TCL, Perl, and Python will aid in performing tasks efficiently. A BS or MS in Electrical Engineering or a related field along with 9+ years of relevant experience is necessary to succeed in this position.,

Qualcomm India Private Limited is looking for an experienced ASIC Design Engineer to join their Engineering Group, Hardware Engineering division. As an ideal candidate, you should hold an MTech/BTech in EE/CS with a minimum of 7 years of experience in ASIC design. Your responsibilities will include micro-architecture development, RTL design, front-end flows, synthesis, DFT, FV, and STA. A good understanding of DDR families and generations, as well as protocols like AHB/AXI/ACE/CHI, will be advantageous. Experience with post-silicon bring-up and debug is a plus. You should be able to collaborate effectively with global teams and possess strong communication skills. Hands-on experience in Multi Clock designs, Asynchronous interface, and Low power SoC design is essential for this role. Your key responsibilities will involve micro-architecture & RTL development, validation for linting, clock-domain crossing, and DFT rules. You will work closely with the functional verification team on test-plan development and waveform debugs at various levels. Experience in constraint development, timing closure, UPF writing, power aware equivalence checks, and low power checks is required. Additionally, you will be supporting performance debugs and addressing performance bottlenecks, along with providing assistance in sub-system, SoC integration, and chip-level debug. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including those related to the protection of confidential information. If you meet the following qualifications and have the required experience, we encourage you to apply for this exciting opportunity at Qualcomm India Private Limited.,

As a Hardware Engineer at Qualcomm India Private Limited, you will play a crucial role in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on cutting-edge technologies such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and DSP systems to contribute to the launch of world-class products. Collaborating with cross-functional teams, you will develop innovative solutions and ensure performance requirements are met. To qualify for this role, you must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 8 years of Hardware Engineering experience. Alternatively, a Master's degree with 7+ years of experience or a PhD with 6+ years of experience in a related field will also be considered for this position. Your primary responsibility will be to develop next-generation SoCs for mobile products and their adjacencies. This role will involve working on all aspects of VLSI development, including micro architecture, platform architecture, front-end design, and design convergence. Additionally, you will oversee physical design and verification aspects to ensure the successful development of SoCs. Key responsibilities for this position include: - Full chip design for multi-million gates SoC - Digital design and development (RTL) - Managing IP dependencies and tracking front-end design tasks - Driving project milestones across design, verification, and physical implementations - Developing architecture and micro-architecture from specifications - Understanding various bus protocols like AHB, AXI, and peripherals such as USB, SDCC - Reviewing top-level test plans and ensuring timing closure - Post-silicon bring-up and debug experience - SoC integration exposure and challenges - Design verification aspects and SoC specification to GDS To excel in this role, you should have a minimum of 15 years of solid experience in SoC design, expertise in Synopsys Design Compiler Synthesis, formal verification with Cadence LEC, and working knowledge of timing closure. Strong communication and leadership skills are essential for effective collaboration with program applicants and mentoring a small to medium-sized group. Qualcomm is an equal opportunity employer committed to providing an accessible process for individuals with disabilities. If you require accommodation during the application/hiring process, please contact Qualcomm via email at disability-accommodations@qualcomm.com or their toll-free number. Qualcomm expects its employees to adhere to all applicable policies and procedures, including security measures related to the protection of confidential information. Please note that Qualcomm's Careers Site is intended for individuals seeking employment directly with Qualcomm. Staffing and recruiting agencies are not authorized to submit profiles, applications, or resumes on behalf of individuals. Unsolicited submissions from agencies will not be accepted. For further information about this role, please reach out to Qualcomm Careers directly.,

ACL Digital is searching for a skilled and experienced Static Timing Analysis (STA) Engineer to become a part of the growing VLSI team. If you possess expertise in timing analysis and have previously handled full-chip designs, we are interested in hearing from you. As an STA Engineer at ACL Digital, your responsibilities will include driving full-chip STA from RTL to GDSII, developing and verifying timing constraints (SDC) for intricate SoCs, conducting timing closure and sign-off utilizing tools such as PrimeTime, collaborating with RTL, physical design, and DFT teams for ECOs and timing fixes, as well as analyzing timing reports, debugging violations, and suggesting optimization strategies. The ideal candidate should have 5-10 years of hands-on experience in Static Timing Analysis, a proven track record in full-chip STA and timing sign-off, a strong understanding of timing constraints, multi-mode/multi-corner (MMMC) flows, familiarity with scripting languages (TCL, Perl) and STA tools (preferably Synopsys PrimeTime), and excellent analytical, debugging, and cross-team communication skills. This position is based in Pune/Bangalore and requires an immediate notice period. Join ACL Digital to be a part of a dynamic team delivering next-gen semiconductor solutions. You will have the opportunity to work on cutting-edge technology projects with top-tier clients globally.,

Job Description Key Responsibilities: Timing Analysis & Closur e Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations and optimizing paths. Constraint Development Define and validate timing constraints (clocks, I/O delays, false/multi-cycle paths). Integrate constraints from multiple IPs for hierarchical STA. Tool Usage & Flow Integration Use STA tools like Synopsys PrimeTime, Cadence Tempus , or equivalent. Integrate STA into the overall design flow and automate processes for efficiency. Job Description: Provide expert guidance on STA methodologies, including setup and hold time analysis, clock domain crossing, and multi-cycle paths for Full Chip, Sub-system and complex IP timing closure. Define and implement timing constraints from scratch such as clock definitions, input/output delays, and path constraints for Full-Chip, Sub-system to ensure accurate timing analysis. Able to integrate the existing timing constraints from various IP for Full-Chip/Sub-system timing analysis. Deep knowledge of STA tools (such as Synopsys PrimeTime, Cadence Tempus, or Mentor Graphics' ModelSim) including their capabilities, limitations, and best practices. Guide the integration of STA tools into the overall design flow, ensuring compatibility and optimal performance. Oversee the process of achieving timing closure, addressing any timing violations and guiding optimizations to meet performance goals. Primary Skills: Deep Technical Knowledge: In-depth understanding of STA concepts, EDA tools, and methodologies. Experience in timing constraints development, timing closure for Full-Chip/Sub-system to meet the design performance. Problem-Solving Skills: Strong analytical and problem-solving abilities to tackle complex timing issues. Communication Skills: Ability to communicate complex technical concepts effectively to various stakeholders. Leadership and Mentoring : Experience in leading teams and mentoring less experienced engineers in STA practices Secondary skills: Design flow management Able to improve the execution efficiency through flow automation and other value adds Cross functional co-ordination Work closely with other teams, such as RTL design, Physical design , design, verification, and manufacturing, to ensure seamless timing closure of physical design.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. The Cadence Advantage The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact. Cadence s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees. The unique One Cadence One Team culture promotes collaboration within and across teams to ensure customer success Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other every day. Job responsibilities: 6+ years of DFT Experience with strong understanding of DFT methodologies and flows. Hands on Experience in ATPG, coverage analysis, ATPG DRC debug etc. Debugging DFT simulations for setup and hold corners. Strong understanding in fault modeling techniques and experience in architecting DFT structures for Serdes IP s Knowledge in test mode timing constraints Hands on experience with script development for automation. Hands on Experience in to Boundary scan in 1149.1/1149.6 & IEEE P1687 IJTAG flow. Exposure to Static Timing Analysis & Timing closure is required. Strong written and oral communication skills Experience working with cross functional teams Job Role: The candidate is expected to build Requirements for DFT for customers of the IP group and work with developing all the DFT verification and customer deliveries To complete the scan features of the IP. Candidate is required to own the end to end development and discussion with customer for all DFT related work. Day to Day automation of script for flow development in closing the activities for DFT completion

Role: Design Analysis Engineer (FPGA/Vivado) [M.Tech Mandatory] What they do: Analyze design issues in Vivado implementation flow. Apply and debug timing constraints to ensure design closure. Propose/design corrections to fix issues. Use scripting (Shell/Python/TCL) to automate and improve analysis. (RTL/Verilog knowledge is optional, not mandatory.) Mandatory Skills: Strong in Timing Constraints (STA concepts) Hands-on with Vivado tool flow Shell/Python/TCL scripting for automation Good to have: Quartus exposure Basic RTL/Verilog understanding In short: This is not an RTL coding role. Its a timing + Vivado design analysis role with scripting. Feel free to share the resume if you feel its a good fit svishnuraj@teksystems.com

Role & responsibilities Should have in depth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS Should have worked on the latest technology nodes (14nm or lesser). Must have experience in Static timing analysis Must have experience in Physical verification and appropriate fixes Should have worked on block level and top-level designs Good to have worked on designs without a customer flow. Strong problem-solving skills and communication skills. Ability to mentor and work closely with junior engineers Location: Bangalore/Kochi/Chennai