880 Timing Closure Jobs - Page 6

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

About The Role : To work independently on block/IP levels analog layout design from schematic. Estimating the Area, Optimizing Floorplan, Routing and Verifications. Good at LVS/DRC debugging skills and other verifications for lower technology nodes like 5,7,10, 14nm FinFet and below. Good understanding of Matching, EM, ESD, Latch-Up, Shielding, Parasitic and short channel concepts. Familiar with EDA tools like Cadence Virtuoso Editor & Calibre RVE Good interpersonal skills and critical thinking abilities to resolve the issue technically, and professionally. Key Responsibilities: Independently execute block/IP-level analog layout from schematics, including area estimation, floorplan optimizat...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles &...

Hello Visionary! We empower our people to stay resilient and relevant in a constantly changing world. Were looking for people who are always searching for creative ways to grow and learn. People who want to make a real impact, now and in the future. Does that sound like you? Then it seems like youd make a great addition to our vibrant international team. We provide a variety of competitive, innovative, and reliable Record-to-Report services from maintaining financial records to financial closing and reporting. We process, compile, and deliver relevant financial information covering Accounting & Closing, Commercial, Tax and Master Data Services. We deliver maximum value to the business by dri...

About The Role Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : SAP FI S/4HANA Accounting Good to have skills : SAP FI S/4HANA Central Finance Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure that application requirements are met, overseeing the development process, and providing guidance to team mem...

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times I...

Job Purpose To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues 2.Resolving BRE level issues 3.Educating internal and field teams on issues due to training requirements 4.Constant observations on the issues raised by the field team 5.Raising regular IT request to resolve issues 6.Constant communication between IT and Product teams to identify the changes 7.Attending bi-weekly meetings with IT to find the bigger solution 8.Find solutions to the repetitive problems and submit BRD 9.Interacting with field teams to...

Job Purpose To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues 2.Resolving BRE level issues 3.Educating internal and field teams on issues due to training requirements 4.Constant observations on the issues raised by the field team 5.Raising regular IT request to resolve issues 6.Constant communication between IT and Product teams to identify the changes 7.Attending bi-weekly meetings with IT to find the bigger solution 8.Find solutions to the repetitive problems and submit BRD 9.Interacting with field teams to...

Job Purpose To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues 2.Resolving BRE level issues 3.Educating internal and field teams on issues due to training requirements 4.Constant observations on the issues raised by the field team 5.Raising regular IT request to resolve issues 6.Constant communication between IT and Product teams to identify the changes 7.Attending bi-weekly meetings with IT to find the bigger solution 8.Find solutions to the repetitive problems and submit BRD 9.Interacting with field teams to...

As part of the power methodology team, the Emulation-Based Power Analysis and Methodology Engineer will be responsible for developing and driving emulation-based power analysis strategies using RLE (Register-Level Emulation) and GLE (Gate-Level Emulation) techniques This role focuses on building accurate, scalable flows that integrate power estimation with functional emulation to provide actionable insights on real-use power behavior across complex SoCs and IPs, Responsibilities Develop and maintain power analysis methodologies demonstrating RLE and GLE platforms, Collaborate with design and emulation teams to define use cases and collect realistic activity traces, Automate power estimation ...

As a Senior RTL Design Engineer at Google, you will play a crucial role in developing custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation behind globally beloved products. Your expertise will be instrumental in shaping the next generation of hardware experiences, focusing on delivering unmatched performance, efficiency, and integration. Key Responsibilities: - Manage a team of RTL engineers, overseeing the design of complex machine learning compute IPs by fully comprehending architecture specifications and collaborating with software and architecture engineers to identify crucial design requirements. - Collaborate with Verification and Silicon Va...

As a Senior SoC Design Engineer at Qualcomm India Private Limited, you will be utilizing your 10-16 years of experience in SoC design. Your responsibilities will include working with AMBA protocols such as AXI, AHB, and APB, understanding SoC clocking/reset/debug architecture, and dealing with peripherals like USB, PCIE, and SDCC. It is crucial to have expertise in memory controller designs, microprocessors, constraint development, and timing closure. Collaboration with SoC verification and validation teams for pre/post Silicon debug will be an integral part of your role. Additionally, hands-on experience in Low power SoC design, Multi Clock designs, Asynchronous interface, and proficiency i...

Role Overview: You should have experience in Timing Closure, including skills in Placement and Routing (PnR), Static Timing Analysis (STA), and TCL scripting. Additionally, you should have at least 1+ years of experience in FPGA Design. Key Responsibilities: - Work on Timing Constraints (SDC) & Static Timing Analysis - Utilize ASIC and/or FPGA software tools like Vivado or Quartus - Apply strong Digital Design Fundamentals and applications - Implement TCL Scripting language - Work on Applications and Designs in Wireless/Wired domain Qualifications Required: - BS or MS in EE or CE - Minimum of 2+ years of experience in digital design and/or timing closure - Strong background in RTL design usi...

Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects of PD from Synthesis to GDSII, Strong background in Floorplanning, Placement, CTS, Routing, P&R, Extraction, IR Drop Analysis, Timing, and Signal Integrity closure Experience at taping out multiple chips, strong experience at the top level at the latest technology nodes. CAD, Methodology & IP team collaboration is very essential for PD implementation, must conduct regular sync-ups for deliveries. Significant knowledge and preferably hands on experience on SoC STA, Power, Physic...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis (CTS), formal verification, physical verification (DRC/LVS), power delivery network (PDN), timing closure, and power optimization. Your role will involve making PPA trade-off decisions for critical cores, ensuring timing convergence of high-frequency data-path intensive cores, and implementing advanced STA concepts. You will work on block-level PnR convergence using tools like Synopsys ICC2/Cadence Innovus and timing convergence in PTSI/Tempus in the latest technology nodes. Additio...

Job Title: RTL Design Engineers Exp Level: 2-3 yrs Loctaion: Hyderabad Job Description: Seeking a motivated RTL Design Engineer to develop, integrate, and verify digital logic using Verilog/SystemVerilog . Responsibilities include ASIC/SoC IP integration , linting, synthesis, and working closely with verification teams. Requires strong fundamentals in digital design , timing closure, and understanding of the ASIC flow. You'll debug simulation failures, implement ECOs, and support gate-level simulations. Collaborate with cross-functional teams (SW, DV, Physical Design) to achieve tapeout goals. Bachelor's or Master's degree in engineering in EE/CS is essential, along with 2-3 years of relevan...

As a Senior Member of Technical Staff (SMTS) Silicon Design Engineer at AMD, you will be part of a highly experienced CPU physical design team, responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMD's next-generation processors. Your role will be crucial in a fast-paced environment with cutting-edge technology. Key Responsibilities: - Own critical CPU units and drive to convergence from RTL-to-GDSII, including synthesis, floor-planning, place and route, timing closure, and signoff. - Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoff...

Role Overview: As a member of the team, you will be part of a group dedicated to pushing boundaries and developing custom silicon solutions for Google's direct-to-consumer products. Your contributions will play a key role in shaping the future of hardware experiences, ensuring unparalleled performance, efficiency, and integration for products loved by millions worldwide. Key Responsibilities: - Develop all aspects of RTL2GDS for ASIC/Mixed signal chips. - Take complete ownership of physical design integration and CAD flow for Mixed signal chip development. - Drive the closure of timing and power/Physical convergence of the design. - Contribute to physical design methodologies and automation ...

Responsible for mobilizing youth for training programs and ensuring successful placement through employer engagement and community outreach. Mobilize youth and conduct outreach Counsel and enroll candidates Coordinate placements and employer interactions Maintain placement records and follow-ups Support training and center operations

Responsible for mobilizing youth for training programs and ensuring successful placement through employer engagement and community outreach. Mobilize youth and conduct outreach Counsel and enroll candidates Coordinate placements and employer interactions Maintain placement records and follow-ups Support training and center operations

Job Summary: We are looking for a proactive and detail-oriented STA Engineer (Supplier Technical Assistance Engineer) to manage and support supplier development and performance. You will be responsible for ensuring that suppliers meet the companys quality, technical, and delivery standards across all phases of the supply chain, from sourcing to production. Key Responsibilities: Evaluate and approve new suppliers through audits, assessments, and technical reviews Monitor and improve supplier performance in terms of quality, cost, delivery, and compliance Provide technical support to suppliers to ensure part quality and manufacturability Work closely with suppliers on PPAP (Production Part App...

Role Overview: Looking for experienced Physical Design Engineer with 4+ years in block-level implementation. The role emphasizes PnR, STA, and logic implementation, driving designs that meet PPA requirements while ensuring sign-off quality. Key Requirements: *Hands-on in floor planning, placement, CTS, routing, and optimization. *Strong background in PnR flows, resolving timing, congestion, power, and SI challenges. *Skilled in STA analysis, ECO handling, and top-level support. *Tool expertise with Synopsys / Cadence and logic equivalence checks. *Proficient in design rule checks (DRC/LVS) and PPA-driven optimizations. *Familiarity with low-power techniques and scripting (TCL, Perl, Python).

In your new role you will: Responsible for leading Physical Design and Timing Closure of low-power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design,methodology and process aspects. Enable next generation of place and route engineers via mentoring and thought leadership. You are best equipped for this task if you have: Hands-on experienc...