600 Timing Closure Jobs - Page 6

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills:

Education : BTech in ECE/EEE or MTech VLSI No. of positions : 5 Desired Skills: Minimum 3+ year of experience Should have block/SOC level netlist-gds2 experience. Expertise in Floor planning, Power planning, CTS. Should be capable of handling block-level timing closure. Good scripting skills (TCL/Perl/Shell). Experience on low power implementation techniques is preferred. Synopsys/Cadence tool experience is preferred. Should be a team player and perform lead role where ever required. Good communication analytical skills.

Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

B.E / B.Tech in ECE / EEE 3 to 7 years Brief JD: Development of FPGA logic for signal processing, control logic, or high-speed interfaces. Detailed JD: Job Description: Design and simulate FPGA logic using VHDL / Verilog. Develop and integrate IP cores for VPX/VME boards. Perform timing analysis, floorplanning, and optimization. Interface with embedded software and hardware teams. Support lab testing and verification on hardware platforms. Professional Skills / Technical Knowledge: Experience with Xilinx (Vivado), Intel (Quartus), or Lattice toolchains. Strong understanding of timing closure, constraints, and protocols (PCIe, Ethernet). Hands-on with test benches, simulation tools. Defense and aerospace exposure is a strong plus.

As a member of the team at this organization, you will play a crucial role in the development of custom silicon solutions that will drive the future of Google's direct-to-consumer products. Your contributions will be instrumental in the innovation process that leads to the creation of products that are beloved by millions around the globe. Your expertise will be key in shaping the next generation of hardware experiences, ensuring exceptional performance, efficiency, and integration. With a Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience, and a minimum of 3 years of experience in Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture, and automation, you are well-equipped to excel in this role. Additionally, you should have 3 years of experience with Register-Transfer Level quality check tool flows such as Lint, Clock Domain Crossing, Reset Domain Crossing, and Synthesis. Preferred qualifications include experience with methodologies for RTL quality checks, IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols, and ASIC methodology. Additionally, experience with methodologies for low power estimation, timing closure, synthesis, and knowledge in areas such as Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, and Pin Multiplexing would be advantageous. Your responsibilities will involve defining microarchitecture details for the integration of Intellectual Property's (IPs) at the macro/Sub-System Workload Requirements Plan (SSWRP) level. You will be engaged in RTL development using SystemVerilog, debugging functional/performance simulations, and conducting RTL quality checks including Lint, Clock Domain Crossing (CDC), Synthesis, and Unified Power Format (UPF) checks. Furthermore, you will participate in synthesis, timing/power estimation, and FPGA/silicon bring-up processes. Join us in our mission to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create experiences that are radically helpful. By researching, designing, and developing new technologies and hardware, we aim to make computing faster, seamless, and more powerful, ultimately improving people's lives through technology.,

You have 7 to 10 years of experience and the job is located in Bangalore with the requirement to work from the office. As an experienced engineer joining our team, your primary skill requirements will include exceptional digital fundamentals. You should have hands-on experience in system design with FPGA devices using relevant FPGA EDA tools. Additionally, you are expected to have experience in designing and implementing FPGA-based solutions using Microchip, Xilinx, or Altera FPGAs. Your responsibilities will also involve writing high-quality code in Verilog/System Verilog, VHDL, and C for embedded processors, as well as maintaining existing code. Moreover, you will be responsible for developing testbenches using Verilog/System Verilog, verifying validation designs in a simulation environment using BFM/VIP, and working with synthesis and placement constraints. You should be well-versed in STA constraint definition and timing closure for high-speed designs, as well as validating FPGA-based implementations on HW boards. In addition to the primary skill requirements, you should have experience in writing embedded FW programs in C/C++, strong lab debug experience, and the ability to solve systems-level hardware issues using lab equipment, embedded debuggers, and RTL debuggers. It is essential to be familiar with on-chip debug tools, scripting languages like tcl/perl, version management systems such as GitHub and SVN, and have excellent verbal and written communication skills in English. Furthermore, you are expected to have a strong technical background in silicon validation, failure analysis, and debug. Understanding hardware architectures, utilizing silicon features, and having basic knowledge of embedded processors like ARM Cortex-M3 or RISC-V, along with familiarity with AMBA protocols APB, AHB, AXI, and ACE, will be advantageous. Depending on your experience level, specific skill needs may vary. For a Lead Engineer specializing in Serdes, DDR, SOC, or Configuration Security, you will be required to have hands-on FPGA silicon validation experience, protocol expertise in areas like PCIe-Gen4/5, DDR-4/5, Ethernet, and Processor-based subsystems, and the ability to plan, execute, and handle complex FPGA system projects. As part of your role, you will be responsible for managing work assignments, training and mentoring junior team members, tracking dependencies, providing guidance in debugging issues, and ensuring the delivery of assigned use cases. Your expertise in PMA/PCS architecture, DDR memory interface training, processor subsystem validation, or configuration and security aspects will be crucial for the successful execution of projects. Additionally, if you have expertise in electrical characterization of memory interfaces or serial interfaces, experience with FPGA design flows, firmware development on multi-core microcontrollers, and a solid understanding of electrical engineering fundamentals, you will be a valuable asset to our team. Thank you for considering this opportunity at Mirafra Software Technologies Pvt. Ltd. Best Regards, Kalpana Bhatia Team Lead - Talent Acquisition,

Job Description: Strong understanding of Physical Design with hands-on experience in RTL2GDS flow. Ability to close tiles/blocks including timing, noise, power, IR, phyV, conformal equivalence, and signoff checks. Exposure to advanced technology nodes (7nm and below) and related design challenges. Experience with the Synopsys tool suite is required. Knowledge of high-frequency design (>2GHz)

As a candidate for this role, you should hold a Bachelor's degree in Electrical/Computer Engineering or possess equivalent practical experience. You should also have at least 2 years of experience working with RTL design using Verilog/System Verilog and microarchitecture, particularly in the realm of ARM-based SoCs, interconnects, and ASIC methodology. A Master's degree in Electrical/Computer Engineering would be considered a preferred qualification for this position. Additionally, experience with methodologies for RTL quality checks (such as Lint, CDC, RDC) and low power estimation, timing closure, and synthesis would be beneficial. Join a dynamic team that is dedicated to pushing boundaries and developing custom silicon solutions that will power the future of Google's direct-to-consumer products. Your contributions to this team will play a crucial role in shaping the innovation behind products that are beloved by millions around the globe. Your expertise will be instrumental in defining the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration. Within our platform IP team, you will collaborate on designing foundation and chassis IPs for Pixel SoCs, including components such as NoC, Clock, Debug, IPC, MMU, and other peripherals. Your role will involve partnering with colleagues from various disciplines including architecture, software, verification, power, timing, and synthesis to specify and deliver RTL. You will be tasked with solving technical challenges using innovative micro-architecture, implementing low power design methodologies, and assessing design options based on complexity, performance, and power considerations. At Google, our mission is to organize the world's information and make it universally accessible and useful. By combining the strengths of Google AI, Software, and Hardware, our team strives to create profoundly helpful experiences. We engage in research, design, and development of new technologies and hardware to enhance computing speed, seamlessness, and power, ultimately aiming to improve people's lives through technology. Your responsibilities in this role will include defining microarchitecture details such as interface protocols, block diagrams, data flow, and pipelines. You will be involved in RTL development using SystemVerilog, debugging functional and performance simulations, conducting RTL quality checks (including Lint, CDC, Synthesis, UPF checks), participating in synthesis, timing/power estimation, and FPGA/silicon bring-up, as well as collaborating with multidisciplinary teams across different locations.,

Your Role Implement and configure SAP Document and Reporting Compliance (DRC) in S/4HANA environments. Design scalable solutions for global e-invoicing and statutory reporting. Integrate SAP DRC with FI, SD, and MM modules for accurate compliance. Collaborate with technical teams for interface development and automation. Support legal change management and country-specific compliance updates. Your Profile 4-12 years of SAP functional consulting experience, including SAP DRC (ACR). Strong knowledge of global statutory reporting and e-invoicing frameworks. Hands-on experience with SAP DRC configuration across multiple countries. Proficient in S/4HANA and integration with core SAP modules. Excellent communication and stakeholder management in global projects. Location -Bengaluru,Chennai,Hyderabad,Mumbai,Pune

Responsibilities As a creative Design Constraints Engineer, you will be part of the Front-End Design team, developing, validating , optimizing , and handing off constraints for complex SoCs, ensuring robust timing closure and seamless integration across the various stages of SOC design cycle. Your key responsibilities will include creating and maintaining Design constraints, validating them using industry standard STA tools and handing off to the Implementation teams. You will closely work with the Design team to capture the Design constraints. You will be validating these constraints using industry standard constraint validation tools like Time Vision and other equivalent tools. You will partner with the Implementation teams to resolve timing and constraint-related issues . You will also contribute to developing and enhancing the design methodologies used by the team. You will guide and support other members of the team as needed to enable the successful completion of project activities. Required Skills and Experience: Bachelor s or master s degree on Electrical & Electronics Engineering, VLSI or an equivalent discipline. Experience of 8+ years working in Design, Synthesis and Design constraints of complex Subsystems or SoCs Strong expertise in SDC syntax and timing constraint methodologies Expertise in Constraints development and validation tools such as Time Vision, or any equivalent Proficient in STA tools such as Synopsys PrimeTime , Cadence Tempus, or equivalent Experience in synthesis tools (Design Compiler, Genus) and PnR tools (ICC2, Innovus) preferred Familiarity with multi-mode multi-corner (MMMC) timing closure Proficient in Perl, Python, Tcl or other scripting language Good communication (written, verbal, presentations) skills. Desired Skills and Experience: Experience leading Synthesis and Design constraints for Subsystems or SoCs Knowledge of clock-domain crossing (CDC) and asynchronous design constraints Familiarity with formal verification of constraints. Exposure to high-speed interface constraints (DDR, PCIe, etc.). Knowledge of DFT and Physical Implementation Experience with ARM-based designs and/or ARM System Architectures Equal Opportunities at Arm Apply Save Job View location Our Hiring Process

As a part of Arms Solutions Engineering group we like to think we are not just crafting sophisticated SoCs, but we are defining future chip design techniques. Not only do we improve the power, performance and system integration of our products, but we also craft the design flows, influence Electronic Design Automation (EDA) tools and build the knowledge base that makes custom SoC and CPU chip design possible. At Arm, our work goes beyond multiple divisions where we drive improved implementation for Arm and our partners. A key component of this is the development of comprehensive implementation and analysis methodologies. Responsibilities: Synthesis, Physical implementation, Timing closure and Physical signoff of CPU cores, system interconnect and other ARM Designs. . Timing constraints development and validation for functional and test modes Analyze design timing, area and power to help improve the quality of ARM Design. Optimize design, flow and methodologies to achieve best in class PPAT working with various internal and external teams. Develop and deploy new methodologies to improve implementation efficiency and results Support and develop detailed implementation analysis and data-mining methodologies. Work with implementation and physical IP RTL design teams to drive analysis and optimization of our IP. Converting R&D concepts into real implementation solutions. Enable our partners to achieve the best possible quality of results Required Skills and Experience : Bachelors or Master s degree equivalent in Electrical Engineering, Computer Engineering or other relevant technical fields. 7+ years of proven experience in ASIC Implementation, Physical design, STA and Timing closure, Structured clock tree, PDN analysis, DFM and Physical verification Strong Communication and Problem Solving Skills. Experience in crafting and adopting new silicon implementation techniques and methodologies and promote their use with international teams

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to develop the feature and close design Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 10 to 15 years of work experience in one or more areas: Processor Architecture/ microarchitecture/ Logic design – Deep technical understanding of dynamic power saving, power capping, droop mitigation techniques. Experience in working with research, architecture/ FW/ OS teams Experience in low power logic design Experience in working with verification, validation for design closure including test plan reviews, verification coverage Good understanding of Physical Design, and able to collaborate with physical design team for floor-planning, placement of blocks for achieving high-performance design and timing closure of high frequency designs Experience in silicon bring-up

About Marvell Marvells semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Built on decades of expertise and execution, Marvells custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, youll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, and networking applications. What You Can Expect This role is based in Bangalore India. You will work with both local and global team members on the physical design of complex chips and lead the development of advanced methodologies that enable scalable, high-performance implementation. As a Principal Engineer, you will operate at the intersection of technical depth and strategic influence, driving innovation across teams and projects. Architect and lead the development of next-generation physical design methodologies and automation flows. Provide deep technical leadership in RTL-to-GDSII implementation, including synthesis, floorplanning, place and route, clock tree synthesis, and timing closure. Serve as a key technical advisor across multiple projects, influencing design decisions and resolving complex implementation challenges. Collaborate with global cross-functional teams, including RTL, verification, and CAD, to ensure cohesive and optimized design execution. Mentor and coach senior and junior engineers, fostering technical growth and promoting best practices across the organization. Evaluate and drive adoption of emerging EDA tools and technologies in partnership with internal CAD and external vendors. Represent the physical design team in strategic technical discussions with internal and external stakeholders, contributing to roadmap planning and methodology evolution. What We&aposre Looking For Bachelors, Masters, or PhD degree in Electrical Engineering, Computer Engineering, or a related field. 12+ years of progressive experience in back-end physical design and verification, including leadership roles. Deep understanding of RTL to GDSII flows, including synthesis, place and route, clock tree synthesis, and timing closure. Strong expertise in static timing analysis (e.g., PrimeTime, Tempus) and power/signal integrity tools (e.g., Voltus, RedHawk). Proficient in scripting languages such as Python, Perl, Tcl, and Makefile for automation and flow development. Demonstrated experience in developing and deploying physical design methodologies and flows. Strong communication and collaboration skills, with the ability to mentor junior engineers and influence cross-functional teams. Experience working with EDA vendors and evaluating new tools and technologies is a plus. Additional Compensation And Benefit Elements With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. Were dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what its like to work at Marvell, visit our Careers page. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Show more Show less

Key Responsibilities : We are looking for a highly motivated software engineer to work in the QuestaSim R&D team of the Siemens EDA Development responsibilities will include core algorithmic advances and software design/architecture. You will collaborate with a senior group of software engineers contributing to final production level quality of new components and algorithms and to build new engines and support existent code. Self-motivation, self-discipline and the ability to set personal goals and work consistently towards them in a dynamic environment will go far towards contributing to your success. Are you excited to know more about this Role ? Job Qualification: An ideal candidate should have skills below: B.Tech or M.Tech in Computer Science & Engineering (CSE), Electrical Engineering (EE), or Electronics & Communication Engineering (ECE) from a reputable engineering institution having 8 - 15 years of experience. Strong knowledge of C/C++, algorithms, and data structures. Familiarity with compiler concepts and optimizations. Experience with UNIX and/or LINUX platforms is essential. Excellent problem-solving and analytical skills. Self-motivated with the ability to work independently and guide others towards successful project completion. We are not looking for superheroes, just super minds! Having the below skills will be an added advantage: Strong understanding of basic digital electronics concepts. Familiarity with machine learning (ML) and artificial intelligence (AI) algorithms, particularly their implementation in data-driven tasks. Proficiency in hardware description languages such as Verilog, SystemVerilog, and VHDL. Experience with parallel algorithms and job distribution techniques. Exposure to simulation or formal verification methodologies is a plus.

Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integration and timing methodology/analysis. Develop and analyze functional coverage. Help define, evolve, and support our design methodology. Collaborate with the verification team to address design bugs and close code coverage. Work closely with the physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures Perform diagnostic and post-silicon validation tests in the lab Minimum Qualifications: Bachelor's Degree / Master's Degreein Electrical or Computer Engineering with 7+ years of ASIC design. Prior experience working with Verilog or System Verilog programming skills Experience with simulators/synthesis/static timing constraints and related tools (e.g., VCS, DC, PrimeTime) Experience with debugging and verification methodologies Preferred Qualifications: Understanding of Networking technologies and concepts Scripting experience (Python, Perl, TCL, shell programming) Experience with formal verification tools Experience with emulation

BE Mechanical/Electrical with 6-10 years of experience in the Energy/Manufacturing sector/Auto Sector Preferred candidates from high voltage industry Candidates will be responsible for - Procurement from Import and Domestic (Timely placement of PO's, ensuring on time delivery, incoterm, optimizing freight, timely forecasting etc) Procurement of casting ,machining, sheet metal, fabrication, electrical articles & equipment's (CT/VT/Panels etc)for production (assembly) ensuring freight optimization & product cost out for high voltage GIS(Gas Insulated Switchgear) upto 400kv. Inventory management -Ensuring ITR targets Built safety stocks for Delivery, quality critical parts ensuring lead times Initiate & drive cost out measures Explore new suppliers & expedite development Maintain business relationship with all supplier for best outcome Travelling /Visit to suppliers required. (As per business requirement) Excellent Communication skills (Written/Oral).

Job Role: * Collaborate with cross-functional team on timing closure. * Perform STA using TCL and MMMC tools. * Ensure compliance with industry standards during static timing analysis. Mail: chaitanya.vasamsetti@gigaopsglobal.com Contact: 7729881999 Office cab/shuttle Food allowance Health insurance Annual bonus Provident fund

Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for complex SoCs. Experience inVerilog/System-Verilogis a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ASIC is required. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience creating pad ring and working with the chip level floorplan team is an added advantage Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime isrequired. Minimum Qualifications: Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Preferred Qualifications 2-9 years of experience in SoC design Educational Requirements: 2+ years of experience with abachelors/masters degree in Electrical engineering

Bachelors degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 8+ years of Hardware Engineering or related work experience. OR Masters degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 7+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. Job Role Work with Physical design engineers to rollout robust, identify areas for flow improvement methodologies. (area / power / performance / convergence) , develop plans and deploy/support them Power performance area improvement using synthesis and place and route tools. Support physical design flows using icc2/innovus tools Provide tool support and issue debugging services to physical design team engineers across various sites Develop and maintain 3rd party tool integration and productivity enhancement routines Understand advance tech PNR and STA concents and methodologies and work closely with EDA vendors to deploy solutions. Skill Set Good TCL, Perl programming skills Knowledge of one of Encounter/Innovus or Icc2 or Olympus tool (or other equivalent PNR tool) is mandatory Basic understanding of Timing/Formal verification/Physical verification/extraction are desired Ability to ramp-up in new areas, be a good team player and excellent communication skills desired Experience 15+ years of experience with the Place-and-route and timing closer and power analysis environment is required Niche Skills Handling support tools like Encounter / Innovus / edi / Icc2 / Olympus / Nitro (or other equivalent PNR tool). One or more of the above is mandatory* Technology enablement for sub-5nm nodes from primary process nodes.

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 6-12 years of experience in physical design from product-based/EDA companies. DDRPhy /PCIE-high speed interface PD Timing Signoff experience with SNPS/CDNS tools PDNIR signoff and Physical verification knowledge Automation skills python/Perl/TCL RDL-design + Bump Spec understanding for smooth SoC PDN integration and signoff Proficiency in automation to drive improvements in PPA Experience working on multiple technology nodes in advanced processes. Experience in low power design implementation, including Unified Power Format (UPF), multi-voltage domains, and power gating. Familiarity with ASIC design flows and physical design methodologies. Good to Have: Design level knowledge to optimize the implementation for PPPA Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Overview In this highly cross functional role, you will be part of the Global Design Enablement team responsible for the physical verification aspects of PDK development. You will conceptualize, develop, maintain and improve the Physical Verification flows. The role requires you to work on flow and rule deck development for various technology nodes utilizing the state of the art tools. You will be collaborating with the Custom Digital/Analog/Mixed Signal/RF, Physical design (PD) and Chip integration teams to understand their requirements and challenges and enabling flows to meets their needs. This role requires a thorough understanding of Design Rule Checks (DRC), Layout Versus Schematic (LVS) and Layout and Programmable ERC, implementing the rules from scratch and/or modify the existing ones . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Minimum Qualification Minimum 5 years experience in a hands-on PDK role Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/PERC/ESD/Latch-up/Antenna. As a member of the Physical Verification CAD team, you will maintain and improve all aspects of physical verification flow and methodology Code custom checks such as Layout/Programmable ERCs, addition of custom devices in LVS, implementation of custom design rules(DRCs), etc to meet the needs of the design teams You will need to have a deep understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, writing from scratch and/or modify existing ones. Proficiency in integration and tech setup of Calibre LVS with StarRC/QRC and other Extraction tools Support the design teams with solving their PV challenges to facilitate the IP release and Chip tapeouts Collaborate with tool vendor and foundries for tools and flow improvements Knowledge of deep sub-micron FINFET, Planar, SOI and PMIC process technologies and mask layout design Proficiency in one or more of the programming/scripting languages- , Python, Unix, Perl, and TCL. Good communication skills and ability to work collaboratively in a team environment Applicants Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [HIDDEN TEXT] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. To all Staffing and Recruiting Agencies Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. If you would like more information about this role, please contact Qualcomm Careers.

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

SUMMARY Part-Time Weekend Job Join Leading Food & Beverage Industry Team in Chennai Job Role: Weekend Supporting Staff Company: Food & Beverage Industry Location: Chennai Work Locations: T. Nagar Nungambakkam Vadapalani Velachery Thuraipakkam Marina Mall (Egattur) Shift Timing: 11:00 AM 8:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend shifts Work experience with a leading restaurant brand Apply Now Turn your weekends into an earning opportunity!

We are looking for an experienced Accommodation and Usage Attribute Lead to define, develop, and validate vehicle attributes related to occupant accommodation, ergonomics, usability, and overall user experience. This role ensures that vehicles meet customer expectations for comfort, accessibility, and intuitive use across diverse global markets. Key Responsibilities: Define attribute targets for accommodation, ingress/egress, visibility, reachability, and usability. Lead cross-functional collaboration with design, enginee ring, and HMI teams to ensure attribute integration. Conduct benchmarking and user studies to inform attribute strategies.Develop a nd manage digital and physical validation plans (e.g., CAD assessments, mock-ups, VR, clinics). Ensure compliance with ergonomic sta ndards and regulatory requirements.Support packaging and layout decisions to optimize occupant space and comfort.Drive resolution of attribute-related issues throughout the development cycle.Present findin

As a Physical Design Engineer, you will be responsible for implementing and optimizing physical designs for high-performance VLSI systems. You will work on a wide range of tasks, including synthesis, placement, routing, and timing closure, ensuring that our designs meet stringent power, performance, and area (PPA) requirements. Responsibilities: 1. Perform RTL-to-GDSII implementation, including synthesis, floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off. 2. Optimize designs for PPA while adhering to design constraints and manufacturing requirements. 3. Conduct static timing analysis (STA), power analysis, and physical verification (DRC/LVS). Collaborate with RTL design, verification, and DFT teams to ensure seamless integration and sign-off. 4. Debug and resolve issues related to timing, signal integrity, and power. 5. Drive closure of physical verification issues such as DRC, LVS, and ERC. 6. Implement low-power design techniques, including power gating, multi-Vt optimization, and dynamic voltage scaling. 7. Work closely with EDA tool vendors to improve design flows and methodologies. 8. Generate and maintain comprehensive documentation for physical design flows and guidelines. Requirements: 1. Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. 2. 3-10 years of experience in physical design for VLSI systems. 3. Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, or Mentor Calibre. 4. Strong knowledge of STA tools like PrimeTime, Tempus, or equivalent. 5. Experience with advanced process nodes (e.g., 7nm, 5nm, or below) and FinFET technologies. 6. Expertise in low-power design techniques and methodologies. Solid understanding of DRC/LVS and parasitic extraction. 7. Familiarity with scripting languages (Python, TCL, Perl) for flow automation. 8. Excellent problem-solving skills with the ability to debug and resolve complex physical design challenges. 9. Strong communication and collaboration skills to work effectively in cross-functional teams. Preferred Qualifications: 1. Hands-on experience with hierarchical design flows and methodologies. 2. Knowledge of 3D IC and advanced packaging technologies. 3. Familiarity with machine learning or AI applications in physical design optimization. 4. Exposure to hardware security aspects in physical design.