213 Timing Closure Jobs - Page 6

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Applied Materials is the leader in materials engineering solutions to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. Our innovations make possible„¢ the technology shaping the future. To achieve this, we employ some of the best, brightest, and most talented people in the world who work together as part of a winning team. Key Responsibilities Expertise in PDK enablement and library validation/automation. Hands-on experience with LVS/Parasitic extraction/standard cell characterization flows and methodologies Design/System level experience with DTCO and PPA analysis Hands-on expertise in TCL, Python, make and shell scripting Broad understanding of system design (product architecture, packaging, SRAM, DRAM, etc.) is a plus Strong understanding of the RTL2GDS concepts and methodology and experience with Synopsys/Cadence physical design tools (Fusion Compiler/Innovus) Knowledge of standard cell architecture and design tradeoffs with respect to PPA Proactively identify and act on new trends or developments in future technology nodes Ability to implement solutions and troubleshoot complex problems with limited or no supervision in area of expertise Creative thinking and ability to look ahead and anticipating future technology innovations/issues Ability to collaborate with internal stakeholders, customers and vendors Collaborate/participate in discussions to solve interdisciplinary technical issues in a cross-functional team environment Mandatory - PDK, DRC, LVS, Python, Physical Design Functional Knowledge Demonstrates depth and/or breadth of expertise in own specialized discipline or field Business Expertise Interprets internal/external business challenges and recommends best practices to improve products, processes or services Leadership May lead functional teams or projects with moderate resource requirements, risk, and/or complexity Problem Solving Leads others to solve complex problems; uses sophisticated analytical thought to exercise judgment and identify innovative solutions Impact Impacts the achievement of customer, operational, project or service objectives; work is guided by functional policies interpersonal Skills Communicates difficult concepts and negotiates with others to adopt a different point of view Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

Who We Are Applied Materials is the global leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. We design, build and service cutting-edge equipment that helps our customers manufacture display and semiconductor chips- the brains of devices we use every day. As the foundation of the global electronics industry, Applied enables the exciting technologies that literally connect our world- like AI and IoT. If you want to work beyond the cutting-edge, continuously pushing the boundaries of"science and engineering to make possible"the next generations of technology, join us to Make Possible® a Better Future. What We Offer Location: Bangalore,IND At Applied, we prioritize the well-being of you and your family and encourage you to bring your best self to work. Your happiness, health, and resiliency are at the core of our benefits and wellness programs. Our robust total rewards package makes it easier to take care of your whole self and your whole family. Were committed to providing programs and support that encourage personal and professional growth and care for you at work, at home, or wherever you may go. Learn more about our benefits . Youll also benefit from a supportive work culture that encourages you to learn, develop and grow your career as you take on challenges and drive innovative solutions for our customers."We empower our team to push the boundaries of what is possible"”while learning every day in a supportive leading global company. Visit our Careers website to learn more about careers at Applied. Key Responsibilities: Understand and Enhance Existing FPGA Architecture: Analyze and comprehend current FPGA designs and architectures. Identify areas for improvement and optimization within existing systems. Implement enhancements to improve performance, efficiency, and functionality. Develop Modular Architectural Approaches with a Focus on Testability: Design modular FPGA architectures to facilitate ease of testing and integration. Ensure that new designs are scalable and maintainable. Incorporate best practices for testability into the design process. Collaborate with Software, Hardware, and System Teams: Work closely with cross-functional teams to ensure FPGA designs meet system requirements. Communicate effectively with software developers, hardware engineers, and system architects. Participate in design reviews and provide feedback to other team members. Develop RTL Code, Perform Logic Synthesis, Timing Analysis, and Timing Closure: Write and optimize RTL (Register Transfer Level) code for FPGA designs. Conduct logic synthesis to translate RTL code into gate-level designs. Perform timing analysis to ensure designs meet timing constraints and achieve timing closure. Create Test Benches and Simulation Tools for Verification: Develop comprehensive test benches to verify the functionality and performance of FPGA designs. Utilize simulation tools to test and validate designs before implementation. Debug and resolve issues identified during the verification process. Troubleshoot and Improve Building Block Modules: Identify and resolve problems in FPGA modules to enhance performance and reliability . Continuously improve the design and functionality of FPGA building blocks. Document troubleshooting processes and solutions for future reference. Qualifications: Bachelors or Masters degree in Electrical Engineering, Computer Engineering, or a related field. Proficiency in hardware description languages such as VHDL or Verilog. Experience with FPGA design tools and platforms (e.g., Xilinx Vivado, Altera Quartus). Strong understanding of digital design principles and practices. Excellent problem-solving skills and attention to detail. Ability to work collaboratively in a team environment and communicate effectively with diverse teams. Preferred Skills: Experience with high-speed digital design and signal processing. Familiarity with scripting languages (e.g., Python, Tcl) for automation tasks. Knowledge of system-level integration and testing methodologies. Experience in low-power design techniques and optimizations. The role of an FPGA engineer is dynamic and requires a strong technical foundation, creativity in design, and the ability to work well within a multidisciplinary team to develop cutting-edge digital systems. Top of Form Additional Information Time Type: Full time Employee Type: Assignee / Regular Travel: Yes, 10% of the Time Relocation Eligible: Yes Applied Materials is an Equal Opportunity Employer. Qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, ancestry, religion, creed, sex, sexual orientation, gender identity, age, disability, veteran or military status, or any other basis prohibited by law.

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Bangalore Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Bangalore Work Locations: Lulu Mall (Rajajinagar) Phoenix Marketcity (Whitefield) Shift Timing: 12:00 PM 5:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 3,000 3,500 Work 4 5 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Opportunity to work with a popular restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Interfacing with customers regarding digital reference flows, including Synthesis Floorplanning Clock tree synthesis Power planning Place and route Timing closure Creating baseline flows to be used by customers as starting point for digital implementation Performing digital place and route and sign-off on small customer designs Creating documentation PPA optimization Bachelor s degree with at least 1-3 years of design/EDA experience or Master s degree. Strong knowledge of Digital Design Fundamentals, Semiconductor Fundamentals and Static Timing Analysis Prior experience with ASIC digital implementation flows and EDA tools is required; Experience with advanced nodes (7nm and below) preferred. Good programming knowledge in Unix, Shell scripting, perl and importantly TCL Strong customer-facing communication and problem solving skills Strong personal drive for continuous learning and expanding professional skill sets Excellent verbal and written communication skills Familiar with EDA tool operation, setup and debug: Digital: Genus, Innovus, Tempus, Voltus, etc We re doing work that matters. Help us solve what others can t.

Role & responsibilities Physical Design Engineer (PD/STA/Synthesis) Must-Haves: •Tools: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime for STA •Flow Experience: •Floorplanning •Power planning •Placement •Clock Tree Synthesis (CTS) •Routing •Physical Verification (DRC/LVS) •Timing Closure •Knowledge of: •Low-power design (UPF/CPF) •ECOs •IR Drop, EM Analysis •STA constraints and timing analysis Nice-to-Haves: •Experience with block-level and/or full-chip PD •Familiarity with scripting (Tcl, Perl, Python)

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Chennai Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Chennai Work Locations: T. Nagar Nungambakkam Vadapalani Velachery Thuraipakkam Marina Mall (Egattur) Shift Timing: 11:00 AM 8:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Support kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend shifts Work experience with a leading restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Kolkata Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Kolkata Work Locations: Salt Lake (City Centre Mall) Park Street (Opposite The Park Hotel) New Town (Axis Mall) Howrah (Avani Riverside Mall) Gariahat (Near Mukti World Mall) Shift Timing: 12:00 PM 9:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Assist kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend opportunity Experience working with a reputed restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

SUMMARY Part-Time Weekend Job Join Barbeque Nation’s Team in Mumbai Job Role: Weekend Supporting Staff Company: Barbeque Nation Location: Mumbai Work Locations: Andheri West (Infinity Mall) Lower Parel (High Street Phoenix Mall) Thane (Viviana Mall) Malad (Inorbit Mall) Vashi (Raghuleela Mall) Shift Timing: 12:00 PM 9:00 PM Work Days: Saturday and Sunday Estimated Monthly Earnings: 5,000 7,000 Work 9 hours and earn extra income every weekend Key Responsibilities: Assist kitchen and floor staff Serve starters, beverages, and non-vegetarian items (including chicken) Maintain cleanliness in service and dining areas Ensure smooth dining operations Requirements: No prior experience required (orientation provided) Must be energetic, disciplined, and customer-friendly Comfortable handling non-vegetarian food Age 18+ and available on both days What We Offer: Quick payouts Flexible part-time weekend work Work experience with a leading restaurant brand Apply Now Make your weekends productive with Barbeque Nation!

Primary & Mandatory Skill: Python, Docker/Kubernetes Level: SA Client Round (Yes/ No): No Location Constraint if any : No Shift timing: 2-11pm JD: Good hands in Python scripting Experience in Docker & Kubernetes

Primary/ Mandatory skills : Extensive experience in “Chef IT Automation” Secondary skills : Good knowledge and experience in DevOps Level: SA RR : Maintain a consistent terraform script when compared to existing cloud resources Chef version update: version 14 to version 18 Crowdstrike, Qualys and Splunk integration for Ecommerce workloads Packer AMI creation for Windows Core and CentOS Stream 9 Terraform version update Collaborate with DB team for “CentOS version + DB version” update project Test every change made. Work with DevOps, SRE and development teams for testing. Document and publish the changes, and projects undertaken. Client Round (Yes/ No): Yes Location Constraint if any : No Constraints Shift timing: IST 1330Hrs – 2330Hrs

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll Do: Perform hands-on physical design and physical verification tasks across projects in advanced process nodes. Manage project-specific ASIC development flow setup and maintenance. Physical design tasks include floor-planning, place and route, CTS, timing closure, IR/EM analysis, and LEC for block level and full chip flat/hierarchical designs. Coordinate full chip physical design and verification activities. Physical verification tasks include creating setup and scripts for DRC, LVS, DFM, Antenna and density checks, report generation, analysis, debugging, and implementing fixes in the physical design database. Ensure correct IP and pad-ring integration in block and flat designs. Mentor junior PD/PV team members and oversee their tasks. You will be reporting to ASIC Design Director. What Youll Need: Minimum 12+ Years of experience in ASIC/ SoC Physical Design. Skills - have working experience in advanced FinFET node designs. Experience with Cadence PnR/STA tools and Calibre; good scripting/automation skills is a must. Education - B. Tech /M. Tech in Electronics Engineering. "We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.

About Tessolve Tessolve is a leading engineering solutions provider, enabling silicon and system companies to accelerate their products to market. With capabilities across silicon design, test engineering, and embedded solutions, we are an end-to-end partner for semiconductor companies globally. Job Description We are looking for a Senior STA Engineer with 8 10 years of hands-on experience in Static Timing Analysis for complex SoC/ASIC designs at advanced technology nodes (7nm, 5nm, or below). The ideal candidate should be technically sound, self-driven, and capable of independently owning STA tasks from RTL to signoff. Key Responsibilities Perform full-chip and block-level static timing analysis using tools such as Primetime , Tempus , or equivalent. Develop and validate timing constraints (SDC) for functional and DFT modes. Drive timing closure in collaboration with physical design, synthesis, and DFT teams. Analyze and resolve setup/hold, transition time, and cross-corner violations. Perform timing ECOs and timing model generation for hierarchical designs. Support signoff flows, including OCV, AOCV, POCV , and SI/IR-drop aware timing. Script automation in TCL/Perl/Python to improve STA efficiency. Participate in customer calls and support project execution in a global delivery model. Required Skills Strong fundamentals in STA, CMOS timing, and VLSI design concepts. Expertise in timing constraints, derating, and ECO implementation. Experience in hierarchical and flat STA at chip-level. Hands-on with timing sign-off methodologies across multiple PVT corners. Familiarity with clock domain crossing (CDC) and false path/multicycle path analysis. Working knowledge of physical design flows is a plus. Good communication and leadership skills. Educational Qualifications B.E/B.Tech or M.E/M.Tech in Electronics or related discipline. Nice to Have Experience with advanced technology nodes (5nm/3nm) . Familiarity with low-power design techniques (UPF) . Customer interaction and project leadership experience.

FELLOW SILICON DESIGN ENGINEER THE ROLE: We are looking for a Fellow-level Engineer to join our team to develop world-class Server products . In this role you will be engaged with Server SOC architects, micro architecture, RTL, CAD/Methodology, and internal stakeholders to define end to end Power Optimization Methodology, PVT Corners, timing methodology that require technically analyzing, defining usage cases, and mapping across a broad spectrum of technologies to ensure a well-defined methodology to achieve PPA uplift across a spectrum of Server products. In this role you will provide a cohesive technical vision of the required PPA improvement methodology. THE PERSON: You will possess very strong problem-solving skills and bring broad experience in methodology, with a strong, self-motivated work ethic. KEY RESPONSIBILITIES: Define and drive PPA uplift methodologies for Server products Develop and deploy end to end power optimization methodology for Physical Design Implementation Define PVT corners, device frequency scaling, frequency targets for next generation Servers in leading foundry technology nodes Deep knowledge of micro architecture, power optimization methodologies, Synthesis, Place and Route, Top level Clocking structure and Timing closure . Hands-on experience in closing very high-frequency designs Proven track record of tapeout experience with leading technology nodes like 10nm, 7nm and 5nm Experience driving Physical Implementation methodology Excellent communication skills and strong collaboration across multiple business units PREFERRED EXPERIENCE: 20+ years experience in SOC Physical Design Implementation, Methodology, Signoff and TapeOut In-depth experience and deep conceptual understanding of domains like Full Chip Floorplanning, CTS, PnR, STA, PV, EMIR, Low power design, Logic synthesis, LEC/Formality, VSI, etc. Presentations, Papers and proven innovations, Patents in these domains is a strong plus Forward looking and dependable techincal leader who proactively identifies and resolves issues and roadblocks before they become bottlenecks or showstopper. Experience working seamlessly across engineering disciplines and geographies to deliver excellent results ACADEMIC CREDENTIALS: Bachelors or Masters degree in computer engineering/Electrical Engineering #LI-SK5 Benefits offered are described: AMD benefits at a glance .

Video Editing Intern Jaipur (In-office) - Digi Spheres Video Editing Intern Jaipur (In-office) Job Summary: We re seeking a creative and technically skilled Video Editing Intern to bring our content to life. You ll be responsible for editing short-form and long-form content for various platforms. Key Responsibilities: Edit videos, reels, and motion graphics for client campaigns Add music, text, transitions, and other visual effects Optimize content for Instagram, YouTube, and other platforms Collaborate with content creators and strategists for ideation Requirements: Proficiency in Premiere Pro, Final Cut Pro, or CapCut Strong sense of pace, timing, and narrative flow

Sr. Staff Digital Engineer in Bangalore, India Sr. Staff Digital Engineer Description Millions of people experience Synaptics every day. Our technology impacts how people see, hear, touch, and engage with a wide range of IoT applications -- at home, at work, in the car or on the go. We solve complex challenges alongside the most influential companies in the industry, using the most advanced algorithms in areas such as machine learning, biometrics, and video processing, combined with world class software and silicon development. Overview Synaptics is looking for a Sr. Staff Digital Engineer, WLAN MAC to join our dynamic and growing WPD organization. You will be responsible for MAC architecture / design / implementation in the Wi-Fi 6/7 for IoT market. You will provide technical expertise in the latest design methodologies. You will provide expertise in Wi-Fi domain. Your responsibility includes coordinating with multiple teams on specification for design, architecture, timing closure. This position reports to the Director, Silicon Engineering. Responsibilities & Competencies Job Duties Define WiFi MAC architecture from Standard Technically lead team on design, methodology Design optimization, enhancement to cater to the need of power and area target Guide and lead the team through digital design, RTL implementation, Lint, CDC checks, timing closure, verification and coverage closure, ECO implementation and chip productization debug Work with Systems/SW team in performance analysis and propose IP enhancements Collaborate with DV team on test plans, closure of code, and functional coverage Support post-silicon bring up activities of the products working with design, product evaluation and applications engineering team Competencies Strong Digital design and Wireless technology fundamentals Conversant with Wifi 802.11 Standard, networking protocol like L3/L4 protocol Strong fundamentals in CPU architecture, Host interfaces like (PCIe, SDIO, UART etc.), Bus interconnects specially AXI/ACE/AHB/APB. Knowledge in Lint, CDC, timing constraints, synthesis, power analysis Ability to communicate complex, interactive design concepts clearly Proactive, self-starter, able to work independently in a fast-paced environment to complete projects on time with minimal guidance Well organized with strong attention to detail; proactively ensures work is accurate Positive attitude and work ethic; unafraid to ask questions and explore new ideas Resourceful and able to solve complex problems through adaptation of existing technology and investigation of new technology with a solid understanding of product architecture Analytical and able to make informed decisions based on experience Sets clear expectations and objectives, and brings parties together to drive key initiatives Ability to work within a diverse team and mentor developing team members Excellent verbal and written communication Qualifications (Requirements) Bachelors or masters degree in computer engineering, Communication, Electrical/Electronic Engineering or related field or equivalent 12+ years of experience in IP design Proven experience in designing digital circuits for wireless product Understanding of digital IC design flow (design, verification, synthesis, HW/SW co-working) Familiar with at least one of the followings: Wi-Fi, Bluetooth, MAC architecture, and Security engine architecture Experience with tapeout of new product No travel required

Here's the information about the PrimeTime role, formatted for clarity and impact: Driving increased usage of the Synopsys PrimeTime tool through both pre-sale and post-sale activities. Conducting competitive benchmarks and evaluations to demonstrate the superiority of our products. Articulating technical advantages to customer design teams and management. Providing customer training and tapeout support to ensure successful product implementation. Collaborating with users, R&D, marketing, and sales teams to enhance product features and usability. Engaging in advanced collaboration initiatives to drive continuous product improvements. The Impact You Will Have Increasing the adoption and integration of PrimeTime, leading to higher customer satisfaction and retention. Enhancing customer design processes through expert guidance and support. Contributing to the development of superior product features based on customer feedback and industry trends. Strengthening Synopsys market position through effective pre-sale evaluations and demonstrations. Facilitating successful tapeouts and design completions for customers using PrimeTime. Driving innovation within Synopsys by collaborating with multiple teams and stakeholders. What You'll Need BSEE with 5+ years of experience or MSEE with 3+ years of experience in related fields. Domain knowledge in Static Timing Analysis (STA) and expertise in timing closure and ECO flows . Experience with Synopsys STA tools , particularly PrimeTime. Understanding of timing corners, modes, process variations, and signal integrity issues. Strong knowledge of TCL scripting and familiarity with synthesis, physical design, and extraction methodologies. Who You Are A proactive and detail-oriented professional with strong technical acumen. An effective communicator with excellent verbal and written communication skills. A collaborative team player who thrives in customer-facing roles. An innovative thinker who is always looking for ways to improve processes and products. A dedicated individual with a strong sense of ownership and responsibility.

Description We are seeking a highly skilled ASIC Physical Design, Sr Staff Engineer to join our team in India. In this role, you will be responsible for the physical design and implementation of high-performance ASICs, collaborating closely with cross-functional teams to ensure successful project delivery. Responsibilities Design and implement physical layouts for ASIC designs. Conduct place and route activities to meet timing and area requirements. Perform timing analysis and optimization to ensure high-performance ASICs. Collaborate with RTL designers to ensure design feasibility and manufacturability. Utilize EDA tools for physical design tasks such as Cadence, Synopsys, or Mentor Graphics. Conduct DRC/LVS checks and ensure design compliance with specifications. Support the verification team in physical design verification activities. Participate in design reviews and provide feedback for design improvements. Skills and Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 2-7 years of experience in ASIC physical design or related roles. Strong knowledge of ASIC design flow and methodologies. Proficiency in using EDA tools for physical design (e.g., Cadence, Synopsys, Mentor Graphics). Experience with place and route, timing closure, DRC/LVS checks, and physical verification. Familiarity with scripting languages (e.g., Perl, Tcl, Python) for automation of design tasks. Understanding of semiconductor manufacturing processes and design for manufacturability (DFM). Strong problem-solving skills and attention to detail.

* Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. * Collaborate with cross-functional teams to achieve design goals. * Close the design to meet timing, power, and area requirements. * Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. * Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure. Preferred technical and professional experience Automation skills in PYTHON, PERL , and/or TCL

Position - ASIC Engineer (5+ Years Floor planning , Place and route , Formal verification , Timing closure , Perl / Python / Scripting ) Our creative and versatile Physical Design team in Bangalore, India. As a member of this team you will be involved in creating next generation innovative networking chips in advanced process node. You will drive the backend process through the entire RTL 2 GDS Implementation flow including hierarchical floor planning, place & route, timing closure, power integrity, static timing verification, physical verification and equivalence checks, with special focus on performance & die size optimization. What you will do: Analyzes current generation quality and efficiency gaps to identify proper incremental or evolutionary changes to the existing physical design related Tools, Flow and Methodology. Work closely with various teams such as physical design, RTL, DFT, tool/flow owners, and EDA vendors to improve physical design methodologies. Good understanding of different CTS strategies and providing the feedback to Implementation Team. As member of physical design team, drive methodologies and best known methods to streamline and automate physical design work. STA setup, convergence methodology, reviews and sign-off for Multi-Mode and Multi-corner designs. Good at Timing ECO Implementation strategy development/convergence. Should have an experience in enabling the Tweaker/Primetime based ECO flows. Work on Automation scripts within STA tools for Methodology development Excellent debugging skills in implementation issues and ability to produce creative solutions. Evaluate multiple timing methodologies/tools on different designs and technology nodes. Good scripting skills (TCL/SHELL/PERL/Python) is a MUST Who you are: You are an ASIC engineer with 6+ years of related work experience with a broad mix of technologies including: All aspects of ASIC Physical implementation including Floor planning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration. Hierarchical design implementation approach, Timing closure, physical convergence. Power Integrity Analysis Experience with large designs (>100M gates) utilizing state of the art sub 16/14/7/5/3nm technologies. Familiarity with various process related design issues including Design for Yield and Manufacturability, multi-Vt strategies. You should also have hands on experience with the following Tool sets Floor planning and P&R tools: Cadence Innovus & Synopsys ICC2 Synthesis Tools: Synopsys DC/FC Formal Verification : Synopsys Formality and Cadence LEC Static Timing verification: Primetime-DMSA Power Integrity : Apache Redhawk Physical Design Verification Synopsys ICV, Mentor Calibre Scripting: TCL, Perl is required; Python is a plus Bachelor's degree in Telecommunications Engineering, Computer Science, MIS, or related experience. We are looking for high achievers who love challenging environment to join our team.

We are seeking a highly skilled and motivated STA Synthesis Engineer to join our offshore development teams . The ideal candidate will have expertise in static timing analysis (STA) to ensure the timing integrity of digital integrated circuits. Develop and execute timing constraints, ensuring compliance with design specifications and performance goals. Prepare detailed STA reports, including analysis and recommendations for improvements. Provide training and support to junior STA engineers and team members Role & Responsibilities : - Timing Constraint Generation : Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design. - STA Setup : Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions. - Timing Analysis : Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations). - Clock Domain Crossing ( CDC ) Analysis : Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues. - Multicycle Paths ( MCP ) and False Paths : Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints. - Timing Closure : Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues. - Clock Tree Synthesis ( CTS ) : Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter. - Post-Layout STA : Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure. - Timing Margins : Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation. - Report Generation : Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization. - Cross-Functional Collaboration : Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues. - Methodology Development : Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy. NOTE : Preferred resources holding valid regional work permits only

PMTS SILICON DESIGN ENGINEER THE ROLE: Should have 15+ years of experience in Physical Design methodologies and Fullchip Design. You have had significant success driving Fullchip Floorplan, Fullchip Place and Route , Fullchip timing. You are meticulous about Power, Performance and Area while driving schedule and managing cost. This senior role will stretch you as you lead Physical Design teams in new directions, network with our world-class, patent-holding think-tank, and negotiate amongst design teams and business unit executives. THE PERSON: You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: Should own and drive the Physical implementation and Full chip timing closure of multiple designs of next gen 3nm (or lower nodes) SOC. Role inovolves interaction with multiple design teams, CAD teams and Tool vendors (on and cross sites) Understand and drive the requirements, define the design implementation methodology, Resource allocation, Scheduling, Resource management and Risk management etc. Ability to learn, make progress and critical times and agility is preferred. Work closely with multiple Design teams for Area , Floorplan refinement and Timing targets PREFERRED EXPERIENCE: Should have 15+ years of experience in Physical Design methodologies , Fullchip Floorplan, Fullchip Place and Route, Fullchip timing signoff closure Automation skills TCL, Perl are must Should have experience with 3nm/2nm design methodology Should have lead team of 15 members and well versed with Tracking, Goal settings and Performance evaluations Excellent communication, management, and presentation skills. Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies ACADEMIC CREDENTIALS: Bachelor s or Master s degree in related discipline preferred

Experienced PD Engineer working on mutliple technology nodes. Design for 40/22nm analog, RF, and mixed/signal circuits will be an added advantage. Perform layout from scratch, modify existing layouts. Create block level floorplans and work within the constraints of higher-level floorplans. Participate in peer and engineering reviews. Provide accurate area and schedule estimates for assigned circuit blocks. Work closely with both design engineers and other layout engineers. Required Experience and Skills We are looking for an experienced person (~10-15 years) who has overall knowledge of PD and takes care of all the flows associated with it. Apart from PnR & Synthesis: Experience with work closer to the front end such as digital modeling, gate level simulations, CDC, LEC, and STA/synthesis. Floor planning: Strategically planning the placement of functional blocks on the chip. Placement and Routing: Optimizing the placement of components and connecting them with wires (routing). Timing Closure: Ensuring the chip meets timing requirements (ensuring signals arrive at the correct time). Power Integrity: Managing power distribution and ensuring the chip operates reliably. Verification: Checking the layout for errors and ensuring it meets design rules. ECOs: Implementing design changes (ECOs) to fix issues identified during verification. Flow Development: Participating in developing and improving physical design methodologies and CAD tools. Job Segment: Front End, Design Engineer, Drafting, Network, CAD, Technology, Engineering

Key Responsibilities: Floor planning: Develop and optimize floorplans for ASIC designs, ensuring optimal placement of cores, macros, and I/O cells while considering performance and manufacturability. Place & Route (P&R): Perform place-and-route tasks, optimizing for timing, power, and area, ensuring congestion-free routing and maximizing PPA (Performance, Power, Area). Static Timing Analysis (STA): Carry out static timing analysis to identify violations and work on techniques for timing closure such as resizing, retiming, or re-optimization. Power Analysis & Optimization: Perform power analysis, targeting low-power designs using techniques such as clock gating, power gating, and low-power state optimization. Signal Integrity & Noise Analysis: Perform signal integrity analysis to avoid noise and crosstalk in the design. Design Rule Check (DRC) and Layout vs. Schematic (LVS): Run DRC and LVS checks to ensure the layout adheres to manufacturing rules and matches the schematic. RC Extraction: Perform parasitic extraction and analyze RC effects to ensure the design functions at the required operating frequencies. Verification: Participate in the final sign-off processes for physical design and support tape-out efforts, ensuring all design specifications are met. Collaboration: Work closely with design, verification, and CAD teams to troubleshoot and resolve any design-related issues. Documentation: Maintain clear documentation throughout the physical design flow for ease of understanding and for future reference. Qualifications: Education: Bachelors/Masters degree in Electronics/Electrical Engineering or a relevant degree. Experience: Minimum 3-14 years of experience in ASIC physical design. Proficiency in place and route (P&R), static timing analysis (STA), power analysis , and DRC/LVS checks. Experience with tools like Cadence Innovus , Synopsys IC Compiler , or Mentor Graphics for physical design. Knowledge of advanced process nodes (e.g., 7nm, 5nm) is a plus. Technical Skills: Proficiency in digital design concepts and semiconductor process flows. Strong knowledge of timing optimization techniques and power optimization strategies. Familiarity with parasitic extraction and signal integrity analysis. Ability to script in languages like Tcl , Python , or Perl to automate tasks. Preferred Skills: Experience with 3D IC design or FinFET technologies. Familiarity with full-chip tape-out procedures. Exposure to machine learning techniques in physical design optimization will be added advantage. Personal Attributes: Strong problem-solving and analytical skills. Detail-oriented, with a focus on accuracy and optimization. Excellent communication and collaboration skills, capable of working in a cross-functional team. Ability to manage multiple tasks in a fast-paced environment.

Collaborate with the design team for the implementation of various hard IPs and the SoC top level. Lead the top-level implementation of SoC designs, including IO ring integration. Utilize Synopsys Fusion Compiler for physical and WLM synthesis. Perform timing analysis and resolve timing issues related to implementation. Conduct DFT insertion and ensure robust design for testability. Execute place and route flows using Cadence Innovus and Synopsys Fusion Compiler. Manage chip-level and block-level design implementation. Design and analyze IO rings. Implement FlipChip SoC designs, including RDL routing. Ensure timing and design signoff, including STA, LVS, and DRC. Utilize tools such as Synopsys Design Compiler, DFT Compiler, PrimeTime, Cadence Innovus, and Mentor Graphics Calibre for various implementation tasks. Interested candidates can share their resumes to shubhanshi@incise.in

The Opportunity Were looking for the Wavemakers of tomorrow. What Youll do: Responsible for front end implementation of IPs which includes Synthesis, LEC, CLP. Collaborate with designers and PNR teams to achieve design closure with focus on Quality Ability to debug and resolve technical issues. Hands on functional ECO generation using Candence conformal LEC Should be able to provide good support to Gate level simulations (GLS) team Overall, should have good knowledge on RTL so as to understand all synthesis related warnings. What Youll Need: 5-7 years experience in physical aware synthesis. Self-motivated complete understanding of timing constraints, low power aspects and concepts of DFT Experienced in synthesis, LEC, CLP and timing closure Should have handled blocks with complex designs, multiple high frequency clocks and complex clocking. scripting and automation experience is a must. We have a flexible work environment to support and help employees thrive in personal and professional capacities" As part of our commitment to the well-being and satisfaction of our employees, we have designed a comprehensive benefits package that includes: Competitive Compensation Package Restricted Stock Units (RSUs) Provisions to pursue advanced education from Premium Institute, eLearning content providers Medical Insurance and a cohort of Wellness Benefits Educational Assistance Advance Loan Assistance Office lunch & Snacks Facility Equal Employment Opportunity Statement Alphawave Semi is an equal opportunity employer, welcoming all applicants regardless of age, gender, race, disability, or other protected characteristics. We value diversity and provide accommodations during the recruitment process.