600 Timing Closure Jobs - Page 9

You should be a PNR Lead with over 8 years of experience, based in Bangalore. Your role will involve handling Full chip PnR tasks such as timing, congestion, and CTS issues, with an understanding of IO ring, package support, and multi-voltage design. It is crucial to have a deep understanding of synthesis, place & route, CTS, timing convergence, IR/EM checks, and signoff DRC/LVS closure. Your responsibilities will include independently planning and executing all aspects of physical design, such as floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, and DFM. You must have experience participating in all design stages including floor planning, placement, CTS, routing, physical verification, and IREM. Furthermore, your expertise should cover timing closure methodologies, DRC, LVS, ERC, and PERC rule files for lower tech node layout verification. Experience in lower tech nodes (<7nm) is required, along with strong automation skills in PERL, TCL, and EDA tool-specific scripting. You should be capable of taking complete ownership of a Block/sub-system throughout the execution cycle and possess out-of-the-box thinking to meet tighter PPA requirements.,

You are a Senior Physical Design Engineer with at least 6 years of experience, and your primary responsibility will be to lead the physical implementation of advanced semiconductor projects. Your role is crucial in shaping the silicon realization of cutting-edge designs, ensuring successful integration from RTL to tape-out. Your responsibilities include providing technical guidance and mentoring to physical design engineers, interfacing with front-end ASIC teams to resolve issues, and working on low power design techniques such as Voltage Islands, Power Gating, and Substrate-bias. You will also be responsible for timing closure on DDR2/DDR3/PCIE interfaces and have excellent communication skills. Your strong background in ASIC Physical Design, including floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure, will be essential. You should have extensive experience and detailed knowledge in Cadence, Synopsys, or Magma physical Design Tools, as well as expertise in scripting languages like PERL and TCL. Additionally, you should have a strong Physical Verification skill set and experience in Static Timing Analysis using Primetime or Primetime-SI. In terms of required skills, you should be proficient in top-level floor planning, PG Planning, partitioning, placement, timing optimization, SI aware routing, and ECO tasks. Experience with 65nm or lower node designs with advanced low power techniques is necessary. Proficiency in EDA tools for floor planning, place and route, clock tree synthesis, and physical verification is also required. A Bachelors or Masters degree in electronics engineering or a related field is essential. Desired skills include familiarity with EDA tools such as Cadence Innovus, Synopsys ICC, and Mentor Calibre, as well as knowledge of low power design techniques and implementation.,

As a Senior RTL Design Engineer with 3-5 years of experience, you will be based in Hyderabad. You will be required to demonstrate strong RTL (Verilog/System Verilog) skills with a focus on IP development. Your responsibilities will include verifying designs by creating simple testbenches, as well as possessing a solid foundation in logic synthesis and timing closure concepts. Additionally, you should have a good understanding of SoC architecture, AXI bus protocols, and hardware debug processes. Experience with Xilinx FPGAs, Vivado tool flows, and micro-architecture development will be considered a plus. If you meet the specified requirements and are interested in this opportunity, please submit your updated resume to janagaradha.n@acldigital.com.,

SILICON DESIGN ENGINEER 2 THE ROLE: The focus of this role is to execute the front end implementation of sub-blocks or IP. This involves ownership of synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure. Co-ordinate with design team and PNR teams. KEY RESPONSIBILITIES: Responsible for front end implementation of IPs which includes synthesis, LEC, CLP, prelayout STA and postlayout STA/Timing closure Collaborate with designer and PNR teams to achieve closure. Execute as per schedule. Complete quality delivery for synthesis and timing closure. Debug and resolve technical issues PREFERRED EXPERIENCE: Experienced in synthesis and timing closure Good to have experience in LEC, CLP Have handled blocks with complex designs, high frequency clocks and complex clocking complete understanding of timing constraints, low power aspects and concepts of DFT Have debug experience to solve issues. scripting and automation ACADEMIC CREDENTIALS: Bachelors with 2 years of experience or Masters degree with 1 years of experience in Electrical Engineering #LI-RP1

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements : Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Qualcomm India Private Limited is looking for a Hardware Engineer with over 12 years of experience in SoC design. You should have a strong understanding of AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. Knowledge of memory controller designs and microprocessors would be an added advantage. In this role, you will be responsible for constraint development and timing closure, working closely with SoC verification and validation teams for pre/post Silicon debug. Hands-on experience in Low power SoC design is required, along with expertise in Synthesis and understanding of timing concepts for ASIC. You should also have experience in Multi Clock designs and Asynchronous interface. Familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime is necessary. Minimum qualifications include a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or related field with 6+ years of Hardware Engineering experience, or a Master's degree in the same field with 5+ years of experience, or a PhD with 4+ years of experience. If you are an individual with a disability and need accommodation during the application/hiring process, Qualcomm is committed to providing an accessible process. For reasonable accommodations, you may contact disability-accommodations@qualcomm.com. Qualcomm expects all employees to adhere to applicable policies and procedures, including security and confidentiality requirements. Please note that Qualcomm's Careers Site is for individuals seeking jobs at Qualcomm. Staffing agencies and individuals represented by agencies are not authorized to use this site. Unsolicited submissions from agencies will not be accepted. For more information about this role, please contact Qualcomm Careers.,

The job requires a deep understanding of protocols such as USB, PCIE, MIPI, JEDEC, I2C, and SPI. You will be responsible for designing and verifying RTL code for high-speed SerDes digital blocks. Your communication skills, both verbal and written, should be excellent. Experience in synthesizing complex SoCs block/top level and writing timing constraints is necessary. You should also have experience in formal verification RTL-to-netlist and netlist-to-netlist with DFT constraints, as well as post-layout STA closure and timing ECOs. Previous work in technology nodes of 45nm and below is preferred. Your mandatory skills should include Timing Closure, STA, ECOs, Synthesis, and SDC. A qualification of BE/B.Tech in VLSI/ECE is required. You should have at least 3 years of experience in the verification of analog mixed signal blocks. Proficiency in tools such as Cadence AMS tools, Verilog, VerilogA, and VAMS languages is essential. For any career-related inquiries or applications, please reach out to hr@terminuscircuits.com.,

Qualcomm India Private Limited is a leading technology innovator that strives to enable next-generation experiences and drive digital transformation for a smarter, connected future. As a Qualcomm Hardware Engineer, your responsibilities will include planning, designing, optimizing, verifying, and testing electronic systems. This involves working on circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment, packaging, test systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and develop innovative solutions. To qualify for this position, you should hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field along with 4+ years of Hardware Engineering experience. Alternatively, a Master's degree with 3+ years or a PhD with 2+ years of relevant work experience would be considered. We are seeking bright ASIC design engineers with strong analytical and technical skills to be part of a dynamic team responsible for delivering Snapdragon CPU design for Mobile, Compute, and IOT markets. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be involved in creating design experiments, conducting PPA comparison analysis, and collaborating closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Additionally, developing Place & Route recipes for optimal PPA, tabulating metrics results for analysis, and contributing to the ASIC flow with low power, performance, and area optimization techniques are crucial aspects of this role. The ideal candidate should have 10-15 years of High-Performance core Place & Route and ASIC design Implementation work experience. Proficiency in Place & Route with FC or Innovus, experience with STA using Primetime and/or Tempus, and strong problem-solving skills are preferred qualifications. Knowledge in constraint generation and validation, power domain implementation, formal verification, scripting languages like Perl/Tcl, Python, C++, as well as exposure to Verilog coding and CPU micro-architecture will be advantageous. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact disability-accommodations@qualcomm.com. The company's work environment is inclusive and supportive of individuals with disabilities. Applicants should adhere to all relevant policies and procedures, including security measures and confidentiality of company information. Qualcomm does not accept unsolicited resumes or applications from staffing agencies. For more information about this role, please reach out to Qualcomm Careers.,

You will be responsible for executing block level P&R and Timing closure activities, including owning up block level P&R and performing Netlist2GDS on blocks. You will work on the implementation of multimillion gate SoC designs in cutting edge process technologies such as 28nm, 16nm, 14nm, and below. Your role will require strong hands-on expertise in physical design aspects like Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning, Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal Integrity Analysis, Physical Verification (DRC, ERC, LVS), DFM, and DFY, and Tapeout. You should have expertise in analyzing and converging on crosstalk delay, noise glitch, and electrical rules in deep submicron processes, along with an understanding of process variation effects. Experience in variations analysis/modeling techniques and convergence mechanisms would be a plus. Proficiency in Synopsys ICC2 and PrimeTime physical design tools is essential for this role. Additionally, skill and experience in scripting using Tcl or Perl are highly desirable. Qualifications required for this position include a BE/BTech or ME/MTech degree with a specialization in the VLSI domain. The ideal candidate should have 5-10 years of relevant experience in the field.,

As a Physical Design Engineer, you will be responsible for the complex SOC top physical implementation of next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. Your role will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of both complex blocks and full-chip designs. You will be expected to demonstrate expertise in top-level floor planning, including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. A strong understanding of timing, power, and area trade-offs, as well as optimization of PPA, will be crucial for success in this role. The ideal candidate will be a power user of industry-standard tools such as ICC, DC, PT, VSLP, Redhawk, Calibre, and Formality, and should be able to leverage their capabilities effectively. Proficiency in scripting languages like Perl and Tcl, along with a deep understanding of implementation flows, will be essential. Experience with large SOC designs exceeding 20M gates and operating at frequencies above 1GHz is highly desirable. You should possess expertise in block-level and full-chip SDC clean up, Synthesis optimization, Low Power checking, and logic equivalence checking. Familiarity with deep sub-micron designs, particularly at 8nm and 5nm nodes, and associated challenges related to manufacturability, power, signal integrity, and scaling, will be advantageous. Understanding typical SOC issues such as multiple voltage and clock domains, ESD strategies, mixed-signal block integration, and package interactions is also important. You should be well-versed in hierarchical design, top-down design, budgeting, timing, and physical convergence. A good understanding of Physical Design Verification methodology to debug LVS/DRC issues at both chip and block levels is expected. Ideal candidates will have participated in recent successful SOC tape-outs, showcasing their ability to deliver high-quality designs.,

Are you passionate about driving performance at the silicon levelWe are looking for an experienced STA Engineer with 5+ years of expertise in Static Timing Analysis (STA) to join our team! Key Responsibilities: Perform timing analysis, validation, and debug across multiple PVT corners using Tempus Hands-on experience with Tempus DMMMC flow for STA Handle STA setup, convergence, reviews, and signoff for both scan and functional modes Review unconstrained endpoints and analyze detailed timing reports Deep understanding of noise, crosstalk, and OCV effects Experience with block-level and full-chip timing closure at advanced nodes like 22nm, 16nm, 5nm Collaborate with cross-functional teams (design, synthesis, PnR) for smooth closure Scripting knowledge in TCL and Python Prior experience with ADI/Cadence flows and power domain-based designs is a plus

We are seeking a highly experienced Senior Physical Design Engineer with 8+ years of experience in block-level and full-chip physical implementation. The candidate should be proficient in physical design flows and methodologies for advanced technology nodes. Key Responsibilities: Drive physical implementation from RTL to GDSII (floorplanning, placement, CTS, routing) Perform timing analysis, congestion analysis, and physical verification (DRC/LVS) Optimize for performance, power, and area (PPA) Collaborate closely with RTL, STA, DFT, and package teams Own signoff checks (IR drop, EM, Antenna, Crosstalk, etc.) Support tape-out and silicon validation activities Requirements: 8+ years of experience in physical design implementation and signoff Strong hands-on experience with tools like ICC2, Innovus, Primetime, RedHawk, Calibre Solid understanding of timing closure, IR/EM analysis, and power optimization Experience with advanced nodes (7nm, 5nm, etc.) is a plus Good scripting skills (TCL, Perl, Python) for automation Strong communication and teamwork skills

Perform Sub system level floor planning, placement, and routing for high-performance microprocessor design. Collaborate with cross-functional teams to achieve design goals. Close the design to meet timing, power, and area requirements. Implement engineering change orders (ECOs) to rectify functional bugs and timing issues. Ensure the quality and efficiency of the RTL to GDS2 implementation process. Required education Master's Degree Preferred education Bachelor's Degree Required technical and professional expertise 8+ years of industry experience Good knowledge and hands on experience in physical design , timing and methodology which include logic synthesis, placement, clock tree synthesis, routing , post route closure. Should be knowledgeable in physical verification ( LVS,DRC. etc) ,Noise analysis, Power analysis and electro migration . Good knowledge and hands on experience in static timing analysis (closing timing at chip level) good understanding of timing constraints . Should have experience in handling asynchronous timing, multiple corner timing closure.

This role does design and layout of complex VLSI (very large scale integration) circuits using graphic editing tools in cutting edge technological nodes. A major portion of the job is in creation of new physical design data from concepts, partial schematics or a working knowledge of overall requirements. Responsibilities include checking the design integrity with respect to semiconductor ground rules and the logical function of the circuit. Symbolic circuit data (schematics) are converted to physical shapes which represent the semiconductor process. The role ranges from manual shapes and checking tool manipulations to extended team coordination and methodology creation. The employee guides functional objectives or technologies. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-7 Years of relevant experience in Memory Layout design for blocks like Caches, CAMs, Register files, multiport register Files, Compilers etc.Should be in a position to work hands on on memory IPs, help generate and curate new ideas for layout designing, innovate new ways of layout designing, bring leadership into work and have growth mindset and have openmindedness to automation ideas; Excellent communication skills to be able to work with crosssite designers, EDA for development and curation of new tools needed for work. Should be able to understand various memory architechtures, experience in bit cells layouts, compiler layout design; Should have hands on experience in Finfets, GAA etc. Should have had experience in technology nodes below 7nm; LVS, DRC, Antenna, DFM, EM, IR, Methodology check debugging and fixing is a must; Leadership to drive collaborative initiatives with cross teams; SRAM designing experience is an added advantage Preferred technical and professional experience Scripting to ease deliverables is an added advantage. Automation skills in PERL, Python , and/or TCL

You should have at least 8 years of experience in Micro-architecture, SoC development, and full-chip design for multi-million gate SoCs. Your expertise should include a strong understanding of the design convergence cycle, encompassing architecture, micro-architecture, Verification, Synthesis, and timing closure. You should also be adept at managing IP dependencies and planning front-end design tasks effectively. Additionally, you should have experience in designing and developing high-speed serial IO protocols. Your skills should cover the implementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, and low power modes. Experience in CPU, bus fabrics, or coherence/noncoherent NOC domains would be highly desirable for this role.,

As FPGA Architect, you will play a pivotal role in leading the design and development efforts across a range of projects in a dynamic and collaborative environment. Your primary responsibility will involve defining and creating complex FPGA designs for our Test products. Working closely with a diverse team including R&D Project Managers, Product Architects, Solution Teams, FPGA developers, Software Qualification, and Software Engineers, you will contribute to the innovation of new product offerings and enhancements to existing products. A vital aspect of this role will be your ability to work effectively with design teams based in the US and Europe, showcasing your strong teamwork skills and collaborative mindset. To excel in this role, you should possess the following qualifications: - A Bachelor's or Master's degree in Electrical/Electronic Engineering - Minimum of 10 years of experience in FPGA development with expertise in Altera and Xilinx technologies - Proficiency in RTL languages such as VHDL or Verilog - Familiarity with Xilinx FPGA Tools Design Flow including Vivado, Chipscope, and Quartus - Experience in using EDA Functional Simulation tools like Synopsys, Mentor, or Cadence - Proven ability to adapt quickly to new technologies, protocols, and product segments - Hands-on experience in developing self-checking Simulation environments, test benches, automation scripts, and test case creation - Collaborative work with system architects to define system architecture and FPGA integration with other components on PCA boards - Strong background in timing closure for intricate designs - Exceptional written communication skills for creating various technical documents such as Product Definitions, Detailed FPGA Designs, and Hardware & Software Interface documents - Self-motivated, well-organized, and proactive individual - Excellent team player with a high level of responsiveness and accountability - Strong verbal communication skills Preferred qualifications include: - Familiarity with Keysight instruments like Oscilloscope, Analyzer, AWG & BERT - Experience working with protocols such as PCI Express, USB, MIPI, Ethernet, and DDR - Exposure to international and multi-vendor collaboration environments - Full-time job type with flexible schedule This role offers the opportunity to work in person at the specified location, providing a conducive environment for professional growth and innovation.,

Job Requirements Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills. Work Experience Key Responsibilities: Execute floorplanning, power planning, placement, CTS, routing, DRC/LVS, and timing closure for blocks/subsystems. Work on multi-voltage designs using UPF, level shifters, isolation cells, and retention strategies. Perform timing analysis and closure using PrimeTime and support IR/EM/Noise closure under guidance. Collaborate with DFT/RTL/STA teams to resolve integration and physical challenges. Run power optimization techniques at synthesis and post-route stage. Support subsystem-level integration and participate in debug and convergence discussions. Write scripts (Python, Tcl) for flow automation, data mining, and report generation. Required Skills: Hands-on experience with full RTL-to-GDS flow using Fusion Compiler, Innovus. Working knowledge of low power flows, UPF, VCLP, power intent checks. Familiarity with timing closure concepts, signal integrity, and power optimization. Good scripting skills in Python/Tcl/Perl for design automation. Enthusiastic team player with strong analytical and debugging skills.

Key Responsibilities Lead block-level PNR activities from floorplanning through final routing, ensuring robust physical implementation aligned with timing, power, and area goals. Drive power grid design and EM/IR-aware routing strategies to ensure block-level power integrity and reliability. Collaborate closely with timing closure engineers to resolve physical design bottlenecks impacting timing and signal integrity. Manage and optimize physical verification flows including DRC, LVS, antenna checks, and physical signoff. Automate PNR flows and develop scripts to improve productivity and design quality. Mentor and guide junior physical design engineers, fostering technical growth and best practices. Coordinate with cross-functional teams including RTL design, STA, verification, and backend integration to ensure seamless block-to-chip integration. Qualifications and Skills 8+ years of experience in physical design with a strong focus on block-level Place and Route (PNR) for complex SoC/IP subsystems, preferably at advanced technology nodes (16nm, 7nm, 5nm, or below). • Proven expertise in block-level physical implementation including floorplanning, placement, clock tree synthesis(CTS), routing, and physical verification (DRC/LVS). • Hands-on experience with industry-standard PNR tools such as Cadence Innovus, Synopsys ICC2, and Mentor Calibre. • Strong understanding of power grid design, EM/IRanalysis, signal integrity (SI), and reliability checks at the block level. • Experience in managing timing closure in coordination with STA teams, resolving congestion, and optimizing for power, performance, and area (PPA). • Proficiency in scripting languages (Tcl, Python, Perl) for flow automation and custom tool development. • Demonstrated ability to lead block PNR efforts, coordinate with RTL designers, physical design teams, and verification groups to meet aggressive tapeout schedules. • Familiarity with low-power design techniques and power- aware physical implementation.

Qualcomm India Private Limited is looking for a passionate STA and Synthesis Engineer to join their Engineering Group in Chennai. As an integral part of the cross-functional engineering teams, you will be engaged in all phases of design and development cycles, specifically focusing on Synthesis, Static Timing Analysis, and LEC of SoC/Cores. Your responsibilities will include full chip and block level timing closure, IO budgeting for blocks, logical equivalence checks between RTL to Netlist and Netlist to Netlist, as well as implementing low-power techniques such as clock gating, power gating, and MV designs. Additionally, you will be involved in ECO timing flow and should be proficient in scripting languages like TCL and Perl. The ideal candidate should possess a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 2+ years of experience in Hardware Engineering. Alternatively, a Master's degree with 1+ year of relevant experience or a PhD in the aforementioned fields is also acceptable. Applicants with 1-5 years of experience are encouraged to apply. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please contact Qualcomm at disability-accommodations@qualcomm.com or refer to their toll-free number for assistance. Qualcomm also emphasizes the importance of compliance with company policies and procedures, including security measures for protecting confidential information. Staffing and Recruiting Agencies are advised that Qualcomm's Careers Site is exclusively for individuals seeking job opportunities directly with Qualcomm. Agency submissions will be considered unsolicited, and Qualcomm does not accept unsolicited resumes or applications from agencies. For further details about this role, please reach out to Qualcomm Careers.,

You should have knowledge of AMBA protocols including AXI, AHB, APB, SoC clocking, reset, debug architecture, and peripherals like USB, PCIE, and SDCC. An understanding of memory controller designs and microprocessors would be an added advantage. Hands-on experience in constraint development and timing closure is essential for this role. You will be required to work closely with the SoC verification and validation teams for pre and post Silicon debug. Experience in Low power SoC design is a must-have for this position. You should also have experience in Synthesis and a good understanding of timing concepts for ASIC. Hands-on experience in Multi Clock designs and Asynchronous interface is a key requirement. Additionally, familiarity with tools in ASIC development such as Lint, CDC, Design compiler, and Primetime is necessary. The ideal candidate should have 2-4 years of relevant experience in the field.,

1Digital is looking for Graphic Design Professional to join our dynamic team and embark on a rewarding career journey Concept Development: Graphic Designers collaborate with clients or creative teams to understand their requirements and develop design concepts They brainstorm ideas, research visual trends, and create design mockups or sketches that align with the project objectives Visual Design: Graphic Designers use various design elements, such as color, typography, images, and layout, to create visually engaging designs They design graphics for print materials, digital platforms, websites, social media, logos, packaging, and other marketing or promotional materials Branding and Identity: Graphic Designers play a crucial role in developing and maintaining brand identity They create brand guidelines, including logo design, color palettes, typography, and visual style guides, to ensure consistency across all brand materials Layout and Composition: Graphic Designers determine the arrangement and placement of design elements within a layout They consider factors such as balance, hierarchy, proportion, and visual flow to create visually appealing and user-friendly designs Digital Design: In the digital space, Graphic Designers create designs optimized for various digital platforms, such as websites, mobile applications, social media platforms, and email campaigns They ensure the designs are responsive, user-friendly, and visually appealing across different devices and screen sizes Image Editing and Manipulation: Graphic Designers are skilled in image editing and manipulation using software such as Adobe Photoshop They retouch and enhance images, adjust colors, remove backgrounds, and resize images to fit design requirements

1Digital is looking for Graphic Design Professional to join our dynamic team and embark on a rewarding career journey Concept Development: Graphic Designers collaborate with clients or creative teams to understand their requirements and develop design concepts They brainstorm ideas, research visual trends, and create design mockups or sketches that align with the project objectives Visual Design: Graphic Designers use various design elements, such as color, typography, images, and layout, to create visually engaging designs They design graphics for print materials, digital platforms, websites, social media, logos, packaging, and other marketing or promotional materials Branding and Identity: Graphic Designers play a crucial role in developing and maintaining brand identity They create brand guidelines, including logo design, color palettes, typography, and visual style guides, to ensure consistency across all brand materials Layout and Composition: Graphic Designers determine the arrangement and placement of design elements within a layout They consider factors such as balance, hierarchy, proportion, and visual flow to create visually appealing and user-friendly designs Digital Design: In the digital space, Graphic Designers create designs optimized for various digital platforms, such as websites, mobile applications, social media platforms, and email campaigns They ensure the designs are responsive, user-friendly, and visually appealing across different devices and screen sizes Image Editing and Manipulation: Graphic Designers are skilled in image editing and manipulation using software such as Adobe Photoshop They retouch and enhance images, adjust colors, remove backgrounds, and resize images to fit design requirements

1Digital is looking for Graphic Design Professional to join our dynamic team and embark on a rewarding career journey Concept Development: Graphic Designers collaborate with clients or creative teams to understand their requirements and develop design concepts They brainstorm ideas, research visual trends, and create design mockups or sketches that align with the project objectives Visual Design: Graphic Designers use various design elements, such as color, typography, images, and layout, to create visually engaging designs They design graphics for print materials, digital platforms, websites, social media, logos, packaging, and other marketing or promotional materials Branding and Identity: Graphic Designers play a crucial role in developing and maintaining brand identity They create brand guidelines, including logo design, color palettes, typography, and visual style guides, to ensure consistency across all brand materials Layout and Composition: Graphic Designers determine the arrangement and placement of design elements within a layout They consider factors such as balance, hierarchy, proportion, and visual flow to create visually appealing and user-friendly designs Digital Design: In the digital space, Graphic Designers create designs optimized for various digital platforms, such as websites, mobile applications, social media platforms, and email campaigns They ensure the designs are responsive, user-friendly, and visually appealing across different devices and screen sizes Image Editing and Manipulation: Graphic Designers are skilled in image editing and manipulation using software such as Adobe Photoshop They retouch and enhance images, adjust colors, remove backgrounds, and resize images to fit design requirements