880 Timing Closure Jobs - Page 9

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilitie...

Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Job Description In your new role you will: Responsible for leading Physical Design and Timing Closure of low power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve ...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation. 3 years of experience with the Register-Transfer Level quality check tool flows (e.g., Lint, Clock Domain Crossing, Reset Domain Crossing, Synthesis). Preferred qualifications: Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC). Experience with IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols and ASIC methodology. Expe...

Responsibilities: Timing constraints development and validation for functional and test modes Timing analysis and closure responsibilities at SoC level as well as block/subsystem level ECO generation and tracking to closure by collaborating with PD, Design, Constraint team and other partners Required Skills and Experience : Experience in performing timing closure at SoC level and block level Hands-on experience with industry leading STA and ECO generation tools(PrimeTime, Tempus, Tweaker) IP integration and timing signoff Must have worked on lower technology nodes, preferably sub 7nm Strong data analysis and presentation skills Well versed with TCL/PERL or Python Experience in collaborating ...

Strong experience in Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirement Your Profile You are best equipped for this task if you have: Strong fundamentals and experi...

- Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Development & Review activities. - Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. - Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance. - Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. - Conduct thorough timing analysis, identify critical paths, and develop strategie...

Job Description: Vivado Backend Location : Hyderabad Experience : 4 years An experienced application engineer to focus on FPGA & ACAP Compilation flows, design closure ease-of-use, tools specification, validation, documentation, and key customer's support Open Position1 No. Basic Job Deliverable: Contribute to triaging reported issues in several Vivado product areas, such as design entry, synthesis, implementation, and help engineering address them effectively. Actively explore innovative methodologies and their impact on flow and design practices, with emphasis on timing closure and compile time, as well as productivity with the new Versal ACAP family. Develop and deliver training materials...

Hi All, Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus. 3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus. 4. Experience with hardware architecture exploration, performance modelling will be a b...

Alternate Job Titles: ASIC Physical Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the ...

Define the architecture of Memory PHY IPs, its major blocks Responsible to develop the architecture and create specification for clocking, ASIC interface, pin-outs, bump-outs, floor plans, functionalities to support the protocol/system level requirements, Digital/Analog/Firmware Interface and partitions, calibration and other algorithm definition, test/debug logic etc Work with cross-functional teams and technical experts in various geographies to define and align scope of the IPs Support marketing on presales activities technically Be the interface to the customer in technical interactions, feasibility analysis, interoperability definitions and tracking Understand and disseminate applicable...

Job Title: STA Design Engineer (Backend) Location: Bangalore Experience: 5+ Years Job Description: We are looking for an experienced STA Design Engineer with strong expertise in Static Timing Analysis (STA) for ASIC/SoC backend design. The candidate should have hands-on experience in timing closure, signoff methodologies, and working closely with physical design and RTL design teams to deliver high-quality silicon. Key Responsibilities: Perform Static Timing Analysis (STA) across multiple process, voltage, and temperature (PVT) corners. Drive timing closure at block and full-chip level. Work on constraint development, validation, and optimization (SDC files). Perform setup, hold, recovery, a...

As Logic Lead, you will be responsible for design and development of Compression, Security, and sustainability features for high performance Processors chips. Lead the Development of features - propose enhancements to existing features, new features, architecture in High level design discussions Develop micro-architecture, Design RTL, Collaborate with the Verification, DFT, Physical design, FW, SW, Research teams to develop the feature Guide and mentor junior engineers. Represent as Design Lead in various forums. Signoff the Pre-silicon Design that meets all the functional, area and timing goals Participate in silicon bring-up and validation of the hardware Estimate the overall effort to dev...

We are looking for a skilled SAP DRC Consultant with 19 years of experience to join our team at Forward Eye Technologies. The ideal candidate will have a strong background in SAP DRC and be able to work effectively in a fast-paced environment. Roles and Responsibility Collaborate with cross-functional teams to design and implement SAP DRC solutions. Provide technical expertise and support for SAP DRC projects. Develop and maintain documentation for SAP DRC implementations. Troubleshoot and resolve complex technical issues related to SAP DRC. Conduct training sessions for end-users on SAP DRC functionality. Work closely with stakeholders to understand business requirements and develop solutio...

Role Overview We are expanding our team in India and seeking a Staff Digital Design Engineer to lead the micro-architecture and implementation of advanced digital subsystems for automotive Ethernet communication systems You will collaborate across analog and digital teams to deliver high-performance, reliable solutions for next-generation automotive networks Required Skills + BS/MS/BTech/M Tech in Electrical Engineering or related field + 8+ years of experience in digital design for communication systems + Expertise in Verilog/SystemVerilog, Ethernet or similar protocols, and PHY layer design + Strong understanding of PLLs, clocking schemes, and timing closure + Experience with analog IP int...

We are looking for a skilled Senior Manager - Physical Design with 10-15 years of experience to lead our team in Bangalore, Hyderabad, Noida, Coimbatore. The ideal candidate will have a strong background in physical design and excellent leadership skills. Roles and Responsibility Manage and lead a team of physical design engineers to achieve project goals. Develop and implement automation scripts for physical design methodologies. Collaborate with front-end engineers to resolve timing and power issues. Evaluate new tools and drive power reduction of designs. Perform floorplanning and time budgeting for successful project execution. Ensure timely completion of projects by managing resources e...

Experience with low-power ASIC design techniques and clock domain crossing Knowledge of AMS verification methodologies Exposure to silicon bring-up and lab validation Familiarity with EDA tools from Synopsys, Cadence, or Mentor Bachelors or Masters degree in Electronics Engineering, Computer Engineering, or related field 8+ years of experience in ASIC digital design, with couple of years of technical leadership role Strong expertise in RTL design, CDC, synthesis, STA, LEC.. Proven experience in mixed-signal ASICs for deep sub-micron and understanding of analog-digital interfaces Familiarity with any scripting languages Excellent problem-solving, communication, and leadership skills Key Respo...

We are seeking highly motivated individuals with a BS, MS, or PhD degree in Computer Science, Computer Engineering/ECE, ready to handle the challenging problems in future technologies and designs. We are seeking energetic, highly motivated individuals willing to go the extra mile with the aim of helping the overall IBM development team. Our dynamic global team is looking to enlist enthusiastic professionals to join world-class hardware design teams responsible for developing the most challenging and complex systems in the world. We are looking for a passionate & experienced EDA Methodology Engineer to join our timing team focusing on timing methodology using IBM Einstimer, Cadence & Synopsys...

Location: Bangalore, Hyderabad, Noida, and Coimbatore. Skills: Soc level floorplanning, partitioning, timing budget generations, power planning, SOC PnR, CTS, block integration Handling timing closure of high frequency blocks. Expertise in signoff closure Timing with SI and OCV, Power, IR and physical verification at both block and chip level. Understanding constraints and fixing techniques. Experience in physical verification Understanding SI prevention, fixing methodology and implementation. Proficient in Synopsys ICC or Cadence or Mentor Olympus and Atoptech tool set. Experience in Design Automation and UNIX system. Experience in Tcl/ PERL is a plus. Primary Skills: Able to handle Soc PNR...

Role Overview: You will be responsible for complex SOC Top Physical Implementation for next generation SOCs in the area of mobile application processors, modem sub-systems, and connectivity chips. This will involve tasks such as Synthesis, Place and Route, STA, timing, and physical signoffs. You should have hands-on experience in physical design and timing closure of complex blocks and full-chip designs. Key Responsibilities: - Conduct top-level floor planning including partition shaping and sizing, pin placement, channel planning, high-speed signal and clock planning, and feed-through planning. - Understand timing, power, and area trade-offs, and optimize Power, Performance, and Area (PPA)....

As an FPGA Architect, you will play a key role in leading the design & development efforts for various projects within a collaborative and fast-paced environment. Your responsibilities will include defining and developing complex FPGA designs for Test products. You will collaborate closely with R&D Project Manager, Product Architects, Solution Teams, FPGA developers, Software Qualification, and Software Engineers to enhance existing products and introduce new offerings. Being a team player is essential as you will work with design teams across different geographical locations. Key Responsibilities: - Define and develop complex FPGA designs for Test products - Collaborate with various teams i...

Role Overview: You will be working as a Fellow Silicon Design Engineer at AMD to develop world-class Server products. Your main responsibility will be to define and drive PPA uplift methodologies, develop power optimization methodology for Physical Design Implementation, define PVT corners and frequency targets for next-generation Servers, and have a deep knowledge of micro-architecture, power optimization methodologies, and timing closure. You are expected to have very strong problem-solving skills, broad experience in methodology, and a self-motivated work ethic to provide a cohesive technical vision for PPA improvement methodology. Key Responsibilities: - Define and drive PPA uplift metho...

Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web-scale and service provider networks. Cisco''s silicon team provides an outstanding, unique experience for ASIC engineers by combining the resources offered by a sizable multi-geography silicon organization and a large campus (with an on-site gym, healthcare, caf, social interest groups, and philanthropy) with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Write micro-architecture specifications and participate in reviews. Implement Verilog RTL to meet timing, performance, and power requirements. Contribute to full chip integr...

Role : Senior STA Engineer Experience Required : 4-5 YEARS Job Location: HYDERABAD Bachelors or Masters degree in Electrical/Electronics Engineering. Preferred Qualifications: Experience with full-chip STA closure. Exposure to low-power design techniques and multi-mode/multi-corner analysis. Knowledge of timing integration for third-party IPs. Required Skills: Strong understanding of STA fundamentals and timing closure methodologies. Proficiency in tools like PrimeTime, Tempus, Tweaker, Timevision, Fishtail. Experience with scripting languages (TCL, Perl, Python) for automation. Familiarity with advanced nodes (e.g., 7nm, 5nm, FinFET). Good grasp of physical design flow and constraints manag...

Responsible for leading Physical Design and Timing Closure of low power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design , floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve design, methodology and process aspects. Enable next generation of place and route engineers via mentoring and thought leadership. Your Profile You are best equipped for this task if you have: Hands-on experience in physica...

You have a rewarding opportunity at Qualcomm India Private Limited in the Engineering Group, specifically in the Hardware Engineering team. As a Senior SoC Design Engineer, you will play a crucial role with your extensive experience in SoC design and expertise in various protocols and architectures. Let's delve deeper into the responsibilities and qualifications required for this role: **Role Overview:** - Utilize your 15+ years of experience in SoC design to contribute effectively to the team - Demonstrate proficiency in AMBA protocols such as AXI, AHB, and APB, as well as SoC clocking/reset/debug architecture - Showcase your knowledge of peripherals like USB, PCIE, and SDCC - Gain an under...