872 Timing Closure Jobs - Page 8

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 4-8 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and ...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. Bachelors or Masters degree from a top-tier institute. 8-14 years of experience in physical design from product-based companies. Experience: Proven experience in managing compl...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Responsibilities: STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs. Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. Run Primetime and/or Tempus for STA flow optimi...

Job Description A layout technical expert taking chip top ownership of analog-on-top ASIC developments. Hands-on technical contributor, able to take chiptop ownership including tape-out procedures. A teamplayer, able to collaborate within a global layout team and cross-discipline stakeholders. Required experience: 15+ years of experience in custom analog layout Experience with nodes in the range of 22nm-40nm-180nm is a must. Experience with BCD technologies is a must. Proven track record of owning chip top layout. Must be able to independently go through required tape-out procedures and take corrective actions. Must be able to take ownership of internal layout flows, continuously work on imp...

General Summary: Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 8 to 10 years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture ...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

Skills/experience: 3 to 6 years of experience in Microprocessor Architecture , Power analysis & optimization , Implementing SoC power managemen t schemes, Good knowledge of Linux Kernel, Debugging Tools, Power and performance analysis, A ndroid Power F ramework , Working experience in systems software design and development. Minimum Qualifications: Bachelor's degree in Engineering, Information Systems, Computer Science, or related field and 2+ years of Software Engineering or related work experience. OR Master's degree in Engineering, Information Systems, Computer Science, or related field and 1+ year of Software Engineering or related work experience. OR PhD in Engineering, Information Syst...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements Minimum Qualifications: Bachelor's degree in Computer Sci...

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in PCIe IP de...

As an ASIC Physical Design Lead, you will be leading the design of IP/SoC in advanced process technologies, serving global Semiconductor product MNC clients. Key Responsibilities: - Lead the physical design of complex ASIC projects from Netlist to GDSII. - Perform timing closure tasks including synthesis, place and route, and static timing analysis. - Oversee full-chip physical design processes, including floor planning, power grid design, clock tree synthesis, and signal integrity analysis. - Collaborate with the packaging team to ensure seamless integration of the chip design with the package, including pads log management, bump placement, and RDL routing. - Mentor junior engineers and gui...

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive de...

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical ...

You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow , doing implementation to achieve best in class ASICs , which are optimized for power, performance and area metrics HOW YOU WILL CONTRIBUTE AND WHAT YOU WILL LEARN Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure Perform technical evaluations of IP vendors, process nodes and provide recommendations...

About The Job Role Choosing Capgemini means choosing a place where youll be empowered to shape your career, supported by a collaborative global community, and inspired to reimagine whats possible.Join us in helping leading Consumer Products and Retail Services (CPRS) organizations unlock the value of technology and drive scalable, sustainable growth. Your Role: As a System Power, Thermal and Performance Engineer , you will play a critical role in validating and optimizing system-level performance across CPU, GPU, and AI/ML workloads. Youll work on Android and Linux platforms, leveraging your understanding of SoC subsystems and performance/power KPIs to drive efficiency and innovation. In thi...

Recruiting is a specialized area of staffing and recruiting focused on attracting and placing prospective employees including: Promoting the organizations image as a desirable place to work Attracting, recruiting, screening, and interviewing candidates Recommending placement of internal and external candidates for entry-level and experienced positions Referring applicants for particular job openings, administering pre-employment tests, checking references, conducting exit interviews for candidates declining offers, and providing feedback to unsuccessful candidates May assist with job advertising and postingPositions on this level are fully proficient in executing established standards. Works...

As an experienced Physical Design Engineer, you will be responsible for executing block level P&R and Timing closure activities. Your primary role will involve owning up block level P&R and performing Netlist2GDS on blocks. You will be working on the implementation of multimillion gate SoC designs in cutting-edge process technologies such as 28nm, 16nm, 14nm, and below. Your expertise should cover various aspects of physical design, including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design, Place and Route, Clock Planning and Clock Tree Synthesis, complex analog IP integration, Parasitic Extraction, Timing Closure, Power / IR Drop (Static and Dynamic), Signal I...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NAMinimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilitie...

Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Job Description In your new role you will: Responsible for leading Physical Design and Timing Closure of low power SoCs. Responsible to achieve die area, performance, power goals for hierarchical blocks and top. Drive physical design implementation which includes package co-design, floor planning, power grid design and signoff, place and route, timing closure, physical verification checks. Influence tools, flows and methodology activities to improve upon QoR. Interact with cross-functional team members to improve ...

Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 3 years of experience with Register-Transfer Level (RTL) design and integration using Verilog/System Verilog, microarchitecture and automation. 3 years of experience with the Register-Transfer Level quality check tool flows (e.g., Lint, Clock Domain Crossing, Reset Domain Crossing, Synthesis). Preferred qualifications: Experience with methodologies for Register-Transfer Level (RTL) quality checks (e.g., Lint, CDC, RDC). Experience with IP integration methodology, IP Design, ARM-based SoCs, ARM-protocols and ASIC methodology. Expe...

Responsibilities: Timing constraints development and validation for functional and test modes Timing analysis and closure responsibilities at SoC level as well as block/subsystem level ECO generation and tracking to closure by collaborating with PD, Design, Constraint team and other partners Required Skills and Experience : Experience in performing timing closure at SoC level and block level Hands-on experience with industry leading STA and ECO generation tools(PrimeTime, Tempus, Tweaker) IP integration and timing signoff Must have worked on lower technology nodes, preferably sub 7nm Strong data analysis and presentation skills Well versed with TCL/PERL or Python Experience in collaborating ...

Strong experience in Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs Job Description In your new role you will: Implement high-performance, low-power, and area-efficient digital designs. Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Optimize designs for power, performance, and area, and meet PPA goals. Power analysis using PT-PX or equivalent flow. Logic Equivalence Check (LEC) and Low Power Checks (CLP) at block and SoC level designs. Define and evaluate constraints and signoff Test/DFT mode timing requirement Your Profile You are best equipped for this task if you have: Strong fundamentals and experi...

- Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Development & Review activities. - Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs. - Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance. - Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes. - Conduct thorough timing analysis, identify critical paths, and develop strategie...

Job Description: Vivado Backend Location : Hyderabad Experience : 4 years An experienced application engineer to focus on FPGA & ACAP Compilation flows, design closure ease-of-use, tools specification, validation, documentation, and key customer's support Open Position1 No. Basic Job Deliverable: Contribute to triaging reported issues in several Vivado product areas, such as design entry, synthesis, implementation, and help engineering address them effectively. Actively explore innovative methodologies and their impact on flow and design practices, with emphasis on timing closure and compile time, as well as productivity with the new Versal ACAP family. Develop and deliver training materials...

Hi All, Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point datapath design is a plus. 3. Should have experience using ASIC design tools such as VCS, Verdi, Design Compiler. Knowledge of power estimation tools(such as Spyglass, PTPX), scripting languages (Shell, Perl, Python), C language is a plus. 4. Experience with hardware architecture exploration, performance modelling will be a b...