600 Timing Closure Jobs - Page 4

1. Deep Submicron Technology Experience: Hands-on experience with SYN/APR/Signoff and tapeout in deep submicron technology. 2. Familiarity with EDA Tools: Proficient in using EDA tools such as ICC, ICCII, and INNOVUS.3. ASIC Flow Knowledge: Well-versed in the ASIC design flow.4. Programming Skills: Proficient in Tcl, Perl, scripting, C, and C++ programming languages. 5. Strong Communication Skills: Excellent communication abilities. 6. Proactive and Responsible: Highly proactive, enthusiastic, and responsible. 7. Education and Experience: MS degree with at least 2 years of experience in the PnR field is preferred. 8. Large-Scale Design Experience: Experience handling designs with more than 2 million instance counts is preferred.9. Top-Level Physical Design and Advanced Node Experience: Experience in top-level physical design and advanced node tapeout is highly desirable. 1. Physical Design Implementation and Methodology: Engage in the implementation of physical design, develop methodologies, and manage sign-off processes. 2. Core Design Tasks: Execute floorplanning, clock planning, placement and routing, timing closure, and physical verification to ensure design integrity and performance. 3. Project Management: Oversee project schedules, troubleshoot design and workflow issues, and drive methodological improvements and execution strategies. 4. Collaborative Teamwork: Work collaboratively with team members to successfully complete projects within designated timelines. 5. Programming Skills: Utilize programming skills to effectively complete tasks, with a focus on scripting and automation to enhance workflow efficiency .6. Proficiency in EDA Tools: Demonstrate proficiency in using Electronic Design Automation (EDA) tools such as Innovus, ICC2, LEC, PrimeTime, Calibre, among others.

In this role, you will be leading all block/chip level physical design activities. This includes tasks such as generating floor plans, abstract views, RC extraction, PNR, STA, EM, IR DROP, DRCs, and schematic to layout verification. Collaboration with the design team to address design challenges will be a key aspect of this position. You will also be assisting team members in debugging tool/design related issues and constantly seeking opportunities to enhance the RTL2GDS flow to improve power, performance, and area (PPA). Troubleshooting various design issues and applying proactive interventions will be part of your responsibilities. Your main responsibility will be overseeing all aspects of physical design and implementation of GPUs and other ASICs targeted at the desktop, laptop, workstation, and mobile markets. Minimum Qualifications: - Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 3 years of Hardware Engineering or related work experience. - Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 2 years of Hardware Engineering or related work experience. - PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field with at least 1 year of Hardware Engineering or related work experience. What We Need To See: - Strong experience in Physical Design. - Proficiency in RTL2GDSII flow or design implementation in leading process technologies. - Good understanding of concepts related to synthesis, place & route, CTS, timing convergence, and layout closure. - Expertise in high frequency design methodologies. - Knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification. - Working experience with tools like ICC2/Innovus, Primetime/Tempus, etc., used in the RTL2GDSII implementation. - Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred. - Familiarity with timing constraints, STA, and timing closure. - Proficiency in automation skills in PERL, TCL, tool-specific scripting on industry-leading Place & Route tools. - Ability to multitask and work in a global environment with flexibility. - Strong communication skills, motivation, analytical & problem-solving skills. - Proficiency in using Perl, Tcl, Make scripting is preferred. As you consider your future career growth, we invite you to explore the opportunities our organization can offer you.,

As a Senior Physical Design Engineer with Micron Technology, you will play a crucial role in the HBM Team based in Hyderabad, India. Your primary responsibility will be to design and develop complex Application-Specific Integrated Circuits (ASICs) catering to the requirements and specifications of High Bandwidth Memories (HBM). These memories are utilized in intensive applications like artificial intelligence and high-performance computing solutions, aiming to push the boundaries of technology and innovation. Your role involves designing IPs or Hierarchical blocks solutions for high-performance and low-power applications. You will collaborate closely with cross-functional teams to define project requirements and conduct feasibility studies. Your expertise will be instrumental in creating detailed IPs or Hierarchical blocks design specifications, ensuring alignment with project goals. Additionally, you will enable Place and route, clock tree synthesis capabilities for the System on Chip (SoC) Integration. To excel in this position, you will implement and optimize digital designs using hardware description languages (HDLs) such as Verilog or VHDL, considering various design trade-offs and performance metrics. Your responsibilities will also include evaluating RTL coding, timing analysis, synthesis, and functional verification to ensure the correctness and robustness of the design. As a Senior Physical Design Engineer, you will lead and participate in verification efforts, write testbenches, run simulations, and debug functional and timing issues. Collaboration with physical design engineers is essential to guide and optimize the layout to achieve performance and power targets effectively. Moreover, you will contribute to the evaluation and selection of third-party IP blocks to integrate into the IPs or Hierarchical blocks design. It is crucial to stay updated with the latest design methodologies, tools, and industry trends, continuously enhancing design practices. Additionally, mentoring junior engineers by providing technical guidance and support will be part of your role. To be successful in this position, you should have at least 5 years of relevant work experience focused on RTL to GDS for high-performance architectures. Experience in physical design, timing closure, and physical integration/signoff is essential. You should possess a drive for continuous learning, evaluating microarchitectural options, and interconnecting complex microarchitectural structures and subsystems. Proficiency in hardware description languages (HDLs), familiarity with EDA tools, and a strong understanding of design methodologies are required. Scripting language proficiency for automating design tasks will be advantageous. A Bachelor's degree (BE) or Master's degree (MTech) in Electronic/VLSI Engineering is necessary to qualify for this role. Micron Technology, Inc. is a global leader in innovative memory and storage solutions, dedicated to transforming the use of information to enrich life for all. If you are passionate about pushing the boundaries of technology and innovation, this role offers an exciting opportunity to contribute to cutting-edge semiconductor products and maintain a competitive edge in the industry.,

At AMD, we are dedicated to transforming lives with our cutting-edge technology to make a positive impact on our industry, communities, and the world. Our goal is to create exceptional products that drive next-generation computing experiences, serving as the foundation for data centers, artificial intelligence, PCs, gaming, and embedded systems. Central to our mission is the AMD culture, where we continuously strive for innovation to address the world's most pressing challenges. We are committed to achieving excellence in execution while upholding values of directness, humility, collaboration, and inclusivity of diverse perspectives. As a SOC Physical Design Director at AMD, you will play a crucial role in leading the development of Server SOC designs and managing a skilled physical design team. This senior position is pivotal in the design evolution of Server SOC products at AMD, ensuring the delivery of high-performance Server SOCs that meet stringent requirements for frequency, power, and other design specifications for our next-generation processors. Operating within a dynamic and fast-paced environment on cutting-edge technology, you will be at the forefront of innovation to drive the success of AMD's future products. The ideal candidate for this role will possess exceptional people leadership skills and the ability to foster teamwork among cross-functional teams across different locations. With a strong technical background and expertise, you will demonstrate advanced analytical and problem-solving capabilities while collaborating with executive-level technical and management leaders to influence and lead transformative change. Key Responsibilities: - Lead and oversee a team of engineers specializing in SOC Physical Design implementation and Signoff - Utilize deep knowledge and experience in Physical design, Timing closure, and signoff to guide the development of complex and advanced Server SOC designs, ensuring timely and high-quality delivery - Provide effective team management to mentor, coach, and cultivate the growth of the Server SOC Physical Design Team, emphasizing a positive impact on team morale and culture - Manage various aspects of Physical Design, including Full Chip Floor planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification, and Sign-Off - Collaborate with cross-functional teams encompassing Architecture, Product Planning, Packaging, IPs, and CAD to drive SOC Implementation and enhance Power, Performance, and Area (PPA) metrics - Possess expertise in flow development and scripting, with a focus on technical problem-solving and debugging Preferred Experience: - Over 20 years of experience in SOC Physical Design Implementation, Signoff, and TapeOut - Prior leadership experience in managing Physical Design teams comprising at least 50+ members - Strong analytical and problem-solving skills with meticulous attention to detail - Excellent written and verbal communication, Time Management, and Presentation Skills - Self-motivated individual capable of independently driving and efficiently completing challenging and time-critical tasks - Forward-thinking and dependable leader who proactively identifies and resolves issues and obstacles to prevent delays or disruptions - Proficiency in EDA tools for Physical Design and Signoff cycles, such as Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Academic Credentials: - Bachelor's or Master's degree in Electrical Engineering Joining AMD offers you an exciting opportunity to be part of a dynamic team that is shaping the future of technology. Experience a rewarding career with us and contribute to the advancement of innovative solutions that have a global impact.,

We are seeking an exceptional Senior Physical Design Engineer to take a key role in our semiconductor design team. As a Senior Physical Design Engineer, you will lead the development and implementation of cutting-edge physical design methodologies and flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensure the successful delivery of high-quality designs Key Responsibilities Perform Synthesis, floor planning, placement, Clock, routing, and PPA optimization for High Speed Advance ASICs. Define and drive physical design strategies to meet aggressive performance, power, and area targets. Conduct detailed analysis of timing, power, and area, and drive design optimizations to improve QoR. Block/Partition signoff closure for STA, PV, LEC, IR/EM, CLP very efficiently. Provide technical leadership and guidance to the physical design team, mentoring junior engineers and fostering a culture of excellence. Work closely with RTL design and DFT teams to understand design requirements and constraints, and drive successful tapout of designs. Support and Development of advanced physical design methodologies and flows for complex semiconductor designs. Requirements Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. 4+ years of experience in physical design of ASICs Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics for Synthesis, PnR, Signoff Closure. Extensive experience with timing closure techniques, power optimization. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Expertise in Synthesis that includes details understanding of RTL, Early PnR timing issues, Constraint issue, design issues. Experience in handling Partitions and blocks for size estimation, pin assignment, CTS. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration. Detailed Knowledge on Clocking methodology and various techniques to improve skew, latency, timing, power. Familiarity with low-power design techniques and methodologies, such as multi-voltage domains and power gating using UPF. Expertise in physical verification, including DRC, Antenna, LVS, PERC, and ERC checks. Expertise in Timing Closure including setup, hold, DRV, SI, Interface issues. Experience with formal verification for RTL to Netlist and Netlist to Netlist. Knowledge of emerging technologies such as machine learning and AI for design automation and optimization.

Job Purpose To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement. Duties and Responsibilities 1.Resolving SFDC functions related issues2.Resolving BRE level issues3.Educating internal and field teams on issues due to training requirements4.Constant observations on the issues raised by the field team5.Raising regular IT request to resolve issues6.Constant communication between IT and Product teams to identify the changes7.Attending bi-weekly meetings with IT to find the bigger solution8.Find solutions to the repetitive problems and submit BRD9.Interacting with field teams to identify the exact issues. Required Qualifications and Experienc E ducational Qualificationsa)Graduate or equivalentb)1+ years of experience Finance industry support of systemc)Well versed in MS Officed)Agile ability on the work timings

Job Purpose This position is open with Bajaj Finance ltd To handle and provide solution for a transactional activities of field team and making sure the implementation of projects are end to end satisfying the requirement Duties and Responsibilities Resolving SFDC functions related issues2 Resolving BRE level issues3 Educating internal and field teams on issues due to training requirements4 Constant observations on the issues raised by the field team5 Raising regular IT request to resolve issues6 Constant communication between IT and Product teams to identify the changes7 Attending bi-weekly meetings with IT to find the bigger solution8 Find solutions to the repetitive problems and submit BRD9 Interacting with field teams to identify the exact issues Required Qualifications and Experience Graduate or equivalentb)1+ years of experience Finance industry support of systemc)Well versed in MS Officed) Agile ability on the work timings

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with Physical design to close SDC related timing issues. Analysis of timing from synthesis to verify constraints. Work with architects and logic designers to generate block and full chip timing constraints. Analyse scenarios and margin strategies with Synthesis & Design team. Work on SDC for block, partition, Fullchip such as define constraints, IO budgeting, merging constraints. Work with third party IP, derive timing signoff requirements. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Total 4+ years of experience in STA, timing closure related work. Hands-on experience in ASIC timing constraints generation and timing closure. Tool Knowledge on Timevision, Fishtail, Genus, Prime Time, Tempus, Tweaker is MUST. Deep understanding and experience in various functional and test modes. Good fundamental on Physical design implementation. Validate timing constraints for Block and Partitions. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization.Excellent problem-solving and analytical skills, with a track record of delivering high-quality designs on schedule. Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Ability to work cross-functionally with various teams and be productive under aggressive schedules. Proven ability to lead and mentor junior engineers, fostering their professional growth and development. Preferred Qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Has at least worked on full chip STA closure of large size silicon. Tool Knowledge on Fishtail, Timevision and other standard tool for constraint development. Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for STA integration. Familiarity with low-power design techniques and methodologies, such as multivoltage domains and power gating using UPF

Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etcYou are meticulous about Power, Performance and Area while driving schedule and managing cost.You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Experience in STA, full chip timing Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

The position will involve working with a very experienced physical design team of Server SOC and is responsible for delivering the physical design of tiles and FullChip to meet challenging goals for frequency, power and other design requirements for AMD next generation processors in a fast-paced environment on cutting edge technology. THE PERSON: The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etcYou are meticulous about Power, Performance and Area while driving schedule and managing cost.You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Working on full chip timing analysis setup and signoff of multi-corner multi-voltage designs.;Hierarchical timing analysis and convergence at block, section and fullchip level. Engaging closely with Design teams to understand the design, constraints and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations. Handling different PNR tools - Synopsys FusionCompiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design,full chip timing andpreferably with high performance designs. Experience in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Working on full chip timing analysis setup and signoff of multi-corner multi-voltage designs.;Hierarchical timing analysis and convergence at block, section and full chip level. Engaging closely with Design teams to understand the design, constraints and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations. Handling different PNR tools - Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design,full chip timing andpreferably with high performance designs. Experience in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD s graphics processor IP, resulting in no bugs in the final design. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details. ACADEMIC CREDENTIALS: Bachelors orMastersdegree in computer engineering/Electrical Engineering

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/timezones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. KEY RESPONSIBILITIES: Implementing RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 5+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases Work with IP SOC teams across all our sites (GFX, Memory controller, Multimedia engines, IOs, PCIE ) to understand the features and create verification plans Will help scoping out the testbench architecture and the simulation configuration, test planning, coverage planning etc Will develop system config and initialization sequences to various system configurations at the SOC Will work with Graphics/IO IP team and verify some of the graphics features at GPU SOC level, give out callouts to IPs and verify the SOC context. Will work on creating test bench components like checkers, monitors, test cases, coverage infrastructure, running simulations, debug, coverage analysis closure etc Estimate the time required to write the new feature tests and any required changes to the test environment Build the directed and random verification tests Debug test failures to determine the root cause; work with RTL and IP engineers to resolve design defects and correct any test issues Review functional and code coverage metrics modify or add tests or constrain random tests to meet the coverage requirements PREFERRED EXPERIENCE: B.E/B.Tech/M.E/M.Tech in Electrical/Electronic Engineering 8+ years experience in Design Verification preferably with SOCs. Experience with SOC verification that involves Graphics core, memory subsystem, PCIE subsystems, cache coherency, interconnects would be a plus. Experience with setting up verification infrastructure would be desirable. Should have strong experience with SV/UVM Methodology Must have excellent knowledge of Design verification flows Experience in developing complex test bench/model in Verilog, System Verilog or SystemC Experience in writing test plans and test cases Excellent hands-on debug skills Strong Verilog, System Verilog, PLI/DPI interface, SystemC or C/C++, Perl/shell script programming skills. Must have good communication skills and the ability and desire to foster a team environment. Must be we'll organized and should be good at multi-tasking. Good understanding for digital system and computer organization Should be a confident coder and be comfortable debugging general hardware/software problems.

Engineer with good attitude who seeks new challenges and has good analytical and and problem-solving skills. Candidate needs to have the ability and desire to learn quickly and should be a good team player who hasexcellent communication skills and experience collaborating with other engineers located in different sites/timezones. KEY RESPONSIBILITIES: Working on static timing analysis setup and signoff of multi-corner multi-voltage designs. Owning timing execution to meet timing requirements including timing budgeting, repeater planning, constraints/exceptions generation and management Areas of focus include Timing analysis and verification, extraction and noise glitch analysis Engaging closely with Design teams to understand the design and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations. Hierarchical timing analysis and convergence at block, section and fullchip level. Understanding CTS strategies, LVF/POCV variations and providing feedback to the implementation/methodology teams. Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Demonstrated ability in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must. Multi-voltage scenarios design handling knowledge is expected. STA closure/convergence execution on Low power designs is an added advantage. Expertise in industry standard EDA tools (Primetime) and ASIC design flow is required Hands-on experience with Physical Design implementation is a plus Proficiency in scripting language, such as, Perl and Tcl. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET & Dual Patterning nodes such as 16/14/10/7/5nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

The ideal candidate has significant experience in industry, with good attitude who seeks new challenges and has good analytical and problem-solving skills. You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc You are meticulous about Power, Performance and Area while driving schedule and managing cost. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide and help to elevate the knowledge and skills of the team around you. KEY RESPONSIBILITIES: RTL to GDS2 flow Handling Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, , Routing, Extraction, Timing Closure (Tile level, Full chip), Physical Verification (DRC LVS), Crosstalk Analysis, EM/IR Working on full chip timing analysis setup and signoff of multi-corner multi-voltage designs.;Hierarchical timing analysis and convergence at block, section and full chip level. Engaging closely with Design teams to understand the design, constraints and convergence challenges and providing ECOs with a focus on PPA and TAT optimizations. Handling different PNR tools - Synopsys Fusion Compiler, Cadence Innovus, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk Identify and implement opportunities for improving PPA PREFERRED EXPERIENCE: 16+ years of professional experience in physical design,full chip timing andpreferably with high performance designs. Experience in areas of Timing analysis, timing convergence, SI/Noise analysis, Signoff quality (PVT, process variation effects, guardbanding, etc), Timing ECOs, PV/Noise modelling, .libs, is a must. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Proficiency in scripting language, such as, Perl and Tcl. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in FinFET Dual Patterning nodes such as 16/14/10/7/5nm/3nm Excellent physical design and timing background. Good understanding of computer organization/architecture is preferred. Strong analytical/problem solving skills and pronounced attention to details.

You will possess very strong DFT knowledge and bring broad experience in with a strong, self-motivated work ethic and leadership qualities. KEY RESPONSIBILITIES: Work closely with the SoC Architecture and uArch teams to define the DFT architecture. Be the Tech Lead driving DFT RTL implementation, DFT functional and Scan capture timing closure, Scan/ATPG implementation to hit the product coverage goals, interactions with the Product Engineering team to ensure on-time and FirstTimeRight pattern delivery and silicon bring-up Drive the required pre-silicon reviews for RTL, DFT DV and ATPG to ensure clean silicon bring-up Collaborate with the Arch, Design, Functional DV, Emulation, Platform Debug, etc teams to comprehend and validate all the usage models Work with the post-silicon team on debug support and to help root-cause any failures Be upto date with the industry trends and bring-in the latest to the AMD products Work with DFT Tool Vendors and drive improvements based on our requirements REQUIREMENTS: 15+ years of in-depth DFT experience having driven multiple Tapeouts and silicon bring-ups across different process nodes. Good understanding and exposure to SoC design and architecture Very good understanding of verif and timing concepts having handled DFT timing closure Exposure to all DFT concepts such as JTAG, SCAN, MBIST, BScan, etc Comfortable with VCS/Verdi and Mentor TK. Logical in thinking and ability to gel we'll within a team Good stakeholder management Ability to quickly adapt to changes and handle pressure Good communication and leadership skills

The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMDs next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure. Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA. Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff. Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk PREFERRED EXPERIENCE: 12+ years of professional experience in physical design, preferably with high-performance designs. Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality; familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow - Perl/Tcl/Python Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Experience in advanced sub 7nm nodes Excellent physical design and timing background. A good understanding of computer architecture is preferred. Strong analytical/problem-solving skills and pronounced attention to detail. ACADEMIC CREDENTIALS: Qualification: Bachelors or Masters in Electronics/Electrical Engineering

As a Silicon Design Engineer in the AMD AECG ASIC TFM (tools Flows Methodology) team, you will work with design experts (FE and BE) to come up with the best implementation methodologies/flows and work on development and support of the FE/BE flows. KEY RESPONSIBILITIES: Define and drive key Frontend/Beckend/Physical Design methodologies. Partner with AMD CAD Teams, Design team, physical design teams to ensure seamless end to end design flows. Work with existing development teams to define roadmaps for existing flows and assist in difficult technical debug. Work closely with design teams to gather requirements and develop strategies to tackle key technical problems. Work on Floor-plan, Physical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), Crosstalk Analysis, EM/IR Handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache Redhawk PREFERRED EXPERIENCE: 8+ years of professional experience in physical design, preferably with high performance designs. Experience in automated synthesis and timing driven place and route of RTL blocks for high speed datapath and control logic applications. Experience in automated design flows for clock tree synthesis, clock and power gating techniques, scan stitching, design optimization for improved timing/power/area, and design cycle time reduction. Experience in floorplanning, establishing design methodology, IP integration, checks for logic equivalence, physical/timing/electrical quality, and final signoff for large IP delivery Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality, familiarity with tools for schematics, layout, and circuit/logic simulation Versatility with scripts to automate design flow. Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams Excellent physical design and timing background. Strong analytical/problem solving skills and pronounced attention to details.

You are an experienced STA (Static Timing Analysis) Engineer with over 5 years of expertise in the field of semiconductor design. In this role, you will play a crucial part in our team, working alongside skilled professionals to develop cutting-edge designs that emphasize performance, energy efficiency, and scalability. Your responsibilities will involve leading the timing analysis for advanced, high-speed, and intricate large ASIC designs, ensuring the delivery of top-notch designs through collaboration with diverse teams. Your key responsibilities will include leading a team of STA engineers to close complex designs, conducting comprehensive timing analysis from initial exploration to tape-out, developing timing methodologies to enhance the timing flow, collaborating with architects and logic designers to establish timing constraints, analyzing scenarios with the Synthesis & Design team, partnering with physical design teams for design closure, improving interface and clock latency, and developing SDC constraints for blocks and full-chip designs. Additionally, you will collaborate with third-party IP providers to meet timing signoff requirements effectively. To qualify for this role, you must hold a Bachelor's or Master's degree in Electrical Engineering or Electronics & Communications, possess a strong background in STA with hands-on experience in timing constraints generation and closure, demonstrate proficiency in industry-standard timing EDA tools, have expertise in deep-submicron processes and timing closure strategies, be skilled in scripting using TCL, Python, or Perl, exhibit problem-solving abilities and excellent communication skills, and have a proven record of delivering high-quality designs within project timelines. Your role will also involve mentoring junior engineers and working efficiently in a team-oriented environment. If you are a dedicated and experienced STA Engineer looking for an opportunity to work on challenging projects and contribute to innovative designs, we encourage you to share your updated resume with us at maruthiprasad.e@eximietas.design. Join our team and be part of shaping the future of semiconductor design.,

Job Overview : We are seeking an exceptional Physical Verification Engineer to take a key role in oursemiconductor design team. As a Block/Fullchip/Partition Physical Verification Engineer , you willResponsible for development and implementation of cutting-edge physical verification methodologiesand flows for complex ASIC designs. You will collaborate closely with cross-functional teams to ensurethe successful delivery of high-quality designs Responsibilities : Drive physical verification DRC, Antenna, LVS, ERC at cutting edge FinFET technology nodesfor various foundries. Physical verification of a complex SOC/ Cores/ Blocks DRC, LVS, ERC, ESD, DFM, Tape out. Work hands-on to solve critical design and execution issues related to physical verificationand sign-off. Own physical verification and sign-off flows, methodologies and execution of SoC/cores. Good hands on Calibre, Virtuoso etc. Requirements: Bachelors or Masters degree in Electrical Engineering or Electronics & Communications. Proficiency in industry-standard EDA tools from Cadence, Synopsys and Mentor Graphics. Strong scripting skills using TCL, Python, or Perl for design automation and tool customization. Expertise in physical verification of Block/Partition/ Full-chip-level DRC, Experience and understanding of all phases of the IC design process from RTL-GDS2. LVS, ERC, DFM Tape out process on cutting edge nodes, Preferably worked on 3nm/5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in debugging LVS issues at chip-level/block level with complex analog-mixed signal IPs Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.) Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc. Experience with ERC rules and ESD rules has an added advantage Outstanding communication and interpersonal skills, with the ability to collaborate effectively in a team environment. Proven ability to Engineer and mentor junior engineers, fostering their professional growth and development. Preferred qualifications: Experience with advanced process nodes 3nm, 5nm, 7nm, 10nm including knowledge of FinFET technology. Proven track record with multiple successful final production tape-outs Proven ability to independently deliver results and be able to work hands-on as and guide/help peers to deliver their tasks Be able to work under limited supervision and take complete accountability. Excellent written and verbal communication skills Knowledge on Handling various custom IP such as PLL, Divider, Serdes, ADC, DAC, GPIO, HSIO for PD integration and Physical verification challenges.

Requirements :Bachelors or Masters Degree with a strong VLSI BackgroundMinimum 3 years of experience in the area of Synthesis Synthesis Engineer: (3-10 Years)Key Responsibilities:Synthesis Environment setupValidating synthesis SDC qualityUtilize Synthesis tool variables and methodologies to extract the best area/power achievable for the process node Checking the synthesis DEF qualityAnalyze critical timing violation groups and congestion solve them by finetune floorplan or placement constraints Compare area/power with previous projects and check current project results DFT Insertion and debugging basic DFT issues Discuss directly with Design teams & Physical design teams to get the best synthesis results

RESPONSIBILITIES:Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksEnsuring timing correlation between PnR STA and timely feedbacks to PD teamGenerating block level HS session and using Top context from SoC for Block-SoC Interface timing closure Generating timing ECO using Tweaker/PrimeClosure

SpiderChip is looking for Physical Design Engineer to join our dynamic team and embark on a rewarding career journey The Physical Design Engineer is responsible for designing and implementing the physical layout of integrated circuits (ICs) using industry-standard tools and methodologies Participate in design reviews and provide input on design trade-offs, performance targets, and optimization strategies Excellent communication and collaboration skills Strong analytical and problem-solving skills Familiarity with scripting languages, such as Tcl, Perl, or Python Education : BTech in ECE/EEE or MTech VLSI No. of positions : 10 Desired Skills: