1082 Timing Closure Jobs - Page 2

Location: Bengaluru, India Type: Full-Time Industry: Semiconductors / VLSI / ASIC Design Job Summary We are seeking an experienced Physical Design Technical Manager to join our chip development team. In this leadership role, you will drive the implementation and optimization of complex ASIC designs from RTL to GDSII . You will collaborate closely with RTL, Verification, and DFT teams to ensure successful tape-outs of high-performance, low-power silicon designs, while mentoring team members, driving execution, and contributing to methodology and flow improvements. Key Responsibilities Technical Manager Responsibilities (Added Pointers) Own project planning, resource allocation, and delivery f...

You have the opportunity to work as an Analog / Mixed Signal Layout Designer with 2-8 years of hands-on experience in advanced FinFET processes such as 16nm, 12nm, 10nm, 7nm, 5nm, 3nm. Your responsibilities will include: - Expertise in complete PNR flow including CTS, routing, and Timing Closure. - Hands-on experience in critical blocks like SERDES, PHY, HDMI, PLL, ADC, DAC, LDO, Bandgap, Ref Generators, Charge Pump, Current Mirrors, Comparator, Differential Amplifier, etc. - Understanding of CMOS / Bi-CMOS / SOI / FinFET process and AMS IP integration according to Full Chip needs. - Problem-solving skills in Routing Congestion, Physical Verification in Custom Layout, and verification checks...

Role Overview: As an FPGA Architect, you will play a pivotal role in leading the design and development efforts across various projects in a dynamic and collaborative work environment. Your primary responsibility will involve defining and developing intricate FPGA designs for Test products. Working closely with cross-functional teams including R&D Project Manager, Product Architects, Solution Teams, FPGA developers, and Software Engineers, you will contribute to the enhancement of existing products and the creation of new product offerings. Collaboration with design teams based in the US and Europe will be a key aspect of this role. Key Responsibilities: - Lead the design and development of ...

As a Fellow Silicon Design Engineer at AMD, your role will be to develop world-class Server products by defining and driving PPA uplift methodologies, deploying power optimization methodology, and ensuring the success of next-generation Servers in leading foundry technology nodes. Your expertise in microarchitecture, power optimization methodologies, and high-frequency design closure will be crucial in achieving the desired performance, power, and area improvements. You will collaborate with internal stakeholders and contribute to the cohesive technical vision required for PPA improvement methodology. Key Responsibilities: - Define and drive PPA uplift methodologies for Server products - Dev...

As an FPGA Design Engineer at Eviden, located in Bangalore (Whitefield), you will be responsible for designing FPGAs for Server Motherboards. Your key responsibilities will include: - Understanding the requirements for FPGA design - Creating detailed designs and design documents for FPGA implementation - Developing test benches and conducting verification - Performing on-board validation of the FPGAs To qualify for this role, you should have: - A Bachelor's Degree (BE/BTech) or Master's Degree (ME/MTech) in Electronics - At least 3 years of experience in FPGA development - Good knowledge of FPGA design using Verilog/VHDL - Experience in FPGA design implementation and verification - Expertise...

As a Physical Design Specialist at AMD, you will play a crucial role in troubleshooting critical issues, offering independent analysis, and ensuring execution excellence in the physical design of semiconductor products, particularly focusing on CPU core physical design. Your responsibilities will include: - **Critical Issue Resolution:** - Identify and resolve complex physical design problems during dry runs and execution. - Provide independent analysis and solutions for design integrity and performance challenges. - Address issues such as timing closure, optimization, and signal integrity. - **Securing Execution Excellence:** - Ensure high standards of execution excellence by providing stra...

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Qualcomm Overview: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age - and this is where you come in. General Summary: 8-15 years of relevant ASIC design experience Solid experience in digital front end design for ASICs Exper...

Job Title: Static Timing Analysis (STA) Engineer Job Overview We are looking for a highly skilled Static Timing Analysis (STA) Engineer to join our ASIC/SoC design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical expertise, problem-solving skills, and cross-functional collaboration. Key Responsibilities Perform Static Timing Analysis (setup, hold, recovery, removal) across all PVT corners and modes. Create, refine, and validate SDC constraints including clocks, generated clocks, false paths, and multi-cycle paths. Drive timing closure during synth...

Looking for an experienced engineer to join a team working on the Logic Design of 3D NAND flash memory. As part of the design team, the individual will be responsible for Logic design development and ownership of the RTL modules. The individual has to exhibit a highly innovative mindset and come up with the solutions for the next technology. Essential duties and responsibilities Understand the NAND architecture and collaborate with other Core/Analog design groups. Drive the design activities and responsible for design of the RTL modules. Timing Closure of the Logic modules. Create the SVA check specs. Work with verification team on the creating and updating test plans. With the cross-functio...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

ROLE & RESPONSIBILITIES Engineer will be responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, Antenna fixing &signal integrity, Power grid analysis atc in ASIC PNR Flow Engineer will be responsible for executing the block level place and route assignments from Netlist through GDS flow Should be able to do full chip implementation of complex SoCs (RTL-to-GDSII), but it is not must. To close STA timing across all corners and modes for blocks and should be able to generate ECO independently. Will be responsible to Work with design teams for closing CTS, IO timing, DFT timing. Responsible f...

The position at Samsung Semiconductor India Research (SSIR) requires a Senior DFT Engineer with at least 5 years of experience in full chip DFT architecture, implementation, timing closure, and post-silicon validation. You will be responsible for various key tasks including: - Scan architecture planning - Pin mixing - Scan compression planning and optimization for pattern volume for SA and TD pattern sets - Scan synthesis - Power optimization techniques in test modes - MBIST architecture planning, repair architectures, insertion, verification - Analog and mixed signal IP testing architecture and verification You will also be involved in: - Timing closure of scan, MBIST, and other test modes ...

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined executi...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL to GDS2 and the challenges posed by advanced technologies. The successful candidate will possess detailed understanding of RTL design, synthesis, static timing analysis, formal verification, PLDRC, clock domain crossing, and low power techniques. Knowledge and experience of microprocessor integration is a definite advantage. Skills/Experience Must have 3 to 15 years of practical experience with details of RTL development (VHDL and/or Verilog) including: functional and structural RTL design, design partitioning, simulation and regression, collaboration wi...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Verification Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :Full chip / Subsystem / Block level Physical verification for deep submicron technology 7nm and belowExpertise in LVS, ERC, PERC, DRC, Antenna, DFM, DensityDeep understanding of ESD analysisGood exposure to BUMP and RDL planningHands on experience with Innovus / Fusion compiler ...

About Tessolve Tessolve is a leading engineering solutions provider, enabling silicon and system companies to accelerate their products to market. With capabilities across silicon design, test engineering, and embedded solutions, we are an end-to-end partner for semiconductor companies globally. Job Description We are looking for a Senior STA Engineer with 8 10 years of hands-on experience in Static Timing Analysis for complex SoC/ASIC designs at advanced technology nodes (7nm, 5nm, or below). The ideal candidate should be technically sound, self-driven, and capable of independently owning STA tasks from RTL to signoff. Key Responsibilities Perform full-chip and block-level static timing ana...

Role Overview: Are you looking for a unique opportunity to be a part of something great at Microchip Technology Inc. As a mixed signal design engineer, you will be responsible for the integration and verification of mixed signal blocks in high-speed IOs in FPGAs. Your role will involve floor planning, place and route, timing closure, and integration of mixed signal blocks in the IOs. Key Responsibilities: - Responsible for the integration of mixed signal blocks in the IO, including generating constraint files, floor planning, place and route of performance critical digital blocks in the IO signal path, and timing closure using STA. - Develop and integrate custom mixed signal circuits for hig...

The position will involve working with a very experienced CPU physical design team. The person is responsible for delivering the physical design of critical CPU units to meet challenging goals for frequency, power, and other design requirements for AMDs next-generation processors in a fast-paced environment with cutting-edge technology. THE PERSON: Engineer with a good attitude, strong analytical skills, effective communication, and excellent problem-solving abilities. KEY RESPONSIBILITIES: Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff Understand the micro-architecture to perform feasibility studies...

As an experienced Physical Design Engineer at Tessolve in Bangalore, you will be responsible for the end-to-end physical design flow from RTL to GDSII at advanced technology nodes such as 7nm, 5nm, or below. Your key responsibilities will include: - Optimizing chip area, power, and performance through floorplanning and partitioning. - Optimizing standard cell placement, buffer insertion, and clock tree synthesis during placement and CTS. - Working on congestion analysis, RC extraction, and static timing analysis for routing and timing closure. - Implementing low-power techniques like clock gating, power gating, and multi-voltage domains for power optimization. - Performing DRC, LVS, and Ante...

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Physical Design Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will engage in a dynamic work environment where you will analyze, design, code, and test various components of application code across multiple clients. Your typical day will involve collaborating with team members to ensure the successful imple...