600 Timing Closure Jobs - Page 7

Skills/Experience: Hands on debugging skills in different physical verification checks like LVS, DRC, ERC, PERC, Antenna, ESD and DFM using Calibre, ICV and Pegasus PV tools Knowledge of basic device physics and PV fixing using various PnR tools like Innovus/ICC2 is required. Working experience in cutting edge technologies such as 3/4/5nm and 7nm process nodes is desired Experience (years) : 4+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

We are looking for bright Physical Design Engineer with excellent analytical and technical skills. This is an excellent opportunity to be part of a fast paced team responsible for delivering High performance design, flows for high performance SoCs in sub-10nm process for mobile space. Job Requirement: 2-5 years hands-on experience of different PnR steps including Floor planning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure. Well versed with high frequency design & advanced tech node implementation In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience. In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks. In depth knowledge of PnR tool knobs/recipes for PPA optimization. Experience in automation using Perl/Python and tcl. Good communication skills and ability & desire to work in a cross-site cross-functional team environment. Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Experience with STA using Primetime and PTPX required Proficient in constraint generation. Experience of multiple power domain implementation with complex UPF/CPF definition required Formal verification experience (Formality/Conformal) Perl/Tcl scripting is required Strong problem solving and ASIC development/debugging skills. Experience with CPU micro-architecture and their critical path. Low power implementation techniques experience. High speed CPU implementation. Place and route tool experience. Constraint management tool and Verilog coding experience Experience (years) : 3+ Year Education Qualification: BTECH/MTECH in Electrical/Electronics/Computer Science Engineering or Equivalent

General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 2-5 years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker Tempus Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

Job Area: Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Qualcomm Noida CPU team is hiring for developing high performance and power optimized custom CPU cores. Individuals to Handle hardening complex HMs from RTL to GDS [ Synthesis, PNR, Timing]. We are excited to add folks with us for the most cutting-edge work. Here, individuals would have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. We offer a fun, creative and flexible work environment, with a shared vision to build products to change the world. Desired experience: 2 years of experience in Physical design, STA. Solid understanding industry standard tools for physical implementation [ Genus, Innovus, FC, PT, Tempus, Voltas and redhawk]. Solid grip from floorplan to PRO and timing signoff along with understanding of IR drop and physical verification aspect. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker Tempus Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language .

Skills/Experience: Proficient in STA timing fixes, ECO and Synthesis of complex SOCs at Sub system level, Block level and Chip level. Tools: Design compiler, Prime time, Tempus Experience (years) : 3+ Year Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

Roles & Responsibilities: STA Synthesis Deep understanding and experience of STA tool PrimeTime /Tweaker/ DMSA (PTECO). Knowledge of timing corners/modes, process variations and signal integrity related issues are required. Experience in timing closure of high frequency blocks & subsystems (Ghz range ) Experience in working full-chip STA closure, defining mode requirements and corners for timing closure. Strong Understanding of DFT modes requirements for timing signoff Good understanding of physical design flow and ECO implementation. Strong understanding of SDC constraints, OCV, AOCV, POCV analysis. Strong TCL/scripting knowledge is mandatory. Strong Experience in Synthesis Constraints development, LINT checks, CDC checks Experience in Formal Verification with Synopsys Formality and / or Cadence Conformal LEC. Strong understanding of ECO cycle, should be able to generate and implement functional Ecos Strong Understanding of DFT modes requirements for timing signoff No. of Vacancies 1 Job Nature Full Time Educational Requirements Bachelors or Masters degree in Electrical Engineering or related field Experience Requirements 8 Bengaluru Salary Industry Standard Other Benefits Work on next-gen automotive, IoT, and processor technologies. Gain full lifecycle exposure from spec-to-tape-out. Collaborate with leading semiconductor experts in a dynamic environment. Competitive compensation with strong career growth opportunities.

Skills/Experience: Hands-on experience in complex SOC/sub-systems implementation using Innovus & Fusion Compiler. Proficient in top-down floorplan and Power Grid methodologies. Experience in signoff convergence, block-level Timing Signoff, ECO generation, and Power signoff. Successful track records of taping out complex IPs & SoCs at 16/10/7/5 nm Power user of Cadence implementation tools, such as Genus, Innovus, Quantus, Tempus, PVS, Voltus . Automation and programming-minded, coding experience in Tcl/Tk/Perl. Education Qualification: B-TECH/M-TECH in Electrical/Electronics/Computer Science Engineering or Equivalent

• Responsible for high performance microprocessor blocks RTL to GDSII implementation • Perform block level synthesis, floor-planning, placement and routing. • Close the design to meet timing, power budget and area. • Implement ECO's to address functional bugs and timing violations. • Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical verification ( LVS,DRC.. etc), Noise analysis, Power analysis and electro migration . Team player with good problem solving skills, communication skills and leadership skills. Preferred technical and professional experience Automation skills in PYTHON, PERL ,SKILL and/or TCL

About The Role Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. ? Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product development from design, selection of materials, low level system software development and verification. Needs by displaying complete understanding of product vision and business requirements Develop architectural designs for the new and existing products Part Implementation of derived solution Debug and Solve critical problems during implementation Evangelize Architecture to the Project and Customer teams to achieve the final solution. Constant analysis and monitoring of the product solution Continuously improve and simplify the design, optimize cost and performance Understand market- driven business needs and objectives; technology trends and requirements to define architecture requirements and strategy Create a product-wide architectural design that ensures systems are scalable, reliable, and compatible with different deployment options Develop theme-based Proof of Concepts (POCs) in order to demonstrate the feasibility of the product idea and realise it as a viable one Analyse, propose and implement the core technology strategy for product development Conduct impact analyses of changes and new requirements on the product development effort ? Provide solutioning of RFPs received from clients and ensure overall product design assurance as per business needs Collaborate with sales, development, consulting teams to reconcile solutions to architecture Analyse technology environment, enterprise specifics, client requirements to set a product solution design framework/ architecture Provide technical leadership to the design, development and implementation of custom solutions through thoughtful use of modern technology Define and understand current state product features and identify improvements, options & tradeoffs to define target state solutions Clearly articulate, document and sell architectural targets, recommendations and reusable patterns and accordingly propose investment roadmaps Validate the solution/ prototype from technology, cost structure and customer differentiation point of view Identify problem areas and perform root cause analysis of architectural design and solutions and provide relevant solutions to the problem Tracks industry and application trends and relates these to planning current and future IT needs Provides technical and strategic input during the product deployment and deployment Support Delivery team during the product deployment process and resolve complex issues Collaborate with delivery team to develop a product validation and performance testing plan as per the business requirements and specifications. Identifies implementation risks and potential impacts. Maintain product roadmap and provide timely inputs for product upgrades as per the market needs Competency Building and Branding Ensure completion of necessary trainings and certifications Develop Proof of Concepts (POCs), case studies, demos etc. for new growth areas based on market and customer research Develop and present a point of view of Wipro on product design and architect by writing white papers, blogs etc. Attain market referencsability and recognition through highest analyst rankings, client testimonials and partner credits Be the voice of Wipro??s Thought Leadership by speaking in forums (internal and external) Mentor developers, designers and Junior architects for their further career development and enhancement Contribute to the architecture practice by conducting selection interviews etc ? Deliver No.Performance ParameterMeasure1.Product design, engineering and implementationCSAT, quality of design/ architecture, FTR, delivery as per cost, quality and timeline, POC review and standards2.Capability development% trainings and certifications completed, mentor technical teams, Thought leadership content developed (white papers, Wipro PoVs) ? Mandatory Skills: VLSI Physical Design Planning. Experience8-10 Years. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Come to Wipro. Realize your ambitions. Applications from people with disabilities are explicitly welcome.

Position: Financial Reporting & Consolidation Support Title: Deputy Manager / Manager Unit: Finance & Accounts Place: Guwahati (RO), Assam Credentials: Chartered Accountant Responsibilities: Preparation of Balance Sheet and Profit & Loss Statement Analysis of Quarterly variances of Balance sheet and Profit & Loss Analysis of Inventory and valuation of finished goods IndAS Accounting of lease, Employee Loan, Borrowings etc Coordinating Internal and Statutory Audits Ensuring timely completion of quarterly and annual audits Monitoring of Capex and capitalization in SAP including WBS Creation etc. Fixed Assets Deprecation calculation through SAP Preparation of Reports on Asset for different stack holder including Audit. Physical verification of Assets of NE Plants

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most innovative companies unleash their potential. Our digital and software technology experts provide unique R&D and engineering services across all industries. Join us for a career full of opportunities where you can make a difference and experience diverse challenges every day. Key Responsibilities: - Timing Analysis & Closure: Perform setup, hold, and skew analysis at Full-Chip, Sub-system, and IP levels to achieve timing closure by resolving violations and optimizing paths. - Constraint Development: Define and validate timing constraints including clocks, I/O delays, and false/multi-cycle paths. Integrate constraints from multiple IPs for hierarchical STA. - Tool Usage & Flow Integration: Utilize STA tools like Synopsys PrimeTime, Cadence Tempus, or equivalent. Integrate STA into the overall design flow and automate processes for efficiency. Job Description: As an expert in STA methodologies, you will provide guidance on setup and hold time analysis, clock domain crossing, and multi-cycle paths for Full Chip, Sub-system, and complex IP timing closure. You will define and implement timing constraints such as clock definitions, input/output delays, and path constraints to ensure accurate timing analysis. Additionally, you will integrate existing timing constraints from various IPs for comprehensive timing analysis. Your deep knowledge of STA tools like Synopsys PrimeTime, Cadence Tempus, or Mentor Graphics" ModelSim will be essential in guiding the integration of these tools into the overall design flow for optimal performance. You will oversee the process of achieving timing closure, address any timing violations, and guide optimizations to meet performance goals. Primary Skills: - Deep Technical Knowledge: Demonstrated in-depth understanding of STA concepts, EDA tools, and methodologies. - Problem-Solving Skills: Strong analytical and problem-solving abilities to address complex timing issues. - Communication Skills: Ability to effectively communicate complex technical concepts to various stakeholders. - Leadership and Mentoring: Experience in leading teams and mentoring less experienced engineers in STA practices. Secondary Skills: - Design Flow Management: Improve execution efficiency through flow automation and other value-added processes. - Cross-Functional Coordination: Collaborate closely with other teams such as RTL design, Physical design, verification, and manufacturing to ensure seamless timing closure of physical design. Educational Qualifications: Bachelors or Masters Degree in Electrical Engineering, Electronics & Communication Engineering, VLSI Design, Computer Engineering, or related fields. Capgemini is a global business and technology transformation partner, helping organizations accelerate their transition to a digital and sustainable world. With a diverse team of over 340,000 members across 50 countries, Capgemini leverages its strong heritage and expertise to deliver end-to-end services and solutions. The group's 2023 global revenues were reported at 22.5 billion, demonstrating its commitment to unlocking the value of technology for its clients.,

At Atos, we are a global leader in digital transformation, employing around 78,000 individuals and generating an annual revenue of approximately 10 billion. As the top cybersecurity, cloud, and high-performance computing provider in Europe, we offer customized end-to-end solutions to various industries across 68 countries. We are at the forefront of decarbonization services and products, dedicated to providing our clients with secure and sustainable digital solutions. Atos operates as a SE (Societas Europaea) and is listed on Euronext Paris. Our mission at Atos is to shape the future of the information space. Through our expertise and services, we facilitate the advancement of knowledge, education, and research in a diverse cultural context, fostering scientific and technological excellence. Globally, we empower our customers, employees, and broader communities to thrive and progress sustainably within a secure information environment. We are currently seeking a skilled FPGA Design Engineer to join our team in Bangalore (Whitefield) with a minimum of 3 years of experience. The ideal candidate should hold a Bachelor's Degree (BE/BTech) or a Master's Degree (ME/MTech) in Electronics. Key Responsibilities: - Design FPGAs for Server Motherboards based on specified requirements - Create detailed design documentation for FPGA implementation - Develop test benches and conduct verification processes - Perform on-board validation of FPGAs Qualifications and Experience: - Educational background in BE/BTech/ME/MTech in Electronics - Minimum of 3 years of experience in FPGA development - Proficiency in FPGA design using Verilog/VHDL - Hands-on experience in FPGA design implementation and verification - Expertise in timing closure and setting constraints - Familiarity with Xilinx, Altera/Intel, and Lattice tools - Strong problem-solving and debugging skills - Ability to collaborate effectively with global teams across different geographies At Atos, diversity and inclusion are integral to our organizational culture. We are committed to fostering a fair work environment for all individuals. Additionally, our company is recognized for its leadership in Environment, Social, and Governance (ESG) criteria. Learn more about our Corporate Social Responsibility (CSR) initiatives and our dedication to sustainability. If you are looking to shape your future in a dynamic and inclusive work environment, consider joining Atos. Choose a career that aligns with your values and aspirations.,

You will be responsible for Logic design, micro-architecture, and RTL coding, with hands-on experience in SoC design and integration for complex SoCs. It is essential to have expertise in Verilog/System-Verilog and knowledge of AMBA protocols like AXI, AHB, APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. Understanding Memory controller designs and microprocessors will be advantageous. Collaborating closely with SoC verification and validation teams for pre/post Silicon debug is a key aspect of this role. Your role will require hands-on experience in Low power SoC design, Multi Clock designs, and Asynchronous interfaces. Proficiency in using ASIC development tools such as Lint, CDC, Design compiler, and Primetime is necessary. An understanding of constraint development and timing closure will be a plus. Experience in Synthesis and knowledge of timing concepts will also be beneficial. Additionally, experience in creating padring and collaborating with the chip-level floorplan team is desirable. You must hold a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 6 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 5+ years of relevant experience or a PhD with 4+ years of relevant experience will also be considered. Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. Reasonable accommodations will be provided upon request to support individuals with disabilities in the hiring process. The company expects all employees to adhere to relevant policies and procedures, including security protocols and confidentiality requirements. Please note that Qualcomm does not accept unsolicited resumes or applications from agencies. Staffing and recruiting agencies, as well as individuals being represented by an agency, are not authorized to submit profiles, applications, or resumes through the Qualcomm Careers Site. For more information about this role, please reach out to Qualcomm Careers.,

As a Silicon Design Engineer 2 at AMD, your role is crucial in executing the front end implementation of sub-blocks or IP. You will be responsible for tasks such as synthesis, LEC, CLP, prelayout STA, and postlayout STA/Timing closure. Collaborating with the design team and PNR teams is essential to achieve closure and execute tasks as per schedule. Your key responsibilities include ensuring quality delivery for synthesis and timing closure, as well as debugging and resolving technical issues efficiently. The ideal candidate for this role should have experience in synthesis and timing closure, with additional experience in LEC and CLP being a plus. Handling blocks with complex designs, high-frequency clocks, and complex clocking should be within your expertise. A complete understanding of timing constraints, low power aspects, and concepts of DFT is necessary, along with the ability to debug and resolve issues effectively. Proficiency in scripting and automation will be beneficial in this role. To qualify for this position, you should hold a Bachelor's degree with 2 years of experience or a Master's degree with 1 year of experience in Electrical Engineering. Your academic credentials will play a significant role in showcasing your eligibility for this role at AMD. Join us at AMD, where together we advance technology and strive for innovation to solve the world's most important challenges. Your contributions as a Silicon Design Engineer 2 will be instrumental in building great products that shape next-generation computing experiences across various domains such as the data center, artificial intelligence, PCs, gaming, and embedded systems. Let's push the limits of innovation and make a difference in our industry, communities, and the world.,

As a Physical Design Engineer with 4+ years of experience, you will be responsible for Netlist2GDSII Implementation including Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, and Physical Verification. Your expertise should cover Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes. Proficiency in programming languages like Tcl, Tk, and Perl is essential for this role. You should have hands-on experience with Synopsys and Cadence tools such as Innovus, ICC2, Primetime, PT-PX, and Calibre. Being well-versed in timing constraints, STA, and timing closure will be crucial for successful execution of projects. Your role will require inspirational leadership, effective communication skills, and the ability to collaborate in a global environment. Overall, your responsibilities will revolve around ensuring the successful implementation of physical design tasks, adhering to project timelines, and maintaining high quality standards throughout the process. Your contributions will play a key role in the development of cutting-edge semiconductor products.,

Qualcomm India Private Limited is seeking a Hardware Engineer to join their Engineering Group. As a Qualcomm Hardware Engineer, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Your role will contribute to launching cutting-edge, world-class products and collaborating with cross-functional teams to develop solutions that meet performance requirements. To be considered for this position, you must have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with at least 4 years of Hardware Engineering or related work experience. Alternatively, a Master's degree with 3+ years of experience or a PhD with 2+ years of experience is also acceptable. The ideal candidate should have hands-on experience with ASIC design timing closure flow and methodology, expertise in STA tools like Primetime/Tempus, knowledge of timing corners/modes, process variations, and signal integrity related issues. Proficiency in scripting languages such as TCL, PERL, PYTHON, and familiarity with backend related methodology and tools are required. Experience in constraint analysis, timing closure of various test modes, clock structure understanding, and clock tweaking analysis is essential. Qualcomm is an equal opportunity employer and is committed to providing accommodations for individuals with disabilities during the application/hiring process. If you require assistance, you may contact Qualcomm's toll-free number or email disability-accommodations@qualcomm.com. It is important for all employees to comply with applicable policies and procedures, including security and confidentiality requirements. Staffing and recruiting agencies are advised that Qualcomm's Careers Site is intended for individuals seeking employment directly with Qualcomm, and unsolicited submissions will not be accepted. For more information about this role, please reach out to Qualcomm Careers.,

As an STA Engineer with at least 4 years of experience, you will be responsible for netlist and constraint sign-in checks and validation. You will be involved in Prime Time constraint generation and development at the top level, full chip level, and clean up. Your expertise in multimode multi-corner timing knowledge will be crucial for timing closure at sub HM/block/top level. You will also be involved in top-level timing closure with sign-off STA in MMMC with Xtalk and OCV. Additionally, you will play a key role in top-level ECO implementation strategy development for netlist, RTL, and timing level changes. Proficiency in scripting languages such as Perl and TCL will be essential for this role. If you are someone who prefers immediate joiner or has a less notice period, this opportunity based in Bangalore/Hyderabad/Pune could be the next step in your career. Regards, Sneha sneha.s@acldigital.com,

Qualcomm India Private Limited is a leading technology innovator that pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to create a smarter, connected future for all. As a Hardware Engineer at Qualcomm, you will be responsible for planning, designing, optimizing, verifying, and testing electronic systems, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems to launch cutting-edge, world-class products. You will collaborate with cross-functional teams to develop solutions and meet performance requirements. You should have a Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or a related field with 4+ years of Hardware Engineering experience, or a Master's degree with 3+ years of experience, or a PhD with 2+ years of experience. We are seeking bright ASIC design engineers with excellent analytical and technical skills to be part of a fast-paced team responsible for delivering Snapdragon CPU design for high-performance SoCs in sub-10nm process for Mobile, Compute, and IOT market space. In this role, you will participate in projects involved in the development of ASICs, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will create design experiments, perform detailed PPA comparison analysis, work closely with RTL design, Synthesis, low power, Thermal, Power analysis, and Power estimation teams to optimize Performance, Power, and Area (PPA). Key Responsibilities: - Develop Place & Route recipes for optimal PPA - Tabulate metrics results for analysis comparison - Complete ASIC flow with low power, performance, and area optimization techniques - Experience with STA using Primetime and/or Tempus - Proficient in constraint generation and validation - Knowledge of multiple power domain implementation with complex UPF/CPF definition - Formal verification experience (Formality/Conformal) - Skills in Perl/Tcl, Python, C++ - Strong problem-solving and ASIC development/debugging skills - Experience with CPU micro-architecture and their critical path - Low power implementation techniques experience - High-speed CPU implementation - Clock Tree Implementation Techniques for High Speed Design Implementation - Exposure to Constraint management tool and Verilog coding experience Qualcomm is an equal opportunity employer committed to providing accessible processes for individuals with disabilities. If you require accommodations during the application/hiring process, please email disability-accommodations@qualcomm.com or call Qualcomm's toll-free number. Qualcomm expects its employees to comply with all applicable policies and procedures, including security and confidentiality requirements. For more information about this role, please contact Qualcomm Careers.,

Qualcomm India Private Limited is seeking a passionate and skilled Hardware Engineer to join our Engineering Group. As a Hardware Engineer at Qualcomm, you will be involved in planning, designing, optimizing, verifying, and testing electronic systems. Your responsibilities will include working on a wide range of systems such as circuits, mechanical systems, Digital/Analog/RF/optical systems, FPGA, and/or DSP systems to develop cutting-edge products. Collaboration with cross-functional teams is essential to meet performance requirements and deliver innovative solutions. To be considered for this role, you should hold a Bachelor's degree, Master's degree, or PhD in Computer Science, Electrical/Electronics Engineering, or a related field, along with 1-3+ years of Hardware Engineering experience. We are particularly interested in individuals with ASIC design expertise and strong analytical skills. This is a fantastic opportunity to contribute to the development of Snapdragon CPU design and high-performance SoCs in the Mobile, Compute, and IOT market space. Key responsibilities include participating in ASIC development projects, focusing on Place and Route Implementation, Timing Closure, Low Power, Power Analysis, and Physical Verification. You will be required to conduct detailed analysis to improve results, optimize Performance, Power, and Area (PPA), and collaborate closely with various teams to achieve project goals. Proficiency in tools such as FC, Innovus, Primetime, Tempus, and languages like Perl, Tcl, Python, and C++ is highly desirable. Your role will involve developing Place & Route recipes for optimal PPA, managing constraints, and ensuring the implementation of low power techniques. Experience with CPU micro-architecture, clock tree implementation, Verilog coding, and formal verification will be valuable assets. Strong problem-solving skills and a dedication to ASIC development and debugging are essential in this role. Qualcomm is an equal opportunity employer committed to providing a supportive and accessible work environment for individuals with disabilities. If you require accommodations during the application process, please contact us at disability-accommodations@qualcomm.com. We expect all employees to adhere to company policies and procedures, including maintaining the confidentiality of proprietary information. Staffing and recruiting agencies are advised not to submit unsolicited profiles, applications, or resumes through our Careers Site. For further inquiries about this position, please reach out to Qualcomm Careers.,

He/She should be able to do top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks. He/She should have worked on 65nm or lower node designs with adv low power techniques such as Voltage Islands, Power Gating and substrate-bias. Provide technical guidance, mentoring to physical design engineers. Interface with front-end ASIC teams to resolve issues. Low Power Design - Voltage Islands, Power Gating, Substrate-bias techniques. Timing closure on DDR2/DDR3/PCIE interfaces. Excellent communication skills. Strong Back ground of ASIC Physical Design: Floor planning, P&R, extraction, IR Drop Analysis, Timing and Signal Integrity closure. Extensive experience and detailed knowledge in Cadence or Synopsys or Magma physical Design Tools. Expertise in scripting languages such as PERL, TCL. Strong Physical Verification skill set. Static Timing Analysis in Primetime or Primetime-SI. Good written and oral communication skills. Ability to clearly document plans. Ability to interface with different teams and prioritize work based on project needs. Role: Physical Design / Layout Engineer Industry Type: Electronic Components / Semiconductors Department: Engineering - Hardware & Networks Employment Type: Full Time, Permanent Role Category: Hardware Education UG: Any Graduate PG: Any Postgraduate

This role is for an STA Engineer to be a key contributor in the synthesis and static timing analysis of complex SoCs. The ideal candidate will have extensive experience in timing closure, I/O constraint development for industry-standard protocols, and hands-on experience with advanced technology nodes. Responsibilities Perform synthesis of complex SoCs at both block and top levels. Develop and write timing constraints for intricate designs, including those with multiple clocks and voltage domains. Lead post-layout timing closure for multiple tape-outs, including handling timing ECOs and achieving STA signoff. Develop I/O constraints for industry-standard protocols such as DDR1/2/3, SDR, LPDDR, Flash, SPIs, Ethernet, USBHS, USBFS, JTAG, Display, etc. Conduct formal verification (RTL-to-netlist and netlist-to-netlist) with DFT constraints. Skills Expertise in synthesis and Static Timing Analysis (STA) . Proficiency in writing timing constraints for complex designs. Hands-on experience with post-layout timing closure , including timing ECOs. Expertise in I/O constraint development for various industry-standard protocols. Strong knowledge of EDA tools such as RC, DC, PT, PTSI. Good understanding of VLSI process and device characteristics . Good understanding of deep submicron parasitic effects and crosstalk effects . Qualifications B.Tech. or M.Tech. with relevant experience in Synthesis, STA. Hands-on experience working on technology nodes like 28nm, 20nm, 14nm, 10nm

Job Description Change the world. Love your job. In this position, you will be working on high-speed mixed-signal communication circuits using state-of-the art process technology, as well as be involved in the design of high performance digital circuits interfacing to leading edge analog circuitry as part of an overall system. Your responsibilities will include RTL coding, simulation, synthesis, timing closure, verification, evaluation, debugging of high-speed communication chips both at the circuit level and behavioral level. As a design engineer, you will prepare test methods and specifications, assist in preparation of application information, data sheets and demo boards. You will develop solutions to complex problems through assessment of various techniques and approaches. You will plan and organize work to ensure timely completion of many independent tasks with general instructions on routine tasks and with detailed instructions on new assignments. This position involves routine communication with a highly talented team of analog and digital design engineers to solve problems and present information as well as active participation in work groups, providing ideas and collaborative teamwork. Qualifications Minimum requirements: 8 years of relevant experience A thorough understanding of digital logic design Familiarity with the Verilog language and simulators A good understanding of analog functionality and exposure to analog IC design methods Ability to solve problems using a systematic approach Preferred Qualifications Experience with System Verilog Demonstrated strong analytical and problem solving skills Strong verbal and written communication skills Ability to work in teams and collaborate effectively with people in different functions Strong time management skills that enable on-time project delivery Demonstrated ability to build strong, influential relationships Ability to work effectively in a fast-paced and rapidly changing environment Ability to take the initiative and drive for results About Us Why TI Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics. We&aposre different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. About Texas Instruments Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, personal electronics, communications equipment and enterprise systems. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com . Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. If you are interested in this position, please apply to this requisition. About The Team TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment. Show more Show less

As an ASIC Design Engineer specializing in UPF and Low Power Design, you will be responsible for owning and driving RTL design for complex digital blocks with multiple power domains. Your role will involve defining, implementing, and validating power intent using UPF 2.0/3.0 for ASIC and SoC designs. Collaboration with verification and physical design teams will be crucial to ensure correct propagation and verification of power intent across the flow. You will work closely with architecture teams to define low power design strategies including power gating, clock gating, and multi-voltage domains. Additionally, analyzing and debugging power-related issues during RTL and gate-level simulations will be part of your responsibilities. It is essential to develop and maintain design documentation such as micro-architecture specs and power intent specifications. Supporting integration and implementation teams in handling low power design constraints and challenges will also be a key aspect of your role. To be successful in this position, you should hold a Bachelors or Masters degree in Electronics/Electrical Engineering or a related discipline. With a minimum of 7 years of ASIC front-end design experience, including at least 3 years focused on low power/UPF design, you should be proficient in RTL coding using Verilog/SystemVerilog with strong design fundamentals. A deep understanding of low power architecture techniques like power gating, retention, isolation, and voltage scaling is required. Hands-on experience with UPF-based flows and power-aware tools from Synopsys, Cadence, or Mentor is essential. Experience in running LINT, CDC, and synthesis with power intent, along with excellent debugging and problem-solving skills, are also necessary. Preferred skills include exposure to DFT constraints and the impact of power intent on scan/ATPG, familiarity with scripting languages like Python/Perl/TCL for automation, and experience in collaborating across global design and verification teams. A working knowledge of timing closure, clock domain crossing (CDC), and logic equivalence checks (LEC) would be beneficial in this role. Joining BOLTCHIP will offer you the opportunity to be part of a cutting-edge semiconductor design team focused on innovation and quality. You will collaborate with top-tier professionals in the low-power design domain and benefit from competitive compensation and opportunities for growth. If you meet the requirements and are excited about this opportunity, please apply by sending your resume to jasmine.h@boltchip.com.,

The position involves working at Samsung Semiconductor India Research (SSIR) on cutting-edge semiconductor technologies like Foundation IP Design, Mobile SoCs, 5G/6G solutions, etc. As one of Samsung Electronics" largest R&D centers outside Korea, the team at SSIR works on diverse projects and technologies. Innovation and creativity are highly valued at SSIR to provide high reliability and performance in delivering world-class products. The responsibilities include physical implementation of complex SOC top designs for mobile application processors, modem sub-systems, and connectivity chips. The role requires expertise in Synthesis, Place and Route, STA, timing closure, and physical signoffs. The candidate should have hands-on experience in physical design, floor planning, pin placement, and high-speed signal planning. Understanding timing, power, and area trade-offs, along with optimization of PPA, is essential. Applicants should be proficient in industry-standard tools like ICC, DC, PT, VSLP, Redhawk, etc., and have scripting knowledge in Perl/Tcl. Experience with large SOC designs, synthesis optimization, low power checking, logic equivalence checking, and physical design verification is required. Familiarity with deep sub-micron designs, SOC issues, hierarchical design, and physical convergence is a plus. The ideal candidate should have a minimum of 5 years of experience in semiconductor design and hold a degree in B.Tech/B.E/M.Tech/M.E. Samsung Semiconductor India Research values diversity and provides Equal Employment Opportunity to all individuals, irrespective of their background or characteristics. Skills and Qualifications: - 5+ years of experience in semiconductor design - Proficiency in physical design tools and methodologies - Strong scripting skills in Perl/Tcl - Knowledge of deep sub-micron designs and SOC issues - Degree in B.Tech/B.E/M.Tech/M.E Please note that Samsung Semiconductor India Research (SSIR) is committed to diversity and Equal Employment Opportunity for all candidates.,