880 Timing Closure Jobs - Page 7

Role Overview: Job Title : PNR Lead Experience : 8+ Years Work location : Bangalore Job Description: Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the de...

Position Summary Role and Responsibilities About Samsung Semiconductor India Research (SSIR) With a wide range of industry-leading semiconductor solutions, we are enabling innovative growth in market segmentsin component solutions, featuring industry-leading technologies inSystem LSI, Memory and Foundry. Our engineers are offered a foundation to work on cutting-edge technologies such as Foundation IP Design, Mobile SoCs, Storage Solutions,AI/ML, 5G/ 6G solutions, Neural processors, Serial Interfaces, Multimedia IPsand much more. As one of the largest R&D centers outside Korea for Samsung Electronics, we take pride in our ability to work on some of the cutting edge technologies. Our engineers...

As key member of the AMD EPYC Server team, the successful candidate will play a significant role in ensuring the quality of next generation EPYC Server SoCs through structural DFT, Automatic Test Pattern Generation (ATPG) and Logic Built-In Self-Test (LBIST) techniques. Primary responsibilities will include Working closely with the Architecture team to understand the DFT Architecture and implementation Interfacing with the Design teams to ensure DFT design rules and guidelines are met Working with the PD team to ensure to correct DFT implementation and closing timing Generating high quality manufacturing test patterns for stuck-at, transition fault models and through the use of on-chip test ...

Key Responsibilities Lead STA and PNR efforts for large, multi-interface, or mixed-signal subsystems Develop and refine STA and PNR methodologies tailored to complex subsystem challenges Drive automation and validation of timing and physical design data across subsystem boundaries Mentor and guide junior engineers, fostering technical growth and knowledge sharing Collaborate cross-functionally to resolve design, timing, and physical implementation challenges Present technical solutions and lead discussions with internal teams and customers on subsystem-level trade-offs and integration

Responsibilities: Lead RTL synthesis and constraints generation/validation for MCU SoCs to meet performance, power, and area targets Develop and implement innovative methodologies and tools to improve design quality and engineering productivity Act as the key interface between frontend and backend design teams, resolving hand-off and timing-related issues Conduct detailed design reviews and provide feedback to peers and junior engineers Collaborate with cross-functional teams to resolve design collateral issues and enhance overall PPA (Power, Performance, Area) Support low power implementation flows and techniques Perform formality checks to ensure RTL vs. netlist equivalence

As an FPGA Engineer at Ceragon Networks, you will be part of a team responsible for transforming ideas into fully developed products. You will play a crucial role in shaping the entire product lifecycle, including internal development of ASIC, RF chip, and FPGA technologies. Your primary focus will be on contributing to the advancement of next-generation backhaul communication systems within Ceragon's FPGA team based in India. Key Responsibilities: - Engage in various aspects of FPGA design activities, such as coding, synthesis, mapping, timing closure, providing verification support, and conducting LAB bring up. - Contribute to FPGA architecture and design efforts for current and upcoming p...

Job Details Job Description: Develops the logic design, register transfer level (RTL) coding, and simulation for FPGAs to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Creates prototypes, simulates models, and specifies systems requirements. Prepares and designs logic diagrams and codes for implementing system design and test specifications. Delivers software models for device level bring up, including user visible functionality, timing, and power. Applies RTL implementation techniques to qualify the design to meet required po...

As a Physical Design Engineer, you will be responsible for the physical design of ASICs. This includes tasks such as floorplanning, clock tree synthesis, placement, routing, timing closure, and physical verification. Your contributions will be crucial to the successful tape out cycles of multiple chips, ensuring the efficiency of the PD life cycle and ECO life cycle. Your expertise in clock-tree synthesis and power-aware PD flows, such as ADM, P&R, will be essential for the project's success. Additionally, your familiarity with PD-STA, timing constraints, and multi-mode, multi-corner timing closure will play a key role in achieving project milestones. **Qualifications Required:** - 3+ years ...

As an experienced Logic Design Engineer at Qualcomm India Private Limited, your role will involve the following key responsibilities: - Hands-on experience in Logic design, micro-architecture, and RTL coding, with a strong emphasis on SoC design and integration for complex SoCs. - Proficiency in Verilog and System-Verilog, along with a solid understanding of AMBA protocols like AXI, AHB, and APB, as well as SoC clocking, reset, debug architecture, and peripherals such as USB, PCIE, and SDCC. - Knowledge of Memory controller designs, microprocessors, and experience in constraint development and timing closure. - Collaboration with the SoC verification and validation teams for pre/post Silicon...

Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwid...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibiliti...

WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ SENIOR SILICON DESIGN ENGINEER (AECG ASIC PD ENGINEER) The Role The position will involve w...

Role: PD Lead Experience: 7+yrs Location: Bangalore Technical Skills: Should be able to handle Full chip PnR (timing/congestion/CTS issues), understanding of IO ring, package support, multi voltage design Deep understanding of the concepts related to synthesis, place & route, CTS, timing convergence, IR/EM checks and signoff DRC/LVS closure Responsible for independent planning and execution of all aspects of physical design including floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM Must have participated in all stages of the design (floor planning, placement, CTS, routing, ph...

Job Description In your new role you will: Contribute to the implementation of highly complex automotive SoC designs in a multi-site organization covering all aspects of Physical Design. Work independently in different phases of the RTL2GDS flow: With focus on (one or many) Synthesis, Constraints and equivalence check, Generation of Floorplans, Placement, Clock Trees, Routing and Power Distribution Network for efficient Timing Closure with Signal Integrity and Physical Sign off including Power Integrity Work with industry standard tools for physical design and signoff with good understanding of scripting languages (shell, perl, tcl) and Make flow. Focus on PPA, define the Partition shapes, p...

We are seeking a highly skilled and experienced Principal Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities: - Own complete STA signoff for ASIC, providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Development & Review activities. - Develop...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: Job Description Responsibilities will include To be strong designer who is able to work independent on one of the peripheral IPs come up with design and microarchitecture solutions guide/mentor juniors engage with external teams to drive/resolve cross team dependencies. Take complete responsibility of one or more project and drive that independently. Being able to make schedule estimates is a plus. People management experience is a plus Skills & Requirements needed 12+ years of work experience in ASIC IP cores design Required: Bachelor's, Electrical Engineering Preferred: Master's, Electrical Engineering K...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Hi, Greetings!! Hiring for Permanent role of Leadsoc technologies Pvt Ltd. Pl ease find the below JD. PD: Experience in Block/SOC level PD Implementation flow. Netlist to GDSII / PD / Implementation flow / PnR / APR Low power design experience Floorplanning, Power planning, Placement, CTS, Routing, Extraction, DFM Congestion and timing analysis, Coming with better QoR Sign-off flow :: STA, DRC/LVS/Antenna/ERC, Power analysis, IR/EM analysis, LEC, ECO (Timing and Functional) Have in-depth knowledge of entire physical design process from RTL to GDS2 generation which includes floorplan, Placement, CTS, Routing and Sign Off ( STA, PV, IR/EM) Experience in ECO implementation Hands on experience i...

Job Description Role Purpose The purpose of the role is to design, and architect VLSI and Hardware based products and enable delivery teams to provide exceptional client engagement and satisfaction. Do Define product requirements, design and implement VLSI and HARDWARE Devices. Constant upgrade and updates of design tools, frameworks and understand the analysis of toolset chain for development of hardware products. Ability to analyse right components and hardware elements to choose for product engineering or development. Ability to conduct cost-benefit analysis and choose the best fit design. Knowledge on end to end flow of VLSI including design, DFT and Verification and Hardware product dev...

You will work on physical design implementation of Optical Network ASICs and will be learning latest technology nodes and developing flow , doing implementation to achieve best in class ASICs , which are optimized for power, performance and area metrics How You Will Contribute And What You Will Learn Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure Perform technical evaluations of IP vendors, process nodes and provide recommendations...

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance ...

As a Physical Design Engineer at ARF Design, you will be responsible for designing and implementing the physical design of integrated circuits. You will collaborate with cross-functional teams to ensure successful design completion. Additionally, you will be performing physical design verification and optimization. Qualifications required for this role: - Minimum of 3 years of experience in physical design engineering - Proficiency in tools such as Synopsys, Cadence, and Mentor Graphics - Strong understanding of timing closure and physical verification methodologies If you are interested in applying for this position, please send your updated resume to divyas@arf-design.com with the subject ...