1082 Timing Closure Jobs - Page 7

As a Hardware Engineer at Qualcomm India Private Limited, your role involves planning, designing, optimizing, verifying, and testing electronic systems to launch cutting-edge products. You will work on a variety of systems including circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems. Collaboration with cross-functional teams is essential to develop solutions and meet performance requirements. Key Responsibilities: - Perform Physical Implementation activities for high-performance Cores for various technologies such as 16/14/7/5nm or lower - Tasks may include floor-planning, place and route, clock tree synthesis, for...

Experience : 8 to 15 years Expertise : Strong understanding of the design convergence cycle, including architecture, micro-architecture, Verification, Synthesis and timing closure. Expertise in managing IP dependencies, as well as planning front-end design tasks. Design and development of high-speed serial IO protocols Implementation of clock rate compensation FIFO, gearbox design for data width, bypass on controller, power gating, low power modes Experience in CPU, bus fabrics, or coherence/noncoherent NOC domains is highly desirable. Skills : Excellent communication and interpersonal skills. Ability to collaborate in a fast-paced, product-oriented, and distributed team environment. Minimum...

STA engineer : Work Experience :: 3 + years Location :: Noida Tool Expertise :: PrimeTime & PT-ECO Technical Expertise :: Block level Timing Constraints enablement & analysis ; Clocking & Data flow understanding ; Well versed in reviewing check_timing and Constraints QoR checks + Constraints Validation understanding ; Able to interact with Implementation team counterparts for block timing closure ; CTS building understanding along with Clock Tree spec review/closure ; Timing ECOs & Final Timing last mile closure at block level ;

7 to 18 years of experience in RTL design skills in VHDL with knowledge of digital signal processing fundamentals Proficient in MATLAB/Simulink for algorithm modeling, fixed-point conversion, and simulation Solid understanding of ORAN domain control and data planes Experience in lower and upper layer protocol implementation in wireless domain Experience in wireless stack packet processing Layer 2/Layer 3 switching etc. Familiarity with verification methodologies desirable (UVM/SystemVerilog preferred) Exposure to FPGA design flow including synthesis, implementation, STA and timing closure Exposure in AMD and Altera tool flows hands on experience on Altera Agilex FPGA or AMD(Xilinx) Zynq RFSo...

There is energy here energy you can feel crackling at any of our international locations. It s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to ...

L&T Technology is looking to hire for STA Engineers. Job Location : Bangalore Detailed JD is below :: JD For STA Engineer-6+ experience Good knowledge of timing closure knowledge for high frequency timing, congestion, and area sensitive designs. Can work closely with FE team for constraints development and constraints cleanup. Work with partitions/block owner to give timing ECO for timing closure. Knowledge of advanced timing closure techniques and methodology Knowledge of industry stanrd tools from Synops or Cadence. Worked on DSM technologies, tsmc 5nm and below experience preferred. Minimum 5+ of relevant experience Good scripting and communication skills

Role : Application Specific Integrated Circuit Design Engineer Industry : Semiconductor Required Technical Skill Set : RTL design skills using verilog, SV, Exposure to complex designs and protocols like PCIe, CXL, ARM subsystem, SATA, DDRx etc. Should have good experience in synthesis and timing closure and low power design flow, partition and upf creation. Should have good experience in unit level testing and DFT concepts Good to have : Low power design and FPGA design and floor plan Desired Experience Range : 12-20 years Location of Requirement : PAN India

Role & responsibilities SEMICONDUCTOR- Physical Design (Mentor) - fulltime Job description Responsibilities: 1. Instant Query handling. 2. Handling LIVE sessions. 3. Providing various weekly assignments, assessments, and tasks to learners and evaluating them on a regular basis. 4. Creating individual real-time mini projects involving learners to do hands-on and helping them update their profiles. 5. Tech support advice and tips for the interview Preparation. 6. Building good rapport with learners and helping them with the smooth learning process in all possible ways. Proficiency in the following tools: VLSI Technology & Design flow Digital Electronics & Fundamentals Cmos Technology & Mosfet ...

As a Digital Physical Design Engineer (G2) at our company, your role will involve contributing to the physical implementation of complex digital integrated circuits. You will work on various stages of the physical design flow, from synthesis to tape-out, ensuring that performance, power, and area targets are met. **Key Responsibilities:** - Execute physical design activities including floorplanning, power planning, place and route, clock tree synthesis, and static timing analysis (STA). - Perform physical verification (DRC, LVS, Antenna) and resolve related issues. - Conduct power integrity analysis (IR drop, EM) and optimize designs for power efficiency. - Participate in design-for-test (DF...

Introduction As a Hardware Developer at IBM, you'll get to work on the systems that are driving the quantum revolution and the AI era. Join an elite team of engineering professionals who enable customers to make better decisions quicker on the most trusted hardware platform in today's market. Your Role And Responsibilities As a Logic designer, you will be responsible for design and development of the POR Boot Engine, Boot security features, and the test & debug infrastructure for very high performance Processors chips. You will be part of the design team which will deliver this critical infrastructure to IBM's Mainframe and POWER processors. Develop the features, present the proposed archite...

As a Physical Design Engineer at Qualcomm India Private Limited, you will be responsible for the physical implementation activities for sub-systems, including floor-planning, place and route, clock tree synthesis, formal verification, physical verification (DRC/LVS), power delivery network, timing closure, and power optimization. You will need to have a good understanding of PD implementation of PPA critical cores and be able to make appropriate PPA trade-off decisions. Additionally, knowledge in timing convergence of high-frequency data-path intensive cores and advanced STA concepts is essential. You should also be proficient in block-level PnR convergence with tools like Synopsys ICC2/Cade...

Tool Expertise :: PrimeTime , PT-ECO, Tempus Technical Expertise :: • Block level Timing Constraints enablement & analysis ; • Clocking & Data flow understanding ; • Well versed in reviewing check_timing and Constraints QoR checks + Constraints Validation understanding ; • Able to interact with Implementation team counterparts for block timing closure ; • CTS building understanding along with Clock Tree spec review/closure ; • Timing ECOs & Final Timing last mile closure at block level ; • Scripting like TCL, Unix etc Role & responsibilities

As a Physical Design Leader at Baya Systems, you will play a crucial role in revolutionizing semiconductor design with chiplet-based, high-performance modular systems. Your responsibilities will include tasks such as floor planning, clock tree synthesis, place-and-route, and timing closure activities for advanced technology nodes. You will collaborate cross-functionally with RTL designers, verification teams, and DFT engineers to ensure successful tape-outs. Your expertise in physical design tasks, EDA tools, timing closure, clock tree synthesis, low-power design methodologies, scripting languages, power integrity, and thermal optimization will be essential in overseeing the physical impleme...

As an experienced ASIC design engineer at Qualcomm India Private Limited, you will be responsible for micro-architecture development, RTL design, and front-end flows. Your key responsibilities will include: - Mirco architecture & RTL development and its validation for linting, clock-domain crossing, and DFT rules. - Working with the functional verification team on test-plan development and waveform debugs at core, sub-system, SoCs levels. - Hands-on experience in constraint development and timing closure. - UPF writing, power-aware equivalence checks, and low power checks. - Supporting performance debugs and addressing performance bottlenecks. - Providing support to sub-system, SoC integrati...

Company Qualcomm India Private Limited Job Area Engineering Group, Engineering Group > Hardware Engineering General Summary 2-5 years of hardware experience involving design and integration of large complex Sub-systems/ SoCs. Strong DSP/Multimedia Domain Knowledge on Video Codecs/Computer Vision/ AI / ML Hardware Architecture is preferred. Experience in micro-architecting & designing complex datapath cores for ASICs/SoCs including AI/ML cores for CV applications Experience with RTL coding using Verilog/VHDL/system Verilog Should have knowledge of AMBA protocols - AXI, AHB, APB, with clocking/reset/debug architectures. Hands on experience in Low power design is required Hands on experience in...

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. Alphawave Semi is expanding its team in Chiplet Ar...

General Summary: Qualcomm GPU team is actively seeking candidates for several physical design engineering positions. Graphics HW team in Bangalore is part of a worldwide team responsible for developing and delivering GPU solutions which are setting the benchmark in mobile computing industry.Team is involved in Architecture, Design, Verification, implementation and Productization of GPU IP COREs that go into Qualcomm Snapdragon SOC Products used in Smartphone, Compute, Automotive, AR/VR and other low power devices. Qualcomm has strong portfolio of GPU COREs and engineers get an opportunity to work with world class engineering team that leads industry through innovation and disciplined executi...

Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibiliti...

Timing analysis, validation and debug across multiple PVT conditions using Tempus. Familiar with Tempus DMMMC flow for STA and logical/physical aware ECO flows focusing timing and leakage optimization. Peripheral timing checks. STA setup, convergence, reviews and signoff for multi-mode (func/scan/atspeed/atspeed exceptions), multi-voltage domain designs. Review of Unconstrained endpoints and check timing reports. Proficient in STA and timing methodologies with good understanding of noise, crosstalk, and OCV effects. Should have worked on both block level and full chip timing closure in 16nm, 5nm and below. Additionally, closely interact with designers/synthesis/PNR team to provide the feedba...

Matillion Requirement/Skill Mandatory Skill combination Matillion, Python, SQL Experience 5 to 12 Yrs JR No 22022 Grade 5A Location All BSL Shift (Please specify Zone/timings) 2:30 PM to 11:30 PM IST Levels of interviews 2 Demand Immediate to 15 days CTC Bracket Upto 28 Lpa Mode of Work (Hybrid/Remote) Hybrid Location - Chandigarh,Dadra & Nagar Haveli,Daman & Diu,New Delhi,Goa,Lakshadweep,Puducherry,Sikkim,North Tripura

At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world's most?innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they?provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are?the same. Job Description Key Responsibilities: Timing Analysis & Closure Perform setup, hold, and skew analysis across Full-Chip, Sub-system, and IP levels. Achieve timing closure by resolving violations...

Job Description Position Overview: We are seeking a highly skilled and experienced Principal Engineer for our Static Timing Analysis (STA) function. The successful candidate will be part to a team of talented engineers responsible for ensuring the timing performance and integrity of our complex semiconductor designs. This role requires a deep understanding of STA methodologies, leadership skills, and a strategic vision to drive continuous improvement in our timing analysis processes. Key Responsibilities: - Own complete STA signoff for ASIC, providing direction and guidance to PnR team for Timing closure & Synthesis report analysis. - Work with IP & Design team for Timing constraints Develop...

As an experienced ASIC design engineer at Qualcomm India Private Limited, you will be responsible for the micro-architecture development, RTL design, and validation for linting, clock-domain crossing, and DFT rules. Your expertise will be utilized in working with the functional verification team on test-plan development and waveform debugs at core, sub-system, and SoCs levels. Additionally, you will play a crucial role in constraint development, timing closure, UPF writing, power-aware equivalence checks, and low power checks. Your support will be vital in performance debugs and addressing performance bottlenecks, as well as providing assistance to sub-system, SoC integration, and chip level...

The Opportunity We're looking for the Wavemakers of tomorrow. Alphawave Semi enables tomorrow's future by accelerating the critical data communication at the heart of our digital world from seamless video streaming to AI to the metaverse and much more. Our technology powers product innovation in the most data-demanding industries today, including data centers, networking, storage, artificial intelligence, 5G wireless infrastructure, and autonomous vehicles. Customers partner with us for mission-critical data communication, our innovative technologies, and our proven track record. Together, we enable the next generation of digital technology. What You'll Do You will be responsible for pre-sal...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. OR Master's degree in Computer Science, Electrical/Electronics Engine...