600 Timing Closure Jobs - Page 3

The role at Ceremorphic AI hardware involves owning and driving the physical implementation of next-generation SOCs. The responsibilities include understanding requirements, defining physical implementation methodologies, collaborating with various teams, implementing and verifying designs, interacting with foundry, and supervising resource allocation and scheduling. The ideal candidate should have hands-on expertise in floorplanning, power planning, logic and clock tree synthesis, placement, timing closure, routing, extraction, physical verification (DRC & LVS), crosstalk analysis, and EM/IR. Additionally, full chip/top-level expertise in multiple chip tape-outs, understanding of SCAN, BIST, and ATPG, strong background in TCL/Perl programming, and expertise in double patterning process nodes are required. Preferably, expertise in Cadence RTL-to-GDSII flow is also desired.,

As a member of our team, you will play a key role in developing custom silicon solutions that drive the future of Google's direct-to-consumer products. You will be at the forefront of innovation, contributing to products that are cherished by millions globally. Your expertise will be instrumental in shaping the next wave of hardware experiences, delivering exceptional performance, efficiency, and integration. In your role within the platform IP team, you will be involved in designing foundation and chassis IPs for Pixel SoCs, including components such as NoC, Clock, Debug, IPC, MMU, and other peripherals. Collaboration with cross-functional teams such as architecture, software, verification, power, timing, and synthesis will be essential as you specify and deliver RTL solutions. Your problem-solving skills will be put to the test as you tackle technical challenges using innovative micro-architecture and low-power design methodologies, assessing design alternatives based on complexity, performance, and power considerations. Google's overarching mission is to organize the world's information and make it universally accessible and useful. Our team leverages the synergies between Google AI, Software, and Hardware to create exceptionally beneficial user experiences. Through our research, design, and development efforts, we strive to enhance computing speed, seamlessness, and power. Ultimately, our goal is to enhance people's lives through technology. Your responsibilities will include defining microarchitecture specifics such as interface protocols, block diagrams, data flow, and pipelines. You will engage in RTL development using SystemVerilog, conducting and debugging functional and performance simulations. Additionally, you will be responsible for performing RTL quality checks, including Lint, CDC, Synthesis, and UPF checks. Participation in synthesis, timing/power estimation, and FPGA/silicon bring-up processes will also be part of your role. Effective communication and collaboration with diverse, geographically dispersed teams will be essential for success in this position.,

You should have 5 to 14 years of work experience in VLSI RTL IP or Subsystem design. Your main responsibilities will include designing and developing CXL and DRAM controller (DDR4/5) based intellectual property, engaging with other architects within the IP level to drive the Micro-Architectural definition, delivering quality micro-architectural level documentation, producing quality RTL on schedule by meeting PPA goals, being responsible for the logic design/RTL coding [in Verilog and/or System Verilog], RTL integration, and timing closure of blocks. You will collaborate with the verification team to ensure implementation meets architectural intent, run quality checks such as Lint, CDC, and Constraint development, debug designs in simulation environments, and have a deep understanding of fundamental concepts of digital design. Preferred skills for this role include strong Verilog/System Verilog RTL coding skills, experience with DRAM Memory Controller design, and knowledge of DRAM standard (DDR4/5) memory. Interface/Protocol experience required are AHB/AXI, Processor local bus, Flash, SPI, UART, etc. Experience with Xilinx/Intel FPGA Tool flow, knowledge of PCIe/PIPE, knowledge of projects with Microblaze, ARM cores, etc., and CXL Protocol knowledge is appreciated. To qualify for this position, you should have a Masters or Bachelors degree in Electronics or Electrical Engineering along with 5 to 14 years of relevant work experience in RTL design & Integration, Synthesis, and timing closure.,

You should have a strong understanding of EDA tools and flows, with specific experience in Tempus/Primetime. Your expertise should include timing closure (STA) and various timing closure methodologies. You will be responsible for pre/post-layout constraint development towards timing closure and collaborating with the design team to establish functional/DFT constraints. Additionally, you will need to integrate IP level constraints and define multi-voltage/switching aware corners. An understanding of RC/C model selection and expertise in abstraction techniques such as Hyperscale/ILM/ETM will be crucial for this role. You will also be expected to perform RC balancing and scaling analysis for full chip clocks and critical data paths. Proficiency in automation using PERL, TCL, and EDA tool-specific scripting is essential. Experience with DMSA at full chip level and developing custom scripts for timing fixes will also be required. Overall, the role demands a deep understanding of timing closure concepts, strong automation skills, and the ability to work closely with the design team to ensure successful implementation of constraints and fixes.,

As an FPGA Architect, you will play a crucial role in leading the design and development efforts across various projects within a dynamic and collaborative environment. Your primary responsibility will involve defining and developing intricate FPGA designs for our Test products. Working closely with a diverse team including R&D Project Managers, Product Architects, Solution Teams, FPGA developers, Software Qualification, and Software Engineers, you will contribute to the innovation of new product offerings while enhancing existing ones. A key aspect of this role will be your ability to effectively collaborate with design teams located in the US and Europe, necessitating strong teamwork skills. Key qualifications for this role include a Bachelor's or Master's degree in Electrical/Electronic Engineering and a minimum of 7+ years of R&D experience specifically in FPGA development with Altera and Xilinx technologies. Proficiency in RTL languages such as VHDL or Verilog, as well as hands-on experience with Xilinx FPGA Tools Design Flow (Vivado, Chipscope, Quartus) and EDA Functional Simulation tools like Synopsys, Mentor, or Cadence are essential. Your ability to adapt quickly to new technologies, protocols, and product segments will be critical, along with expertise in creating self-checking Simulation environments, test bench automation, and writing test cases. Additionally, you will collaborate with system architects to define system architecture, determine FPGA interfaces with other components on the PCA board, and select suitable FPGAs based on project requirements. Experience in timing closure for complex designs and strong written skills for creating various documents such as Product Definitions, Detailed FPGA Designs, and Hardware & Software Interface documents are highly valued. Desirable qualifications include experience with Keysight instruments (Oscilloscope, Analyzer, AWG, BERT), familiarity with protocols like PCI Express, USB, MIPI, Ethernet, DDR, as well as exposure to international and multi-vendor collaborations. Your ability to work effectively with diverse teams, adapt to evolving technologies, and drive innovation will be instrumental in excelling in this role.,

Alternate Job Titles: ASIC Physical Design Manager We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a passionate and accomplished leader with a deep-rooted expertise in ASIC physical design, ready to take on the challenge of managing complex chip projects from conception to tapeout. With 10-15 years of experience in the semiconductor industry, you thrive in dynamic, fast-paced environments and have successfully led teams through multiple tapeoutsat least two of which you have completed independently. Your hands-on knowledge of physical design implementation, timing closure, power optimization, and physical verification using industry-standard tools sets you apart as a technical authority in your field. You bring a holistic understanding of the chip design flow, and your familiarity with both front-end and back-end design methodologies allows you to bridge gaps across the development cycle. Your leadership style is inclusive and motivating, fostering a culture of innovation, collaboration, and continuous learning within your team. You are adept at project and technical management, ensuring milestones are met while maintaining the highest standards of quality and efficiency. Your communication skills are exceptional, enabling you to interact effectively with cross-functional teams, foundry partners, and customers alike. You are driven by the excitement of building next-generation embedded memory products and thrive on solving complex engineering challenges. You value diversity, are committed to mentoring others, and believe in empowering your team to achieve their best. If you are ready to make a tangible impact on cutting-edge silicon validation and design, Synopsys offers the perfect environment for your ambitions. What Youll Be Doing: Leading and mentoring a high-performing team responsible for physical design implementation and tape out of advanced ASICs and test chips. Driving end-to-end chip design flow, from RTL to GDSII, ensuring successful execution of multiple projects. Overseeing timing closure, power optimization, and physical verification using industry-standard EDA tools. Collaborating closely with front-end design, silicon validation, and software teams to deliver robust and efficient solutions. Managing project schedules, resource allocation, and risk mitigation to ensure timely and successful tape outs. Acting as the technical point of contact for foundry interactions and customer communications throughout the design and post-silicon support phases. Championing best practices in design methodology, quality assurance, and continuous process improvement. The Impact You Will Have: Delivering high-quality, high-performance test chips that enable next-generation embedded memory products. Accelerating time-to-market for Synopsys customers by ensuring robust and timely tape outs. Enhancing the companys technical reputation through successful project delivery and customer satisfaction. Driving innovation in physical design methodologies and tool flows to optimize efficiency and reliability. Mentoring and developing the next generation of engineering talent within the organization. Strengthening key partnerships with foundries and customers through proactive engagement and technical leadership. Contributing to the strategic direction of the Silicon Validation Design Team and influencing future product development. What Youll Need: 10-15 years of hands-on experience in ASIC physical design, with at least 5 years in a leadership role. Proven track record of multiple successful tape outs (minimum two completed independently). Expertise in physical design implementation, timing closure, power and physical verification using industry-standard EDA tools. Strong understanding of the complete chip design flow, from RTL to GDSII. Experience in project technical management, people management, and cross-functional collaboration. Knowledge of front-end design and RTL methodologies is a significant plus. Who You Are: Inspirational leader with a collaborative and inclusive approach to team management. Excellent communicator, able to articulate complex technical concepts to diverse audiences. Analytical thinker with strong problem-solving skills and a detail-oriented mindset. Adaptable, proactive, and comfortable making decisions in fast-paced, evolving environments. Committed to continuous learning, mentoring, and fostering a culture of growth and innovation. The Team Youll Be A Part Of: You will join the Silicon Validation Design Team, a passionate group dedicated to designing and developing test chips for embedded memory products. Our unique strength lies in owning the process end-to-endfrom RTL to GDSII tape out and post-silicon supportwhile engaging directly with foundry partners and customers. We pride ourselves on innovation, technical excellence, and a collaborative spirit that drives continuous improvement and customer success. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Alternate Job Titles: Senior Static Timing Analysis Engineer - Lead PrimeTime Application Engineer - Principal STA Engineer We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are an experienced Application Engineer with a deep understanding of Static Timing Analysis (STA) and a passion for driving technological advancements. With a solid background in timing closure, ECO flows, and methodology expertise, you excel in both pre-sale and post-sale capacities. Your familiarity with Synopsys STA tools, particularly PrimeTime, and knowledge of timing corners, modes, and signal integrity issues make you a valuable asset. You possess a BSEE with 5+ years of experience or an MSEE with 3+ years of experience. Your strong technical skills are complemented by excellent verbal and written communication abilities, making you effective in customer-facing roles and collaborative environments. What Youll Be Doing: Driving increased usage of Synopsys' PrimeTime tool through both pre-sale and post-sale activities. - Conducting competitive benchmarks and evaluations to demonstrate the superiority of our products. - Articulating technical advantages to customer design teams and management. - Providing customer training and tapeout support to ensure successful product implementation. - Collaborating with users, R&D, marketing, and sales teams to enhance product features and usability. - Engaging in advanced collaboration initiatives to drive continuous product improvements. The Impact You Will Have: Increasing the adoption and integration of PrimeTime, leading to higher customer satisfaction and retention. - Enhancing customer design processes through expert guidance and support. - Contributing to the development of superior product features based on customer feedback and industry trends. - Strengthening Synopsys market position through effective pre-sale evaluations and demonstrations. - Facilitating successful tapeouts and design completions for customers using PrimeTime. - Driving innovation within Synopsys by collaborating with multiple teams and stakeholders. What Youll Need: BSEE with 5+ years of experience or MSEE with 3+ years of experience in related fields. - Domain knowledge in Static Timing Analysis (STA) and expertise in timing closure and ECO flows. - Experience with Synopsys STA tools, particularly PrimeTime. - Understanding of timing corners, modes, process variations, and signal integrity issues. - Strong knowledge of TCL scripting and familiarity with synthesis, physical design, and extraction methodologies. Who You Are: A proactive and detail-oriented professional with a strong technical acumen. - An effective communicator with excellent verbal and written communication skills. - A collaborative team player who thrives in customer-facing roles. - An innovative thinker who is always looking for ways to improve processes and products. - A dedicated individual with a strong sense of ownership and responsibility. The Team Youll Be A Part Of: You will be part of the dynamic applications engineering team that supports the industry-leading Static Timing Analysis tool, PrimeTime. The team focuses on driving product adoption, providing exceptional customer support, and collaborating with various departments to enhance product features. Together, we work towards empowering our customers and advancing Synopsys' technological leadership. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. Show more Show less

Company: General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical DesignCADengineer, you will build and support the worlds best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles andResponsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science 5+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

General Summary: You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume productionExperience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and/or design-for-test (DFT)Experience with Computer Architecture, Computer Arithmetic, C/C++ programming languages is desiredExposure to DX9~12 level graphics HW development is big plusGood communication skill and desire to work as a team player Required: Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field.Preferred: Master's degree in Computer Science, Electrical Engineering, Information Systems, or related field. ASIC, hardware, design, GPU, OpenGL, DirectX, RTL, Verilog, SystemVerilog Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

About The Role Project Role : Application Lead Project Role Description : Lead the effort to design, build and configure applications, acting as the primary point of contact. Must have skills : SAP FI S/4HANA Accounting Good to have skills : SAP FI S/4HANA Central Finance Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As an Application Lead, you will lead the effort to design, build, and configure applications, acting as the primary point of contact. Your typical day will involve collaborating with various teams to ensure that application requirements are met, overseeing the development process, and providing guidance to team members. You will also engage in problem-solving activities, ensuring that the applications are aligned with business objectives and user needs. Your role will require you to facilitate communication between stakeholders and the development team, ensuring that all parties are informed and engaged throughout the project lifecycle. Roles & Responsibilities:- Liaising with clients to gather necessary requirements and resolve GST-related queries.- Configuring and maintaining GST settings in SAP, including TDS, E-invoice, and other tax-related modules.- Configuring and Testing of GST returns (Document compliance Reporting), To ensure compliance with GST laws and regulations.- Proficient in implementing and handeling third party integration- Join Cluster Tax team, focusing on localization and deployment- he/she will need to have experience in/with SAP tax reporting or tax determination- he/she will support tax localization requirements during the full project lifecycle.- he/she will review build demos and test results against design/- he/she will support country users in organizational change activities and ensure country users know & act on their responsibilities- he/she will perform cutover and hypercare activities- Expected to be an SME- Collaborate and manage the team to perform- Responsible for team decisions- Engage with multiple teams and contribute on key decisions- Provide solutions to problems for their immediate team and across multiple teams- Lead the team in implementing best practices for SAP FI S/4HANA Accounting- Conduct regular code reviews and ensure adherence to coding standards- Stay updated with the latest trends in SAP FI S/4HANA Accounting and provide training to team members Professional & Technical Skills: - Strong knowledge of GST laws and regulations.- Proficiency in SAP FICO with experience in end-to-end implementations.- SAP Experience in baseline configuration for GST India in SAP. Experience in SAP FI, MM, and SD.- Must To Have Skills: Proficiency in SAP FI S/4HANA Accounting- Strong understanding of financial accounting principles- Experience in configuring and customizing SAP FI modules- Knowledge of integration with other SAP modules- Hands-on experience in SAP implementation projects- SAP Tax Accounting- SAP S/4HANA Finance- SAP Tax reporting- SAP Tax determination- SAP ARC/DRC is a plus Additional Information:- The candidate should have minimum 5 years of experience in SAP FI S/4HANA Accounting.- This position is based at our Hyderabad office.- A 15 years full time education is required. Qualification 15 years full time education

About The Role Project Role : Software Development Engineer Project Role Description : Analyze, design, code and test multiple components of application code across one or more clients. Perform maintenance, enhancements and/or development work. Must have skills : Emulation Good to have skills : NA Minimum 5 year(s) of experience is required Educational Qualification : 15 years full time education Summary :As a Software Development Engineer, you will analyze, design, code, and test multiple components of application code across one or more clients. You will perform maintenance, enhancements, and/or development work in a dynamic environment, contributing to the success of the projects. Roles & Responsibilities:- Expected to be an SME, collaborate, and manage the team to perform.- Responsible for team decisions.- Engage with multiple teams and contribute on key decisions.- Provide solutions to problems for their immediate team and across multiple teams.- Lead and mentor junior team members.- Conduct code reviews to ensure code quality and adherence to coding standards. Professional & Technical Skills: - Must To Have Skills: Proficiency in Emulation platform like Palladium/Zebu/Veloce/HAPS.- Strong understanding of SOC Architecture- Experience with debugging using any Emulation Palladium/Zebu/Veloce/HAPS platform.- Hands-on experience with ARM (A/M) architecture.- Knowledge of C language. Additional Information:- The candidate should have a minimum of 5 years of experience in Emulation.- This position is based at our Bengaluru office.- A 15 years full-time education is required. Qualification 15 years full time education

Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checksEnsuring timing correlation between PnR STA and timely feedbacks to PD teamGenerating block level HS session and using Top context from SoC for Block-SoC Interface timing closure Generating timing ECO using Tweaker/PrimeClosure

The analyst will produce high-quality written content that communicates complex market dynamics clearly. Support insights with compelling visuals such as charts and graphs. The candidate will engage regularly with clients through calls, meetings, conferences, and events delivering tailored insights, explaining methodologies, and articulating value propositions. Responsibilities The analyst will conduct power modelling for power markets to deliver short-term market forecasts in client-facing reports. Key considerations in modelling may include, but are not limited to: Capacity build-up. Thermal fuel switching. Temperature-adjusted power demand. Power market mechanisms and price settlement methods. Carbon emission policy, cost, price and new technologies. Power and renewables policies, market trends and key players. Requirements A university degree in economics, business, public policy, or a related field. Familiarity with broader commodity markets, especially in the energy sector. Excellent English communication skills (reading/writing/speaking). Experience building forecasts or models. Knowledge of electricity markets in South and Southeast Asia. Experience with integrated cross-commodity analysis. Strong team players who can work across geographies and time zones. Proven ability to write clearly, visualize data effectively, and present complex analysis in high-level engagements and public forums. Having experience from a similar role is a plus.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. 5+ years hands-on experience of different PnR steps including Floorplanning, Power planning, Placement & Optimization, CTS, Routing, Static timing analysis, Post route optimization, ECO implementation and DRC closure Well versed with high frequency design & advanced tech node implementations In depth understanding of PG-Grid optimization, including identification of high vs low current density paths & layer/via optimization, Adaptive PDN experience In depth knowledge of custom clock tree including H-tree, SPINE, Multi-point CTS, Clock metrics optimization through tuning of CTS implementation. Well versed with tackling high placement density/congestion bottlenecks In depth knowledge of PnR tool knobs/recipes for PPA optimization Experience in automation using Perl/Python and tcl Good communication skills and ability & desire to work in a cross-site cross-functional team environment.

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Min 6+ Years experience

High Performance DSP core Implementation(Synthesis) Senior Lead Engineer General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. Experience: Minimum 4 to 6 years of hands on experience in Synthesis and LEC Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus) , Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field. Experience: Minimum 2 years of hands-on experience in Synthesis and LEC Job Role Should have strong understanding and in-depth knowledge of Physical Synthesis and Synthesis methodologies with leading industry standard tools. Experience with writing timing constraints for synthesis, STA, timing closure and pipelining at different levels for performance optimization and timing closure. Experience in all aspects of timing closure for multi-clock domain designs. Should be familiar with MCMM synthesis and optimization. Should have good understanding of low-power design implementation using UPF. Experience with scripting language such as Perl/ Python, TCL. Experience with different power optimization flows or technique such as clock gating. Should be able to work independently with design, DFT and PD team for netlist delivery, timing constraints validation Should be able to handle ECOs and formal verification and maintain high quality matrix Skill Set Proficiency in Python/Tcl Familiar with Synthesis tools (Fusion Compiler/Genus) , Fair knowledge in LEC, LP signoff tools Proficient in VLSI front end design steps- Verilog/VHDL, Synthesis, QoR optimization & Equivalence Checking Familiarity with standard software engineering practices like Version Control, Configuration Management, Regression is a plus Should be sincere, dedicated and willing to take up new challenges

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience. 5+ years of experience in static timing analysis, constraints and other physical implementation aspects. Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC etc. Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths. Should have experienced about preparing complex ECOs for timing convergence [ across huge set of corners] through Tweaker / Tempus / Physical PT ECOs. Should be aware about the tricks for minimizing power. Experience in deep submicron process technology nodes is strongly preferred. Knowledge of high performance and low power implementation methods is preferred. Willing to push PPA to the best possible extent. Strong fundamentals. Expertise in Perl, TCL language

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU Physical DesignCADengineer, you will build and support the worlds best implementation tools and flows. Your tools and flows will ensure our custom CPUs have industry-leading power, performance and area. Roles andResponsibilities Develop, integrate and release new features in our high-performance place-and-route CAD flow Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain, support and debug implementation flows, and resolve project-specific issues Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and help achieve class-leading PPA. Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science Ten+ years of hands-on experience in place-and-route of high-performance chips - either in a design or CAD role High level of proficiency in Tcl as well as Python Experience with automation Experience with a wide variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Solid understanding of digital design, timing analysis and physical verification Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. . Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. As CPU IntegrationCADengineer, you will enable the floor-planning, physical design (PD), physical design verification (PDV), and signoff of Qualcomms class-leading Oryon CPU cores . You will build and support agile flows and methodologies that enable the first time right development of products with industry-leading power, performance and area. Experience: 6 to 15 years of experience with good academics . Roles andResponsibilities Work closely with worldwide cross-functional teams such as CPU physical design, CPU and SOC Integration, Technology and Central CAD Develop, integrate and release flows and methodologies for floor planning, power planning, pin placement, chip assembly, PDV analysis Develop and maintain unit and system tests to enable correct-by-construction floorplans and physical layouts Architect and recommend methodology improvements to ensure our silicon has the best power, performance and area Maintain and support implementation flows, and resolve project-specific issues Work with EDA vendors to define roadmap and to resolve tool issues Preferred Qualifications: Bachelors/Masters degree in Electrical/Electronics Engineering or Computer Science 10+ years of hands-on experience in development of high-performance chips - either in a design or CAD role High level of programming proficiency ( Python and TCL ). Knowledge of data structures and algorithms Experience with automation Experience with a broad variety of Physical Design tasks - ranging all the way from place-and-route, analysis, timing sign-off and PDV Experience with advanced technology nodes (5nm or lower) Strong user of industry-standard PDV tools such as Siemens/Mentor Calibre Strong user of industry-standard place-and-route tools such as Cadence Innovus Proven track record of managing and regressing place-and-route flows

General Summary: Are you interested in working with a world-class CPU design team? Are you interested in the application of formal methods to the verification of application processors? In contributing to the development of the next generation of formal methodologies in this space? Qualcomm's CPU team has some of the best CPU architects and engineers on the planet, developing the processors that will power the future. Come and join us on this exciting adventure. Sharpen your formal verification skills to their fullest on some of the complex designs ever attempted. Roles and Responsibilities: Work with design team to understand design intent and bring up verification plans and schedules with an eye towards the end-to-end formalization of the refinement from architecture to micro-architecture Define formal verification architecture, develop test plans and build end-to-end formal sign-off environments for Qualcomm CPU components Engage in full-spectrum deployment of model-checking technology to hardware designs including property verification, math proofs, architectural modeling and validation amongst other cutting-edge application areas To be successful in this position you will need: BA/BS degree in CS/EE with 8+ years of practical experience in application of formal methods in hardware or software Strong model checking or theorem proving background/experience in verification of complex systems Experience in writing assertions and associated modeling code in Hardware Description Languages or in proving correctness of architectural specifications using formal methods Working familiarity with model checkers like Jaspergold and VC-Formal or theorem-proving tools such as ACL2 and HOL The ideal candidate will have the following experience: MS/PhD degree in CS/EE; 4+ years of practical experience Strong foundation in formal methods and in their application to hardware specifications and/or implementations Domain knowledge in one or more of these areas: Microprocessor architecture and micro-architecture, instruction set architecture, floating-point math, memory consistency, memory coherency, security architectures Strong software engineering skills with proven ability in automation and proficiency in at least one programming language (C++, Python, TCL etc.) Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.

General Summary: You will be implementing the industry's leading edge graphics processor, specific areas include 2D and 3D graphics, streaming processor, high speed IO interface and bus protocols. In this position, the designer will be responsible for architecture and micro-architecture design of the ASIC, RTL design and synthesis, logic and timing verification. The successful candidate for this position will specify and design digital blocks in our Multimedia Graphics team that will be integrated into a broad range of devices. All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications Bachelor's degree in Science, Engineering, or related field Previous experience in designing GPU or CPU cores and ASICs for Multimedia and Graphics applications in deep sub-micron CMOS processes for volume productionExperience with Verilog/VHDL design, Synopsys synthesis, static timing analysis, formal verification, low power design, test plan development, coverage-based design verification, and/or design-for-test (DFT)Experience with Computer Architecture, Computer Arithmetic, C/C++ programming languages is desiredExposure to DX9~12 level graphics HW development is big plusGood communication skill and desire to work as a team player Required: Bachelor's degree in Computer Science, Electrical Engineering, Information Systems, or related field.Preferred: Master's degree in Computer Science, Electrical Engineering, Information Systems, or related field. ASIC, hardware, design, GPU, OpenGL, DirectX, RTL, Verilog, SystemVerilog Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.

This position is for Physical Design and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Candidate will be responsible to drive die area, performance, power goals for hierarchical blocks/Top. Candidate will work on various stages of physical design implementation which includes floorplanning, IO planning, packager co-design, power grid design, place and route, clock tree synthesis, timing closure, Static/Dynamic IRdrop, physical verification checks. Candidate is expected to have deep understanding and hands-on experience in implementing SOCs with multiple voltage islands, power islands and other power reduction techniques. Candidate should have good understanding of IO planning, package co-design aspects. Candidate is expected to drive flow/methodology activities to improve upon QoR. You are best equipped for this task if you have: Bachelors or Masters degree with specialization in VLSI design. Hands-on experience in physical design and timing closure of SoCs. Experience of industry standard tools for physical design and signoff. Experience in scripting languages (shell, perl, tcl) and Make flow. Understanding of 40nm/28nm technologies and associated physical design challenges. Must be a good team player and should have desire to learn and explore.

STA and Timing closure of Infineon SoCs targeted for IoT and MCU markets. Job Description Responsible for leading STA and Timing Closure of complex, low power SoCs targeted for IOT and MCU markets. Key contribution to timing sign-off methodology development for lower technology nodes (22nm and beyond). Ownership of constraints development for functional/test modes at pre and post layout stage. Opportunity to work on IO timing closure for critical interfaces like Serial Peripherals and External Memory Interfaces. Timing analysis and convergence of large hierarchical design across multiple modes and corners. Interact with RTL and DFT teams on timing feasibility and performance assessment. Work closely with physical design team for timing/SI closure Your Profile B.Tech or M.Tech relevant work experience and specialization in VLSI design. Strong hands-on technical experience in constraints development, timing analysis/closure of SoCs. Experience in low-power synthesis and equivalence checks will be a plus. Expert user of industry standard tools for timing signoff. Experience in scripting languages (shell, perl, tcl) and Make flow. Must be well organized, methodical and detail oriented.