872 Timing Closure Jobs - Page 3

As a Hardware Engineer at Qualcomm India Private Limited, you will be responsible for independent planning and execution of Netlist-to-GDSII. Your role will involve a good understanding of basics of static timing analysis and well-versed with Block level and SOC level timing closure (STA) methodologies, ECO generation, and predictable convergence. You will collaborate closely with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, Physical design, and more. Your exposure to high frequency multi-voltage design convergence and good understanding of clock networks will be essential for this role. Additionally, your circuit level comprehension of t...

As a Physical Design Engineer with full chip implementation expertise, including PnR, STA, and signoff flows, your role will involve working on advanced technology nodes and taking ownership from netlist to GDS-II. Key Responsibilities: - Execute full-chip PnR activities from Netlist to GDS-II - Hands-on experience in Floor-planning, Placement, CTS, Routing, Timing Closure (STA) - Perform signoff checks: FEV, VCLP, EMIR, PV - Work on Physical Synthesis through Sign-off GDS2 file generation - Manage signoff convergence, block-level timing signoff, ECO generation, and power signoff - Knowledge of high-performance and low-power implementation methods - Expertise in ICC2 / Fusion Compiler / Inno...

As a STA Synthesis Engineer at AMD, you play a crucial role in planning and executing the front-end implementation of IPs and ensuring their closure. Your responsibilities include ownership of synthesis, LEC, CLP, prelayout STA, and postlayout STA/Timing closure. You will collaborate with the design team and PNR teams, guiding team members on technical issues. Key Responsibilities: - Responsible for front-end implementation of IPs, including synthesis, LEC, CLP, prelayout STA, and postlayout STA/Timing closure - Collaborate with designers and PNR teams to achieve closure - Plan and execute tasks as per schedule, ensuring quality delivery for synthesis and timing closure - Debug and resolve t...

As a Senior FPGA Design Engineer with 7+ years of experience, you will be responsible for designing high-performance FPGA systems for next-generation computing and connectivity. Your key responsibilities will include: - Designing, architecting, and developing FPGA RTL (VHDL/Verilog) logic for high-speed serial protocols. - Handling CDC, multi-clock domains, SerDes, and timing closure challenges. - Performing FPGA synthesis, place & route, and timing optimization using Xilinx Vivado. - Validating FPGA and board-level issues to ensure reliable high-speed interface performance. - Collaborating with global R&D teams and leveraging AI-assisted tools to enhance development productivity. To qualify...

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationa...

Job Description: Physical Design Should have in depth experience in Floor-planning, CTS, Power routing, place and route, timing closure, DRC and LVS Should have worked on the latest technology nodes (14nm or lesser). Must have experience in Static timing analysis Must have experience in Physical verification and appropriate fixes Should have worked on block level and top-level designs Good to have worked on designs without a customer flow. Strong problem-solving skills and communication skills. Ability to mentor and work closely with junior engineers Relevant Experience Required :- 7+Years Available Locations :- Bangalore, Kochi and Chennai

Are you looking for a unique opportunity to be a part of something great Want to join a 17,000-member team that works on the technology that powers the world around us Looking for an atmosphere of trust, empowerment, respect, diversity, and communication How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization We offer all that and more at Microchip Technology Inc. People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's nationa...

Design, and verify FPGA Zynq ORAN for high-speed. IFFT/FFT blocks and digital filters JESD204B interfaces for high-speed RF transceivers or SoCs. Develop and integrate high-speed Ethernet IP cores (10G/25G/40G) within FPGA-based systems.

We are seeking an exceptional STA Engineer to take a key role in our semiconductor designteam. As STA Engineer you will get opportunity to work with talented and passionate STAengineers and create designs that push the envelope on performance, energy efficiency andscalability. you will lead the STA for cutting-edge high speed and complex large ASIC. Youwill collaborate closely with cross-functional teams to ensure the successful delivery of highquality designs Responsibilities: Responsible for leading a team of STA engineers and close high frequency, lower tech node complex designs. Understand Design Architecture and timing requirements Develop timing constraints SDC and validate Work with ...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: The responsibility includes:-. -Independent planning and execution of Netlist-to-GDSII. -Good understanding of basics of static timing analysis. -Well versed with the Block level and SOC level timing closure (STA) methodologies, ECO generation and predictable convergence. -Should be able work in close collaboration with design, DFT and PNR team and resolve issues wrt constraints validation, verification, STA, Physical design, etc. -Should have good exposure to high frequency multi voltage design convergence. -Good understanding of clock networks. -Circuit level comprehension of timing critical paths in the...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

General Summary: Experience in Logic design /micro-architecture / RTL coding is a must. Must have hands on experience with SoC design and integration for SoCs. Experience in Verilog/System-Verilog is a must. Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset/debug architecture and peripherals like USB, PCIE and SDCC. Understanding of Memory controller designs and microprocessors is an added advantage Hands on experience in constraint development and timing closure Work closely with the SoC verification and validation teams for pre/post Silicon debug Hands on experience in Low power SoC design is required Experience in Synthesis / Understanding of timing concepts for ...

General Summary: As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements. Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Enginee...

Minimum Qualifications: Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience. ORMaster's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience. ORPhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience. PD JD: Thorough knowledge of the ASIC designs Place and Route flow and methodology. Hands-on experience in executing complete PD ownership from netlist to GDS2 including HM level...

Position: PD CAD Engineer (SI80FT RM 3639) Key Responsibilities: Develop and support automated physical design (PD) CAD flows, including floorplanning, placement, and routing optimization. Customize and optimize physical design flows using industry-standard EDA tools (such as Synopsys Fusion Compiler, Cadence Innovus). Collaborate with the design and CAD teams to improve PD workflows, ensuring robust and efficient flow from RTL to GDSII. Implement automation scripts using TCL, Perl, and Python to improve flow reliability and reduce design cycle time. Perform tool evaluations and benchmarking to keep PD flows up-to-date with the latest EDA advancements. Provide documentation, training, and su...

Key Responsibilities: Lead the architecture, design, and integration of SoC-wide clocking networks including clock generation (PLLs, DLLs), distribution, gating, and domain crossing strategies. Define and optimize power-performance-area (PPA) trade-offs for complex clocking and circuit topologies. Collaborate cross-functionally with RTL, physical design, verification, and DFT teams to deliver end-to-end SoC clocking and custom IP. Own the technical roadmap and methodology improvements for clocking, timing closure, and custom circuits. Mentor and technically guide a team of junior and senior designers. Review and approve specifications, schematics, simulations, and post-layout signoff for hig...

Roles and Responsibilities: Perform RTL-to-GDSII implementation including floorplanning, placement, clock tree synthesis (CTS), routing, and timing closure. Work on P&R flows using tools such as Cadence Innovus / Synopsys ICC2 . Handle timing analysis and sign-off using PrimeTime / Tempus . Perform power planning, IR-drop, and EM analysis to meet reliability targets. Execute DFM closure DRC/LVS/ANT checks using Calibre . Implement ECOs for timing, functionality, and metal fixes. Work closely with front-end, verification, and DFT teams to ensure full-chip integration and timing convergence. Optimize Power, Performance, and Area (PPA) for block- and top-level designs. Contribute to flow automa...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 5-8 years industry experience in physical design methodology. Good knowledge and hands on experience in physical design methodology which include logic synthesis,placement, clock tree synthesis, routing . Should be knowledgeable in physical ...

Responsible for high performance microprocessor blocks RTL to GDSII implementation Perform block level synthesis, floor-planning, placement and routing. Close the design to meet timing, power budget and area. Implement ECO's to address functional bugs and timing violations. Team player, with good problem solving and communication skills. Required education Bachelor's Degree Preferred education Master's Degree Required technical and professional expertise 8-10 years of industry experience in physical design methodology. Good knowledge and hands-on experience in physical design methodology, which includes logic synthesis, placement, clock tree synthesis, routing. Should be knowledgeable in phy...

Job Details: Develops the logic design, register transfer level (RTL) coding, and simulation for graphics IPs (including graphics, compute, display, and media) required to generate cell libraries, functional units, and the GPU IP block for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed. Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. Reviews the verification plan and implementation to ensure design features are verified correctly across verif...

Job Description: We are looking for a Lead STA (Static Timing Analysis) Engineer to join our semiconductor design team. The ideal candidate will have extensive experience in ASIC/SoC timing analysis, closure, and signoff , along with deep knowledge of industry-standard tools like PrimeTime or Tempus . You will be responsible for driving timing closure , ensuring robust design constraints, and collaborating with Physical Design, Synthesis, and Signoff teams to deliver high-performance silicon. Roles and Responsibilities: Perform Static Timing Analysis (STA) across multiple corners and modes (MMMC). Debug and resolve setup, hold, recovery, and removal violations. Own and maintain timing constr...

Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performanc...

Performs physical design implementation of CPU designs from RTL to GDS to create a design database that is ready for manufacturing. Conducts all aspects of the CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis. Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking. Analyzes results and makes recommendations to improve current and future CPU microarchitectures closely ...

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challengesstriving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Toge...