1570 Tcl Jobs - Page 11

We’re #hiring – Associate / Lead, Enovia CAD Integration 📍 Location: Chennai, Tamil Nadu, India 🕒 Shift: 2 PM – 11 PM IST (Swing Shift) 📅 Work Mode: Hybrid (2–3 days/week in-office) 💼 Experience: 5–8 Years 🎓 Education: Bachelor’s / Master’s / Doctorate in Engineering or related field 📩 Apply Now: Hr.Guha.EPCS@outlook.com Role Summary Seeking an experienced Enovia 3DExperience professional to lead CAD integration and functional configuration projects. You’ll work closely with architects, PMs, and business teams to translate business needs into scalable PLM solutions. Key Responsibilities Participate in design workshops and provide technical inputs Translate business requirements into IT specifications Develop and execute integration test cases Work with Enovia PLM integrations including CAD & SAP Support BOM & Change Management modules Develop and review technical designs and JPOs Configure 3DExperience apps like Product Structure, 3D Visualization, 3DPlay Must-Have Skills 3–5 years in Enovia 3DExperience solution development Expertise in CAD integrations: Creo, SolidWorks, Inventor, Solid Edge Knowledge of XPDM, PowerBy architecture Familiar with UPS data model and visualization tools Proficiency in Enovia development: JPOs, JSPs, TCL, MQL Experience with Oracle SQL, web services-based integrations

Role Overview: We are seeking a forward-thinking and tech-savvy FPGA Engineer to support the development and implementation of digital technologies across our operations. Key Skills Required: Design, simulate, and implement digital logic circuits on FPGAs using VHDL or Verilog Collaborate with hardware and software teams to integrate FPGA designs into larger systems Develop testbenches and perform functional simulations to verify FPGA designs Perform synthesis, place and route, and timing analysis using industry-standard FPGA toolchains (e.g., Xilinx Vivado, Intel Quartus) Debug and validate FPGA designs on target hardware using oscilloscopes, logic analyzers, and in-system debugging tools Optimize FPGA designs for performance, power, and resource utilization Document design specifications, development processes, and test procedures Stay updated with the latest FPGA technologies and best practices Educational Background: Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field Preferred Experience: 3+ years of hands-on experience in FPGA development and digital design Proficiency in VHDL or Verilog and familiarity with scripting languages like Tcl or Python Experience with FPGA development tools (Xilinx, Intel/Altera, Lattice, etc.) Preferably should have exposure to the latest RFSoCs Strong understanding of digital electronics, timing analysis, and embedded systems To apply, please send your resume to hr@sisirradar.com . Please include " FPGA Engineer " in the subject line.

Job Description : 7+ years of experience in design verification with at least 2+ years in a leadership role. Expertise in SystemVerilog, UVM, assertions (SVA), and scripting languages (Python, Perl, Tcl, etc.). Solid understanding of digital design, SoC architecture, and bus protocols. Experience with simulation and debug tools (VCS, ModelSim, Questa, Verdi, DVE, etc.). Strong analytical and problem-solving skills with a keen attention to detail. Excellent communication, project management, and interpersonal skills. Good Working experience on protocol like , AXI, PCIe, CXL, Ethernet, DMAC, USB, UFS·

Company: Eteros Technologies India Private Limited Eteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad • Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies. • Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies. • We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows. • Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity ----------------------------------------------------------------------------- Job Title/Role: DFT - Senior Engineer/Lead Location : Bangalore/Hyderabad/Ahmedabad Experience Level : 4+ Years Industry : Semiconductors Employment Type : Full-time Job Functions : Engineering ----------------------------------------------------------------------------- Summary Minimum 4 yrs+ experience in DFT implementation Must have worked on Scan Insertion, MBiST, ATPG, Simulations Must have experience with Synopsys DFT tools & Flows Experience in DFT timing closure preferred Experience in multi-die HBM/Memory testing with Synopsys tools preferred Work hands-on on critical tasks of DFT implementation Own the DFT implementation flows, methodologies and execution of SoCs Experience Experience in all phases of the DFT pre and post-Si for large SoCs Implement DFT of SoC/Full-chip-level and/or high-speed cores/blocks Experience in high-speed, low-power, mixed-signal SoC’s is a plus Preferably worked on 5nm/7nm/12nm/14nm/16nm nodes at the major foundries Experience in developing DFT architecture, Test-plan, implementation methodologies Experience in scan insertion, memory-BIST, JTAG/IJTAG, CTL, IEEE 1149.1/1500 wrappers, BSCAN, Compression, ATPG, Simulations, post-Si testing/debug Experience in manual test-point insertion, improve coverage targets, high-compression Experience in hierarchical ATPG, OCC/OPCG, power-aware scan/ATPG methodologies Experience in test-mode constraints generation and test-mode timing closure Experience in patter generation for foundry, post-Si support/debug Thorough understanding of digital design, timing analysis, and physical design process EDA Tools: Cadence (Encounter-Test, Modus-DFT, Tempus, Conformal), Mentor (Tessent tool suite), Synopsys (DFTC, Tetramax, TestMax-DFT, SMS, PTSI) Requirements • BTech/MTech/PhD with in Electrical or Computer engineering • 4-8years of hands-on experience with DFT and test flow with commercial EDA tools for large and complex SOCs • Strong fundamental knowledge of DFT techniques include JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST • Experience with Cadence & Synopsys DFT tools is required. • Strong programming skills in Perl/TCL/C++ and shell scripting is required • Must be able to solve complex problems and independently drive tasks to completion in a timely manner. • Be able to work under limited supervision and take complete accountability. • Excellent written and verbal communication skills What's in it for you • Work on leading edge technologies • An opportunity for career development and growth • Competitive compensation • Medical Benefits and more

Key Responsibilities: Perform timing, power, and signal integrity characterization of standard cells across different PVT corners. Generate Liberty (.lib), CCS, ECSM, and other timing/power models used by synthesis and place & route tools. Develop and validate models for dynamic power, leakage power, and noise . Set up and run characterization flows using tools such as Synopsys Liberate, Cadence Tempus/Modgen, or equivalent. Automate workflows using scripts in Python, Perl, Tcl, or Shell to improve efficiency and reliability. Work with library development and circuit design teams to ensure the quality and completeness of characterized views. Debug and resolve modeling discrepancies, setup issues, or tool-related bugs . Participate in library QA and validation across different design flows and EDA environments. Ensure consistency between layout, schematic, and extracted views for accurate modeling. Contribute to documentation, release management, and customer support as needed. Required Skills & Experience: Bachelor’s or Master’s degree in Electrical, Electronics, or Computer Engineering. 3–10 years of hands-on experience in standard cell characterization . Strong understanding of CMOS device physics, STA fundamentals, and signal integrity . Proficiency in Liberty format, characterization tools , and SPICE simulation . Experience with EDA tools such as Synopsys Liberate, PrimeTime, Cadence Tempus, HSPICE, Spectre, etc. Familiarity with advanced nodes (7nm, 5nm, 3nm, etc.) and FinFET technologies. Solid scripting experience in Python, Tcl, Perl, or Shell for automation. Good understanding of PVT variations, voltage scaling, and multi-corner modeling .

Key Responsibilities: Design and develop custom memory circuits such as: SRAM (register file, cache), ROM, eDRAM, MRAM, RRAM, or embedded Flash. Work across the entire memory development cycle: from specification, circuit design, pre/post-layout simulations, to silicon validation. Design key components including bitcells, sense amplifiers, wordline/bitline drivers, precharge, write drivers, and redundancy logic. Optimize memory circuits for power, performance, area (PPA), yield, and reliability. Collaborate with layout engineers to ensure quality layout and adherence to design constraints. Perform exhaustive corner simulations (PVT, Monte Carlo, mismatch, IR drop, etc.). Interface with technology, verification, DFT, product engineering, and test teams to support silicon bring-up and yield improvement. Contribute to design methodology improvements and automation. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics or Electrical Engineering. 3–10 years of hands-on experience in memory circuit design (SRAM, ROM, or other embedded memories). Strong knowledge of CMOS circuit design, device physics, and transistor-level analysis. Proficiency with EDA tools such as Cadence Virtuoso, Spectre, HSPICE, FastSPICE, and Calibre. Experience with advanced technology nodes (preferably 16nm and below, including FinFET). Solid understanding of yield, variation, IR drop, and reliability considerations in memory design. Familiarity with scripting languages (e.g., Python, Perl, TCL) for automation.

Key Responsibilities: Design and develop standard cells for advanced CMOS technology nodes (e.g., 7nm, 5nm, 3nm). Optimize cells for PPA metrics in coordination with layout and circuit teams. Perform circuit-level simulations (e.g., SPICE) to ensure functionality and robustness. Drive layout implementation with an understanding of design rules, parasitics, and manufacturability. Run and debug various verification flows including DRC, LVS, ERC, and EM/IR checks. Perform characterization and validation of standard cells using industry-standard tools (e.g., Liberate, SiliconSmart, etc.). Interface with physical design, RTL, EDA, and process technology teams to ensure seamless integration. Contribute to automation scripts to improve cell development workflows (Python, TCL, Perl, etc.). Document design methodologies and maintain library QA and release processes. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electrical Engineering, Electronics, or a related discipline. 3 to 10 years of hands-on experience in standard cell circuit design and validation. Strong understanding of CMOS fundamentals and transistor-level design. Experience with industry EDA tools from Synopsys, Cadence, or Siemens. Knowledge of characterization methodologies and tools. Familiarity with technology file setup and design rule constraints. Proficiency in scripting (Python, TCL, Shell, etc.) for design automation.

Key Responsibilities: Define and implement DFT architecture for SoCs and IPs. Develop and integrate scan chains, ATPG, MBIST, LBIST, and boundary scan (JTAG). Work with RTL designers to insert DFT logic and resolve DRC violations. Generate and validate test patterns using tools such as TetraMAX , FastScan , DFT Advisor , etc. Analyze and improve fault coverage and test time reduction. Support silicon bring-up and post-silicon validation of test features. Debug and resolve DFT-related issues during synthesis, simulation, and verification. Collaborate with physical design and verification teams to ensure DFT compliance throughout the flow. Required Skills: 3–10 years of hands-on experience in DFT implementation. Strong knowledge of scan insertion, ATPG, MBIST, LBIST, and boundary scan. Experience with DFT tools: Synopsys DFT Compiler , TetraMAX , Mentor Tessent , FastScan , DFTMAX , etc. Proficient in scripting (TCL, Perl, Python, Shell) for automation. Familiar with RTL coding (Verilog/SystemVerilog) and synthesis flow. Good understanding of timing constraints, STA, and low-power design considerations in DFT. Experience in handling gate-level simulations and testbench development.

About Position: We are looking for a highly skilled Python Automation Engineer with expertise in 5G networks and IMS (IP Multimedia Subsystem) testing to join our dynamic team. The ideal candidate will have hands-on experience in automating test scripts, telecom protocol testing, and ensuring the quality, performance, and resiliency of 5G/4G network functions. As a Python Automation Engineer, you will play a critical role in the validation of IMS architecture, automation of test cases, and performance verification of network functions. Role: Automation Engineer – Python & 5G Core Network Expert Location: Pune, Bangalore Experience: 5+ Years Job Type: Full Time Employment What You'll Do: Develop and maintain automated test scripts using Python, TCL, and BDD for validating IMS functionalities and 5G/4G network features. Design, execute, and improve test cases for telecom protocols such as SIP, Diameter, MAP, SBI, RTP, and DNS. Perform integration, performance, and resiliency testing of IMS applications and 3GPP nodes like HLR, HSS, UDM, SMSC, PGW, SMF, and MME. Build and maintain automation frameworks to streamline test execution and reporting. Conduct manual and automated testing for IMS-based services such as VoLTE, VoWiFi, and RCS. Simulate network traffic and test performance under various conditions using tools like IxLoad, Landslide, and EXFO. Debug and troubleshoot issues at both software and network levels using logs, stats, Grafana, and protocol analyzers like Wireshark. Collaborate with software engineers, network engineers, and DevOps teams to resolve issues and improve system performance. Integrate automated tests into CI/CD pipelines using Kubernetes, Flux/GitOps. Test system resiliency, geo-redundancy, hardware failure scenarios, and conduct chaos testing. Stay up to date with the latest trends in 5G/4G technologies, IMS advancements, and AI tools such as CoPilot and Augment. Expertise You'll Bring: Strong programming skills in Python; experience with TCL and BDD is a plus. Solid understanding of IMS and its components (HSS, PCRF, CSCF). Practical experience with 5G/4G networks and 3GPP nodes. Deep knowledge of telecom protocols: SIP, Diameter, MAP, SBI. Experience with automation tools and frameworks like Robot Framework, Selenium, or pytest. Proficiency with network simulators and analyzers: IxLoad, Landslide, EXFO, Wireshark. Hands-on experience with Kubernetes, GitOps (Flux), and CI/CD pipelines. Strong networking knowledge including switch/router configuration and debugging. Experience in performance/load/stress testing and debugging at scale. Familiarity with monitoring tools like Grafana and bug tracking tools like JIRA. Understanding of telecom standards (3GPP, IETF) and IMS-based services (VoLTE, VoWiFi, RCS). Excellent communication skills and ability to work in a collaborative environment. Benefits: Competitive salary and benefits package Culture focused on talent development with quarterly promotion cycles and company-sponsored higher education and certifications Opportunity to work with cutting-edge technologies Employee engagement initiatives such as project parties, flexible work hours, and Long Service awards Annual health check-ups Insurance coverage: group term life, personal accident, and Mediclaim hospitalization for self, spouse, two children, and parents Inclusive Environment: Persistent Ltd. is dedicated to fostering diversity and inclusion in the workplace. We invite applications from all qualified individuals, including those with disabilities, and regardless of gender or gender preference. We welcome diverse candidates from all backgrounds. We offer hybrid work options and flexible working hours to accommodate various needs and preferences. Our office is equipped with accessible facilities, including adjustable workstations, ergonomic chairs, and assistive technologies to support employees with physical disabilities. If you are a person with disabilities and have specific requirements, please inform us during the application process or at any time during your employment. We are committed to creating an inclusive environment where all employees can thrive. Our company fosters a values-driven and people-centric work environment that enables our employees to: Accelerate growth, both professionally and personally Impact the world in powerful, positive ways, using the latest technologies Enjoy collaborative innovation, with diversity and work-life wellbeing at the core Unlock global opportunities to work and learn with the industry’s best Let’s unleash your full potential at Persistent “Persistent is an Equal Opportunity Employer and prohibits discrimination and harassment of any kind.”

Key Responsibilities: Drive block-level and/or full-chip physical design from RTL to GDSII. Floorplanning, placement, clock tree synthesis (CTS), and routing. Work on static timing analysis (STA) and timing closure. Run and debug physical verification (LVS/DRC/ERC) and power integrity checks (IR Drop/EM). Collaborate with RTL, DFT, synthesis, verification, and packaging teams. Ownership of PPA (Power, Performance, Area) targets and meeting timing goals. Participate in multiple tape-outs and manage block-level signoff closure. Automate and optimize flows using Tcl, Perl, Python, or shell scripting. Keep up-to-date with the latest EDA tools and technology trends. Required Skills & Experience: B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or related field. 4–10 years of experience in physical design with successful tape-outs. Strong expertise in Synopsys/Cadence tools (ICC2, Fusion Compiler, Innovus, PrimeTime, etc.). Deep understanding of digital design concepts, timing, and power trade-offs. Hands-on experience in advanced technology nodes (16nm and below preferred). Experience with scripting languages (Tcl, Python, Perl, Shell). Familiarity with ECO flows, DFT insertion, and low-power design techniques (UPF/CPF). Knowledge of signal and power integrity issues (IR/EM) is a plus.

Logic Design Engineer II Bangalore, Karnataka, India Date posted Jul 21, 2025 Job number 1848527 Work site Up to 50% work from home Travel None Role type Individual Contributor Profession Hardware Engineering Discipline Silicon Engineering Employment type Full-Time Overview Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission. As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. We are looking for an SOC RTL to PD Engineer to join the team. Qualifications Required Qualifications: MS with 2+ years of experience or BS with 4+ years of experience. At least 3+ years of experience applying digital design principles in SOC and/or IP development. Strong Static Timing Analysis background; understanding timing signoff fundamentals. Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus. Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion & demotion. Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints. Understanding in design closure challenges in power and clock domain crossings. Understanding reset and FIFO related design requirements. Preferred Qualifications Experience with FEV and industry standard tools such as Formality and/or Conformal Applied understanding of low power design principles. Highly Proficient in Verilog/System Verilog coding constructs. Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting) Strong understanding in clock crossing techniques Strong understanding in IJPF (Low power intent). Ability to write scripts using Perl, TCI, Python etc. Familiarity with Industry standard interface protocols is a plus. Good verbal and written communication skills. Responsibilities Ensure high quality deliverables from RTL to Physical Design Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results Create, analyze, and maintain timing constraints/SDCs Analyze and drive UPF solutions for low power checks Drive RTL to Synthesis FEV clean Collaborate with RTL and Physical Design team to address design feedback and drive quality Benefits/perks listed below may vary depending on the nature of your employment with Microsoft and the country where you work.  Industry leading healthcare  Educational resources  Discounts on products and services  Savings and investments  Maternity and paternity leave  Generous time away  Giving programs  Opportunities to network and connect Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations.

Category Application Development and Support Location Hyderabad, Telangana Job family Software Engineering Shift Evening Employee type Regular Full-Time Overall 3-5 years working in IT, as Middleware IT professional working with Infor’s Cloverleaf Suite (Cloverleaf Interface Engine, Secure Courier, Global Monitor, Secure Web Services) Cloverleaf Level 2 certification or comparable experience required. Minimum 3 years of TCL programming Design, develop, and unit test Infor’s Cloverleaf Suite of applications using agile and waterfall methodologies. Troubleshoot and debug services using the Cloverleaf’s tools and logs provided with the Cloverleaf Suite of products. Strong understanding and experience in various versions of HL7 v2.x, v3, XML and JSON structures. Should have experience in end-to-end monitoring of message tclproc’s and xlates. Understanding of Firewalls to request firewall rules. Knowledge of F5 load balancers and DNS networking is required. Should have some experience with tcp/ip sockets and ports, FTP, sFTP, and HL7 MLLP. Should have experience of working in Healthcare Industry (or similar) to understand the data security requirements like PCI/HIPPA/SOX/PHI etc. Web Service programming using TCL and Cloverleaf to handle SOAP and RestFul interfaces Good understanding of the FHIR standard Working knowledge of the Infor Cloverleaf FHIR server and service a plus View more

Job Titles: ASIC Emulation Sr. Architect We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: You are a visionary and accomplished ASIC emulation expert with a passion for leading teams and solving complex challenges in digital design. Your career has been marked by a commitment to innovation, technical excellence, and driving results in fast-paced, collaborative environments. You have a proven track record of architecting and optimizing emulation solutions for high-performance, mixed-signal IPs, and thrive on guiding teams to deliver robust, scalable verification environments. Your leadership style fosters trust, encourages open communication, and empowers engineers to achieve their best. You are adept at bridging the gap between design and verification, and you excel at translating technical requirements into actionable plans. Your expertise extends to regression management, test coverage analysis, and the development of emulation-friendly models, ensuring projects are delivered on time and to the highest quality standards. You are customer-focused, comfortable representing your work to both internal stakeholders and external partners, and committed to continuous learning and professional development. Your ability to mentor, inspire, and innovate makes you an invaluable asset to any organization. If you are excited by the prospect of shaping the future of emulation at the forefront of semiconductor technology, you belong at Synopsys. What You’ll Be Doing: Lead the integration of verification environments and RTL into the Zebu emulation platform for seamless operation. Execute emulation tests, debug issues, and optimize environments for improved performance and reliability. Manage and analyze regression results to identify issues and ensure comprehensive test coverage. Collaborate with design and verification teams to align requirements and resolve bottlenecks effectively. Innovate and refine emulation methodologies to enhance scalability, efficiency, and reliability. Define requirements on simulation environments to enable mapping to emulation environments. Define emulation targets and test plans to be prioritized for emulation. Develop emulation-friendly Real Number Models (RNM) for mixed-signal IPs to expedite digital and firmware verification. Define emulation planning across the IP titles, report status, risks, and mitigations to emulation plan. Standardize emulation flows across PHY and controller IPs, working closely with Synopsys’ Zebu team. Represent Synopsys on customer calls regarding emulation validation strategy, plans, and progress. Lead a team of emulation engineers, providing direction, mentorship, and technical leadership. The Impact You Will Have: Drive the integration of cutting-edge verification environments into emulation platforms, ensuring high performance and reliability. Enhance the efficiency of the emulation process, leading to faster and more reliable verification of complex designs. Ensure comprehensive test coverage through meticulous regression analysis and issue identification. Collaborate effectively with design and verification teams to optimize emulation strategies and resolve bottlenecks. Innovate emulation methodologies, contributing to the scalability and efficiency of verification processes. Develop and implement emulation models that accelerate the verification of mixed-signal IPs. Standardize emulation processes across various IPs, promoting consistency and best practices. Represent Synopsys in customer interactions, showcasing expertise in emulation validation. Lead and mentor a team of emulation engineers, fostering a collaborative and innovative environment. What You’ll Need: 20+ years of hands-on emulation experience on platforms such as Palladium, Veloce, or Zebu. Extensive knowledge of design mapping, testbench mapping, and transactor development for emulation environments. Expertise in hardware/software debug solutions tailored to emulation, with excellent debugging skills in functional and gate-level simulations. Strong programming skills in object-oriented languages such as C++, Java, or Python, and scripting languages like PERL, TCL, and Shell scripts. Hands-on experience with verification metrics, including functional, code, and assertion coverage. Comprehensive knowledge of protocols, including PCIe, I2C, and Ethernet packet headers. Familiarity with multi-domain verification environments, SystemVerilog DPI, and collaborative workflows using Git, Jenkins, or CI/CD pipelines. Strong analytical and problem-solving skills, with a proven ability to mentor junior engineers and collaborate effectively. Who You Are: A strong leader with excellent communication and mentoring skills. Innovative and committed to continuous improvement. Detail-oriented with a strategic mindset. Collaborative, with the ability to work effectively in a team environment. Passionate about technology and eager to work on cutting-edge projects. The Team You’ll Be A Part Of: You will be part of a dynamic team focused on driving innovation and excellence in the emulation of state-of-the-art protocol IPs. The team collaborates closely with design and verification teams to ensure the successful integration and optimization of verification environments. As a key member of this team, you will lead and mentor a group of talented engineers, fostering a culture of collaboration and innovation. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

Meta is hiring talented individuals to join our Infrastructure organization as ASIC Frontend Implementation Engineers (RDC/CDC). In this role, you will play a critical part in designing and developing efficient System on Chip (SoC) and IP for data center applications. As an ASIC Frontend Implementation Engineer, your primary focus will be on the front-end implementation process and static verification tools, transforming RTL designs into optimized netlists. You will utilize your expertise in RTL Lint, CDC analysis, timing constraints, and synthesis to ensure seamless integration of various components to build efficient System on Chip (SoC) and IP for data center applications.By joining our team, you'll have the opportunity to contribute to the development of cutting-edge technology that powers Meta's infrastructure. ASIC Engineer, Frontend Implementation RDC/CDC Responsibilities: Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power Developing Automation scripts and Methodology for all Front End (FE)-tools including (Lint, CDC, RDC,) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in static verification tools Experience with Lint, Clock Domain & Reset Domain crossing Knowledge of SOC Integration (Clocking, Reset, PLL, etc) Knowledge of front-end ASIC flows Experience with RTL design using SystemVerilog or other HDL Successful candidates must remain in role in the same team in India for a minimum period of 24 months before being eligible for transfer to another role, team or location Preferred Qualifications: Scripting and programming experience using Perl/Python, TCL, and Make Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Experience with SOC Design Integration and Front-End Implementation Experience with developing structural rule based checks for RTL & Netlist Experience with Netlist-CDC Analysis and improving MTBF Knowledge of Timing/physical libraries, SRAM Memories About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Job Description/Requirements ABOUT THE COMPANY Tatu City is part of Rendeavour, Africa’s largest urban land developer with over 30,000 acres of visionary projects in the growth trajectories of large cities in Kenya, Ghana, Nigeria, Zambia and Democratic Republic of Congo. Rendeavour’s vision goes beyond alleviating what is a self-evident problem – that of stifling urban congestion and a dearth of quality housing and commercial property in Africa. Rather, we aim to help create the infrastructure – the living and working spaces, communities, schools and hospitals – that will help sustain and accelerate Africa’s economic growth, meet the aspirations of Africa’s burgeoning middle classes, and serve as a catalyst for further urban development. Job Summary RequirementsSkills and Experience:Must have a BSc in Civil and Structural Engineering.Must be an EBK (Engineers Board of Kenya) registered engineer.Must have 8 plus years of professional experience.Must have experience in carrying out diverse projects including Industrial projects, low, medium and high-density projects, mixed use commercial projects, among others.Basic understanding of the different types of construction contracts.Track record of successfully carrying out projects from inception all the way to completion.Ability to drive quality assurance and quality control for construction projects. Responsibilities Prepare client briefs, designs and reports of civil and structural drawings for DCC and any other assigned projects.Undertake day-to-day peer review of civil, structural, and MEP development plans on behalf of the DCC.Undertake quality control by ascertaining the integrity of building materials, and developing and interpreting design calculations regarding pressures, loads and stresses.Brief clients, developers, contractors, and other development interested parties on the TCL development standards, development control measures, and the development plans approval procedures.Undertake effective consultation with customers and contractors before and during all construction works regarding their property.Undertake regular site visits to perform technical inspections and ensure adherence to the approved development plans. Monitor changes to scope during the development cycle and re-evaluate plans and resources accordingly.Assist in providing technical guidance and supervising site construction activities. This includes making recommendations on required building materials, equipment and tools to ensure timely implementation.Liaise with the relevant government agencies/regulators to ensure timely approval of development plans and issuance of licenses.Develop strategies, plans, and monitoring policies and procedures within appropriate internal controls to maintain a high-level development standard and ensure an update of development strategies in line with industry regulations. Required Skills Site engineering, Construction management, Collaboration, Teamwork, Ability to coordinate Required Education Bachelor's degree

If you are passionate towards crafting customer success and interested to build exciting career working in cutting edge technology with world’s largest EDA company, then this role meets your requirement. You will get an opportunity to work on latest Synopsys implementation technologies (Machine Learning, Physical Synthesis , Multi-Source CTS, etc.) to solve complex PPA challenges faced by Synopsys customers. Working on benchmarks to displace competition implementation solutions. Working on developing and debugging RTL-GDS implementation methodologies and flows. Providing technical solutions by identifying the design and/or EDA tool issues and provide an appropriate solution for customers. Effectively translate the findings into requirements for R&D to improve both tool behavior with enhancements as adaptive long-term solutions. Involved in deployment of new technologies on latest EDA versions and enable customers to migrate to newer versions achieving best PPA. Coming up with a proactive understanding of customers' pain point and coming up with innovative solutions to address the same. Closely interacting with Synopsys R&D team and product development team to develop future technologies. This role requires you to act as customers advocate while talking to inhouse R&D and be a product brand ambassador while engaging with customers. The candidate must have good exposure to methodology changes to achieve targeted PPA metrics for complex designs. At least 2 years of experience in Physical Implementation RTL-GDS. Experience in autonomously debugging and resolving synth & PnR implementation challenges. Proficiency in Synopsys implementation tools is an advantage. The individual must be self-motivated and dedicated with strong debugging skills. Requires proficiency in scripting (tcl / unix / perl). Excellent communication skills including the ability to interface with customers and business unit personnel are essential.

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. You Are: As an ideal candidate for the ASIC Digital Design Engineer, Senior role, you are a highly motivated and innovative individual with a deep understanding of ASIC development flow. You possess a strong theoretical and practical background in high-speed serializer and data recovery circuits. You are someone who thrives in dynamic environments and embraces the challenges that come with constant technological changes. You are self-motivated, proactive, and able to balance good design quality with tight deadlines. Your excellent communication skills enable you to interact seamlessly with different design groups and customer support teams. You are known for your ability to resolve issues creatively and exercise independent judgment in selecting methods and techniques to obtain solutions. You are a team player who can produce excellent results both as an individual and as part of a team. What You’ll Be Doing: Supporting development and verification of digital designs for next-generation NRZ and PAM-based SerDes products. Setting up and Running lint/cdc/rdc checks and synthesis flow. Working with Verilog and VCS to ensure design accuracy. Defining synthesis design constraints and resolving STA issues. Collaborating with mixed-signal engineers to deliver high-end mixed-signal designs from specification development to functional and performance tests. Setting up flows/process for quality checks, release management for different front-end flows. Interacting with Application Engineers for customer support and resolving technical issues with Analog and P&R teams. The Impact You Will Have: Contributing to the development of cutting-edge SerDes products that lead the industry. Enhancing the performance, power, and size efficiency of our silicon IP offerings. Enabling rapid market entry for differentiated products with reduced risk. Driving innovation in high-speed digital design and data recovery circuits. Supporting the creation of high-performance silicon chips and software content. Collaborating with a world-class team to solve complex design challenges. What You’ll Need: BSEE or MSEE with a minimum of 4 years of experience in digital design and front-end flows. Proficiency in running lint/cdc/rdc checks and synthesis flow. Experience in coding, verifying verilog and system verilog design. Experience of working with minimum supervision and owning and delivering for Front end activities in IP/SOC Experience of leading technically for Front end activities. Knowledge of digital design methodologies, DFT insertion, synthesis constraints, and flows. Scripting experience in Shell, Perl, Python, and TCL (preferred). Who You Are: Excellent communicator with the ability to interact with diverse teams. Self-motivated and proactive, with a strong attention to detail. A creative problem-solver who can think independently. Capable of working under tight deadlines while maintaining high-quality standards. A team player who can contribute effectively both individually and collaboratively. The Team You’ll Be A Part Of: Join our highly experienced mixed-signal design and verification team, where you will work alongside experts in digital and mixed-signal engineering. Our team is dedicated to developing innovative solutions for the next generation of high-speed SerDes products, providing continuous training and opportunities for growth. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.

ASIC Design Verification Engineer, Staff The candidate will be part of the R&D in Solutions Group, India. The position offers learning and growth opportunities. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in a role that will include IP verification using the latest verification methodology flows. Job Description The candidate will be part of the DesignWare IP Verification R&D team at Synopsys. He/She will be expected to specify, design/architect and implement state-of-the-art Verification environments for the DesignWare family of synthesizable cores and perform Verification tasks for the IP cores. He/ She will work closely with RTL designers and be part of a global team of expert Verification Engineers. Will be working on the next generation connectivity protocols for Commercial, Enterprise and Automotive applications Job role will have a combination of Test planning, Test environment coding both at unit level and system level, Test case coding, debugging, FC coding and analysis, meeting quality metric goals and regression management. Requirements: Must have BSEE in EE with 4 to 8+ years of relevant experience or MSEE with 3 to 7+ years of relevant experience in the following areas: Must have experience in developing HVL (System Verilog) based test environments, developing, and implementing test plans, implementing, and extracting verification metrics such as functional coverage. Must have strong HVL coding skills for Verification and be hands-on with one or more Industry standard simulators such as VCS, NC, MTI used in Verification and waveform based debugging tools. Exposure to verification methodologies such as VMM/OVM/UVM/ is required. Exposure to Formal verification methodologies is highly desirable. Knowledge of one or more of protocols: MIPI-I3C/UFS/Unipro, AMBA (AMBA2, AXI), SD/eMMC, Ethernet, DDR, PCIe, USB Familiarity with HDLs such as Verilog and scripting languages such as Perl, TCL, Python is highly desired. Exposure to IP design and verification processes including VIP development is an added advantage. There will be strong focus on functional coverage-driven methodology. So, the corresponding mindset is a must. It is essential that the individual has good written and oral communication skills and can demonstrate good analysis, debug and problem-solving skills and show high levels of initiative. This position requires prior industry experience and is not open for college fresh grads. Location: Bengaluru

As an engineer of NVIDIA's Software Quality Assurance (QA) team, you will play a crucial role in orchestrating the Software Quality processes for CAD tools and flows that support all semiconductor products. You will be working on infrastructure and software used to test complex semiconductor devices, including developing in-house tools for Design for Test (DFT) using languages like C++, Python, and TCL. This role requires a diverse skill set and a willingness to tackle challenges head-on. Your responsibilities will include providing support for testing and validation processes, architecting automated and customizable Software Quality processes, crafting test plans and cases, automation of testing, maintaining regression testing frameworks, performing code reviews and testing, and ensuring the delivery of high-quality, bug-free software applications. You will collaborate closely with team members to provide DFT and DFP methodologies for cutting-edge chip designs and support the development of tools using C++, Python, and TCL. To be successful in this role, you should have a BS or MS in Electrical Engineering, Computer Science, or Computer Engineering with a minimum of 4 years of experience in a Software QA role. You should possess knowledge of various software testing techniques, code reviews, testing tools such as TestRail or Zephyr, CI/CD tools like Jenkins and GitLab, and have skills in Python, TCL, or C++. Experience with defect tracking tools like JIRA and lab software and hardware support is also essential. To stand out, additional knowledge or experience with DFT, BDD processes, Verilog, ASIC design principles, and logic cells will be advantageous. NVIDIA is known for being one of the most desirable employers in the technology industry, attracting forward-thinking and talented individuals. If you are a creative and autonomous professional looking to make an impact, we encourage you to apply and join our diverse team today.,

You are a highly skilled and experienced engineer with a deep understanding of synthesis, timing closure, power optimization, and constraints management. Your expertise includes working on advanced nodes under 5nm and proficiency in low-power, high-performance design. Familiarity with RTL, DFT, LDRC, TCM, VCLP, and PTPX gives you an edge in tackling complex design challenges. Your ability to use scripting languages such as TCL, Perl, and Python is a valuable asset. Holding a BS or MS in Electrical Engineering or a related field with over 9 years of relevant experience, you are well-equipped to drive continuous technological innovation and transform the future. Your responsibilities will include developing innovative methodologies for implementing high-performance CPUs, GPUs, and interface IPs. You will utilize advanced technologies and tool features to enhance quality of results and streamline the implementation process. Contributing to the development and implementation of power, performance, and area (PPA) methodologies for complex IPs will be a key part of your role. Working with industry-leading Synopsys tools such as RTLA and Fusion Compiler, you will solve critical design challenges and collaborate with a global team to stay ahead of technological advancements. Your impact will be significant as you advance the state-of-the-art in high-performance core and IP implementation, enhance the performance and efficiency of Synopsys" design methodologies and tools, and enable the development of cutting-edge semiconductor technologies at advanced nodes. You will contribute to the successful delivery of high-quality, high-performance IPs to the market, drive innovation, and support Synopsys" mission to lead in chip design, verification, and IP integration. To excel in this role, you will need deep knowledge of synthesis, timing closure, power optimization, and constraints management, along with experience in low-power, high-performance design at advanced nodes under 5nm. Proficiency in RTL, DFT, LDRC, TCM, VCLP, and PTPX, as well as familiarity with scripting languages such as TCL, Perl, and Python, are essential. A BS or MS in Electrical Engineering or a related field with 9+ years of relevant experience will further strengthen your qualifications. You are a detail-oriented and innovative engineer with a passion for pushing the limits of technology. Your problem-solving skills, ability to optimize design processes, and effective collaboration with a global team set you apart. Motivated by continuous improvement and making a significant impact in the field of semiconductor design, you are well-suited to join the growing global team at Synopsys dedicated to advancing high-performance core and IP implementation.,

You are a Data Integration & Modeling Specialist responsible for developing common metamodels, defining integration specifications, and working with semantic web technologies and various data formats. Your expertise will contribute to enterprise-level data integration and standardization initiatives. Your key responsibilities include developing common metamodels by integrating requirements across systems and organizations, defining integration specifications, establishing data standards, and developing logical and physical data models. You will collaborate with stakeholders to align data architectures with organizational needs and industry best practices. Additionally, you will implement and govern semantic data solutions using RDF and SPARQL, perform data transformations and scripting using TCL, Python, and Java, and work with data formats like FRL, VRL, HRL, XML, and JSON to support integration and processing pipelines. Documenting technical specifications and providing guidance on data standards and modeling best practices are also part of your role. The qualifications required for this position include: - 3+ years of experience in developing common metamodels, preferably using NIEM standards. - 3+ years of experience in defining integration specifications, developing data models, and governing data standards within the last 8 years. - 2+ years of recent experience with Tool Command Language (TCL), Python, and Java. - 2+ years of experience with Resource Description Framework (RDF) and SPARQL Query Language. - 2+ years of experience working with Fixed Record Layout (FRL), Variable Record Layout (VRL), Hierarchical Record Layout (HRL), XML, and JSONodeling Specialist. This is a contract position located remotely with a duration of 6 months. Join us to bring your technical expertise and collaborative mindset to drive successful data integration and modeling initiatives.,

As a senior software engineer at AMD, you will play a crucial role in driving and enhancing AMD's capabilities to deliver cutting-edge technologies to the market. You will work collaboratively with a dynamic team to develop comprehensive and highly effective software for new technology and product introduction projects. Your innovative mindset and strong problem-solving skills will be essential in validating new software features before releasing them to customers. Your responsibilities will include contributing to a high-functioning feature team, collaborating with multiple teams to deliver key planning solutions, and participating in the design and implementation of future architecture for a highly scalable and durable system. You will closely work with development teams and project managers to ensure successful execution and drive results. The ideal candidate for this role possesses a Bachelor's or Master's degree in Computer/Software Engineering, Computer Science, or a related technical discipline. You should have a solid understanding of digital design and simulations basics, RTL coding skills (VHDL, Verilog & System Verilog), and experience in FPGA design flow and tools such as Synthesis, Simulation, and implementation. Knowledge of ASIC/FPGA verification techniques, Xilinx Vivado Design Suite, and simulators like XSIM, Questa, Modelsim, VCS is preferred. Additionally, hands-on experience with scripting languages like tcl, pearl, and python, as well as advanced debugging skills in a software environment, will be beneficial for this role. If you are passionate about technology, possess leadership skills in technical areas, and thrive in a fast-paced environment, we invite you to join our team at AMD and be part of advancing innovative solutions that shape the future of computing.,

If you are looking for a challenging and exciting career in the world of technology, then look no further. Skyworks is an innovator of high performance analog semiconductors whose solutions are powering the wireless networking revolution. At Skyworks, you will find a fast-paced environment with a strong focus on global collaboration, minimal layers of management and the freedom to make meaningful contributions in a setting that encourages creativity and out-of-the-box thinking. Our work culture values diversity, social responsibility, open communication, mutual trust and respect. We are excited about the opportunity to work with you and glad you want to be part of a team of talented individuals who together can change the way the world communicates. Requisition ID: 74460 Summary Job Description Digital design engineer developing complex mixed-signal ICs for frequency control, clock generation, network synchronization, and other timing applications. Candidate will take a supporting or leading role depending on experience relative to other team members, but regardless of experience level, candidate will be involved in all aspects of the design process from system conceptualization to mass production. For example, candidate will participate in digital system architecture, block- and system-level RTL design/coding, algorithm and firmware development, digital circuit back-end (e.g. synthesis, timing closure, P&R preparation, scan insertion), firmware development (some ICs include embedded processors), digital design verification, and full-chip mixed-signal verification. Responsibilities will also include detailed documentation, test vector development, lab test and evaluation, customer support, and other activities as required for the achievement of high volume production. Responsibilities Digital design specification, design, analysis, and HDL (Verilog) coding Behavioral modeling of analog and mixed signal circuits Digital back-end: synthesis, physical implementation (prep for P&R), static timing, scan insertion, etc. Verification of digital sub-systems, mixed-signal sub-systems, and the entire chip using a combination of digital models/RTL, firmware, and behavioral models. Test bench development Validation of silicon functionality, behavior, and performance Job Requirements Master's with 7-10 years of IC design experience or PhD with 4-6 years of IC design experience Strong motivation to contribute to all facets of chip design from conceptualization to release to production Working knowledge of digital IC circuit design in an HDL synthesis environment Working knowledge of digital verification and testing techniques Good verbal and written communication skills, positive attitude, desire to learn, and willingness to work on a team Working knowledge of UNIX operating systems Additional skills (one or more of these are highly desirable): Experience with digital design at geometries ranging from 130-40 nm Experience with digital IO interfaces such at I2C, SPI, etc. Competence in high-level languages (e.g. Matlab, C), scripting languages (e.g. Tcl, Perl, Python, SKILL), and version control systems (e.g. SVN, SOS) Working knowledge of System Verilog and/or UVM Experience leading a team of digital designers, either formally or informally Experience with embedded processor design and firmware/software development, especially for 8051 or ARM cores Competence in exploring digital and firmware system/architecture trade-offs such as memory size (ROM, RAM, FLASH, OTP, cache), clock speed, multiple clock domains, and the necessity for dedicated logic and DSP Experience with memory generators and MBIST Low power design and implementation techniques Familiarity with DSP techniques and algorithms Experience with Phase-locked-loops, Frequency Synthesizers or CDR circuits. Skyworks is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law.

Job Summary We are seeking a dynamic and driven Senior Account Manager to handle the TCL brand B2B business in Kollam & Trivandrum regions. The ideal candidate must have at least 1 year of experience in B2B sales , preferably in the consumer electronics/mobile/TV industry , and should be capable of independently managing dealer networks and driving regional growth. Key Responsibilities Develop and manage a strong dealer and distributor network for TCL products in Kollam & Trivandrum. Drive B2B sales of TCL TVs and other smart products by onboarding and activating new channel partners. Achieve monthly and quarterly sales and collection targets. Build strong relationships with channel partners to drive loyalty and business growth. Conduct regular market visits, dealer meetings, and promotional activities. Monitor competitor activities and provide actionable insights. Ensure timely billing, dispatch coordination, and payment collection. Maintain accurate reporting on sales, market conditions, and customer feedback. Candidate Requirements Minimum 1 year of experience in B2B sales (preferably in TV/mobile/electronics industry). Strong business acumen and negotiation skills. Proven ability to achieve targets and handle dealer accounts independently. Good communication and interpersonal skills. Proficiency in MS Office (Excel, Word, PowerPoint). Willing to travel extensively in Kollam and Trivandrum. What We Offer Work with a fast-growing national distributor of global technology brands. Competitive salary package with attractive incentives. Travel and communication allowances. Structured growth path and professional development. Energetic and collaborative work environment. About Company : Alps Distribution is Apple products authorised distribution company in Kerala and Tamil Nadu, headquartered in Cochin and have branches in Trivandrum, Thrissur and Calicut.Aldous Glare Tech & Energy (AGTE) is a sub company of ALPS.Aldous Glare, India’s leading distributor for Smartphone, Android TV, Google TV, Smart AC, Smart Washing Machine. For 30 years now, Aldous Glare Tech & Energy have stood the test of time and established ourselves as a brand synonymous with trust and quality. Technology and its advancements are ubiquitous and we function with the prime goal of increasing accessibility, awareness of the latest tech gadgets and appliances. We creates opportunities for its channel partners through aggressive market development and continuous improvements through agility. Company Website : www.aldousglare.com & www.alpsd.com Job Type: Full-time Pay: ₹27,000.00 - ₹30,000.00 per month Benefits: Cell phone reimbursement Flexible schedule Health insurance Internet reimbursement Leave encashment Provident Fund Schedule: Day shift Fixed shift Morning shift Supplemental Pay: Performance bonus Yearly bonus Work Location: Remote

The Infra Silicon team at Meta is responsible for designing and building in-house hardware accelerator Application-Specific Integrated Circuits (ASICs) to enhance Meta's computing efforts with capacity and efficiency at lower power and cost. The team focuses on creating domain-specific System on Chips (SoCs) that enable Meta's data centers to execute computationally-intensive workloads, such as video transcoding and AI/ML, with higher performance and lower energy consumption. They are organized into several key areas, including architecture & algorithms, design & micro-architecture, design verification, implementation & backend design, emulation/prototyping, and system on chip (SoC), which collaborate extensively with other teams to deliver comprehensive solutions for various technical domains. ASIC Engineer, Implementation Responsibilities: Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power. Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures Perform RTL Lint and work with the Designers to create waivers Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults Perform Flat and Hierarchical Clock Domain Crossing and work with the designers to analyze the complex clock domain crossings and sign off the CDC Perform Flat and Hierarchical Reset Domain crossing Checks. Understand the Reset-Architecture by working with Design and FW teams and develop reset groups and the corresponding reset sequence for RDC Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC. Analyze the inter-block timing and come up with IO budgets for the various partition blocks Develop Power Intent Specification in UPF for the multi-Vdd designs Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA, Power) Work closely with the Design Engineers, DV Engineers, Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback Minimum Qualifications: Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience 2+ years of experience in Design Integration and Front-End Implementation Experience with Register-Transfer Level (RTL) Synthesis and design optimization for Power, Performance, Area Knowledge of front-end and back-end ASIC tools. Experience with RTL design using SystemVerilog or other Hardware Description Language (HDL) Experience managing multiple design releases and working with cross functional teams to support and debug timing, area, power issues Experience with Electronic Design Automation (EDA) tools and scripting languages (Python, TCL) used to build tools and flows for complex environments. Experience with communicating across functional internal teams and vendors Preferred Qualifications: Experience Knowledge of Register-Transfer Level (RTL) coding using Verilog/System Verilog. Knowledge of Timing/physical libraries, Static Random Access Memory (SRAM) Experience with Power, Performance, Area Analysis and techniques for reducing power Knowledge of Clock Domain Crossing, Reset Domain Crossing, Logic Error Correction (LEC) Scripting and programming experience using Perl/Python, TCL, and Make Knowledge of Low power design. Experience with Design Compiler, Spyglass, PrimeTime, Formality or equivalent tools Synthesis Background, Timing Constraints Development, Floorplanning and Static Timing Analysis (STA) About Meta: Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics. Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.